drm/amd/display: Split program front end part that occur outside lock

[Why]
Eventually want to lock at a higher level in stack.
To do this, we need to be able to isolate the parts that need to be done
after pipe unlock.

[How]
Split out programming that is done post unlock.

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 073172e53b5bf9df8985ed207da2f01663a03f05..738ba91220df59eb777a385bfe63d6a05c635912 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -786,11 +786,15 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
                if (should_disable && old_stream) {
                        dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
                        disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
-                       if (dc->hwss.apply_ctx_for_surface)
+                       if (dc->hwss.apply_ctx_for_surface) {
                                dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
+                               dc->hwss.post_unlock_program_front_end(dc, dangling_context);
+                       }
+                       if (dc->hwss.program_front_end_for_ctx) {
+                               dc->hwss.program_front_end_for_ctx(dc, dangling_context);
+                               dc->hwss.post_unlock_program_front_end(dc, dangling_context);
+                       }
                }
-               if (dc->hwss.program_front_end_for_ctx)
-                       dc->hwss.program_front_end_for_ctx(dc, dangling_context);
        }
 
        current_ctx = dc->current_state;
@@ -1219,6 +1223,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
                                dc, context->streams[i],
                                context->stream_status[i].plane_count,
                                context); /* use new pipe config in new context */
+                       dc->hwss.post_unlock_program_front_end(dc, context);
                }
 
        /* Program hardware */
@@ -1238,19 +1243,24 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
        }
 
        /* Program all planes within new context*/
-       if (dc->hwss.program_front_end_for_ctx)
+       if (dc->hwss.program_front_end_for_ctx) {
                dc->hwss.program_front_end_for_ctx(dc, context);
+               dc->hwss.post_unlock_program_front_end(dc, context);
+       }
+
        for (i = 0; i < context->stream_count; i++) {
                const struct dc_link *link = context->streams[i]->link;
 
                if (!context->streams[i]->mode_changed)
                        continue;
 
-               if (dc->hwss.apply_ctx_for_surface)
+               if (dc->hwss.apply_ctx_for_surface) {
                        dc->hwss.apply_ctx_for_surface(
                                        dc, context->streams[i],
                                        context->stream_status[i].plane_count,
                                        context);
+                       dc->hwss.post_unlock_program_front_end(dc, context);
+               }
 
                /*
                 * enable stereo
@@ -2183,6 +2193,7 @@ static void commit_planes_for_stream(struct dc *dc,
                if (dc->hwss.program_front_end_for_ctx)
                        dc->hwss.program_front_end_for_ctx(dc, context);
 
+               dc->hwss.post_unlock_program_front_end(dc, context);
                return;
        }
 
@@ -2315,6 +2326,9 @@ static void commit_planes_for_stream(struct dc *dc,
                dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
        }
 
+       if (update_type != UPDATE_TYPE_FAST)
+               dc->hwss.post_unlock_program_front_end(dc, context);
+
        // Fire manual trigger only when bottom plane is flipped
        for (j = 0; j < dc->res_pool->pipe_count; j++) {
                struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 5b689273ff4403ccf8fd2538abb643fc726c290a..a961b94aefd9c891509b7a9e7fc85927921da2a1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2621,6 +2621,11 @@ static void dce110_apply_ctx_for_surface(
                enable_fbc(dc, context);
 }
 
+static void dce110_post_unlock_program_front_end(
+               struct dc *dc,
+               struct dc_state *context)
+{
+}
 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
        struct dce_hwseq *hws = dc->hwseq;
@@ -2722,6 +2727,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
        .init_hw = init_hw,
        .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
        .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
+       .post_unlock_program_front_end = dce110_post_unlock_program_front_end,
        .update_plane_addr = update_plane_addr,
        .update_pending_status = dce110_update_pending_status,
        .enable_accelerated_mode = dce110_enable_accelerated_mode,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 1008ac8a0f2afb8bf637aa8601eed3bf19214388..a9a5a13d5edf741ba4d4948ce1dfae66cc806c30 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2512,7 +2512,6 @@ void dcn10_apply_ctx_for_surface(
        int i;
        struct timing_generator *tg;
        uint32_t underflow_check_delay_us;
-       bool removed_pipe[4] = { false };
        bool interdependent_update = false;
        struct pipe_ctx *top_pipe_to_program =
                        dcn10_find_top_pipe_for_stream(dc, context, stream);
@@ -2552,6 +2551,9 @@ void dcn10_apply_ctx_for_surface(
                struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
                struct pipe_ctx *old_pipe_ctx =
                                &dc->current_state->res_ctx.pipe_ctx[i];
+
+               pipe_ctx->update_flags.raw = 0;
+
                /*
                 * Powergate reused pipes that are not powergated
                 * fairly hacky right now, using opp_id as indicator
@@ -2571,7 +2573,7 @@ void dcn10_apply_ctx_for_surface(
                    old_pipe_ctx->stream_res.tg == tg) {
 
                        hws->funcs.plane_atomic_disconnect(dc, old_pipe_ctx);
-                       removed_pipe[i] = true;
+                       pipe_ctx->update_flags.bits.disable = 1;
 
                        DC_LOG_DC("Reset mpcc for pipe %d\n",
                                        old_pipe_ctx->pipe_idx);
@@ -2602,16 +2604,41 @@ void dcn10_apply_ctx_for_surface(
                dcn10_lock_all_pipes(dc, context, false);
        else
                dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
+}
+
+void dcn10_post_unlock_program_front_end(
+               struct dc *dc,
+               struct dc_state *context)
+{
+       int i, j;
+
+       DC_LOGGER_INIT(dc->ctx->logger);
 
-       if (num_planes == 0)
-               false_optc_underflow_wa(dc, stream, tg);
+       for (i = 0; i < dc->res_pool->pipe_count; i++) {
+               struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+               if (!pipe_ctx->top_pipe &&
+                       !pipe_ctx->prev_odm_pipe &&
+                       pipe_ctx->stream) {
+                       struct dc_stream_status *stream_status = NULL;
+                       struct timing_generator *tg = pipe_ctx->stream_res.tg;
+
+                       for (j = 0; j < context->stream_count; j++) {
+                               if (pipe_ctx->stream == context->streams[j])
+                                       stream_status = &context->stream_status[j];
+                       }
+
+                       if (context->stream_status[i].plane_count == 0)
+                               false_optc_underflow_wa(dc, pipe_ctx->stream, tg);
+               }
+       }
 
        for (i = 0; i < dc->res_pool->pipe_count; i++)
-               if (removed_pipe[i])
+               if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
                        dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
 
        for (i = 0; i < dc->res_pool->pipe_count; i++)
-               if (removed_pipe[i]) {
+               if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) {
                        dc->hwss.optimize_bandwidth(dc, context);
                        break;
                }

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index 4d20f6586bb57e49de2f83de58428119a4fc9b26..b523f0b8dc23f9b5c7296c78524222a24b8585da 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -75,6 +75,9 @@ void dcn10_apply_ctx_for_surface(
                const struct dc_stream_state *stream,
                int num_planes,
                struct dc_state *context);
+void dcn10_post_unlock_program_front_end(
+               struct dc *dc,
+               struct dc_state *context);
 void dcn10_hubp_pg_control(
                struct dce_hwseq *hws,
                unsigned int hubp_inst,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
index e7e5352ec424b36aa64a62dd79c631cc611e17be..681db997a532390a570c0bd58a5a4af54ba6199a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
@@ -32,6 +32,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
        .init_hw = dcn10_init_hw,
        .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
        .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
+       .post_unlock_program_front_end = dcn10_post_unlock_program_front_end,
        .update_plane_addr = dcn10_update_plane_addr,
        .update_dchub = dcn10_update_dchub,
        .update_pending_status = dcn10_update_pending_status,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index a444fed94184919c51bded44ebb4eaafd3db117b..f36c4d1b7c301dc316e48ae024c3d0f30b757342 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1551,7 +1551,6 @@ void dcn20_program_front_end_for_ctx(
                struct dc *dc,
                struct dc_state *context)
 {
-       const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
        int i;
        struct dce_hwseq *hws = dc->hwseq;
        bool pipe_locked[MAX_PIPES] = {false};
@@ -1626,6 +1625,16 @@ void dcn20_program_front_end_for_ctx(
                        if (!pipe_ctx->update_flags.bits.enable)
                                dc->hwss.pipe_control_lock(dc, &dc->current_state->res_ctx.pipe_ctx[i], false);
                }
+}
+
+void dcn20_post_unlock_program_front_end(
+               struct dc *dc,
+               struct dc_state *context)
+{
+       int i;
+       const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
+
+       DC_LOGGER_INIT(dc->ctx->logger);
 
        for (i = 0; i < dc->res_pool->pipe_count; i++)
                if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
index 02c9be5ebd47480ecfe6029f9831522f85159388..80f192b8b3a2ca6a4152c3aab936b8a597a06dc3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
@@ -35,6 +35,9 @@ bool dcn20_set_shaper_3dlut(
 void dcn20_program_front_end_for_ctx(
                struct dc *dc,
                struct dc_state *context);
+void dcn20_post_unlock_program_front_end(
+               struct dc *dc,
+               struct dc_state *context);
 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
index d51e02fdab4d3eb427e310dbde23122b5b162d86..cb0cb999251e92ddf22176be4322f1a6d444d8c0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
@@ -33,6 +33,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
        .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
        .apply_ctx_for_surface = NULL,
        .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+       .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
        .update_plane_addr = dcn20_update_plane_addr,
        .update_dchub = dcn10_update_dchub,
        .update_pending_status = dcn10_update_pending_status,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
index 4861aa5c59aefd4ba3962d14b68d0bd0ff5c88b5..4963a540948d5826ff56d11239f3e9bbfc1733b3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
@@ -34,6 +34,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
        .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
        .apply_ctx_for_surface = NULL,
        .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+       .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
        .update_plane_addr = dcn20_update_plane_addr,
        .update_dchub = dcn10_update_dchub,
        .update_pending_status = dcn10_update_pending_status,

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 209118f9f19358558a911d337a9b9f72144db561..63919866ba38ee877ab3362bfedb95d20fdbdc53 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -66,6 +66,8 @@ struct hw_sequencer_funcs {
                        int num_planes, struct dc_state *context);
        void (*program_front_end_for_ctx)(struct dc *dc,
                        struct dc_state *context);
+       void (*post_unlock_program_front_end)(struct dc *dc,
+                       struct dc_state *context);
        void (*update_plane_addr)(const struct dc *dc,
                        struct pipe_ctx *pipe_ctx);
        void (*update_dchub)(struct dce_hwseq *hws,