mt76: mt7915: enable HE UL MU-MIMO
authorShayne Chen <shayne.chen@mediatek.com>
Mon, 18 Oct 2021 08:09:38 +0000 (16:09 +0800)
committerFelix Fietkau <nbd@nbd.name>
Wed, 20 Oct 2021 08:37:04 +0000 (10:37 +0200)
Enable HE UL MU-MIMO in sta_rec_muru, which works on both ap and station
mode.

For sending trigger frames, one of the conditions fw uses is to check if
mib rx airtime meets the threshold.
There's a main control of mib rx airtime report register in fw, so we
need to enable the register by mcu cmd instead of directly writing it,
otherwise it will still be disabled by fw.

Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
drivers/net/wireless/mediatek/mt76/mt7915/init.c
drivers/net/wireless/mediatek/mt76/mt7915/mcu.c
drivers/net/wireless/mediatek/mt76/mt7915/mcu.h
drivers/net/wireless/mediatek/mt76/mt7915/regs.h

index 85afe965169ec708988da9a5ee8c04bd240c136f..7bb7e97427551584ad42eea302407ab1c3fc8dbd 100644 (file)
@@ -386,8 +386,6 @@ mt7915_mac_init_band(struct mt7915_dev *dev, u8 band)
              FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF);
        mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set);
 
-       mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(band), MT_WF_RMAC_MIB_RXTIME_EN);
-
        mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 1536);
        /* disable rx rate report by default due to hw issues */
        mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN);
index d4c8759bedd84903ec13c6200963f053624bf7bd..8ba60b66e4a92828259b6467475b5a8acbc6fe9e 100644 (file)
@@ -1534,6 +1534,7 @@ mt7915_mcu_sta_muru_tlv(struct sk_buff *skb, struct ieee80211_sta *sta,
                               mvif->cap.he_mu_ebfer ||
                               mvif->cap.vht_mu_ebfer ||
                               mvif->cap.vht_mu_ebfee;
+       muru->cfg.mimo_ul_en = true;
 
        muru->ofdma_dl.punc_pream_rx =
                HE_PHY(CAP1_PREAMBLE_PUNC_RX_MASK, elem->phy_cap_info[1]);
@@ -2921,6 +2922,47 @@ int mt7915_mcu_set_muru_ctrl(struct mt7915_dev *dev, u32 cmd, u32 val)
                                 sizeof(req), false);
 }
 
+static int
+mt7915_mcu_init_rx_airtime(struct mt7915_dev *dev)
+{
+#define RX_AIRTIME_FEATURE_CTRL                1
+#define RX_AIRTIME_BITWISE_CTRL                2
+#define RX_AIRTIME_CLEAR_EN    1
+       struct {
+               __le16 field;
+               __le16 sub_field;
+               __le32 set_status;
+               __le32 get_status;
+               u8 _rsv[12];
+
+               bool airtime_en;
+               bool mibtime_en;
+               bool earlyend_en;
+               u8 _rsv1[9];
+
+               bool airtime_clear;
+               bool mibtime_clear;
+               u8 _rsv2[98];
+       } __packed req = {
+               .field = cpu_to_le16(RX_AIRTIME_BITWISE_CTRL),
+               .sub_field = cpu_to_le16(RX_AIRTIME_CLEAR_EN),
+               .airtime_clear = true,
+       };
+       int ret;
+
+       ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RX_AIRTIME_CTRL), &req,
+                               sizeof(req), true);
+       if (ret)
+               return ret;
+
+       req.field = cpu_to_le16(RX_AIRTIME_FEATURE_CTRL);
+       req.sub_field = cpu_to_le16(RX_AIRTIME_CLEAR_EN);
+       req.airtime_en = true;
+
+       return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RX_AIRTIME_CTRL), &req,
+                                sizeof(req), true);
+}
+
 int mt7915_mcu_init(struct mt7915_dev *dev)
 {
        static const struct mt76_mcu_ops mt7915_mcu_ops = {
@@ -2955,6 +2997,10 @@ int mt7915_mcu_init(struct mt7915_dev *dev)
        if (ret)
                return ret;
 
+       ret = mt7915_mcu_init_rx_airtime(dev);
+       if (ret)
+               return ret;
+
        return mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
                                 MCU_WA_PARAM_RED, 0, 0);
 }
index 4043cf547c9e82bbac60f8f9ec2d4e623c2c3bf1..d66918d914da1c2350d45f54d9182697c098ba1d 100644 (file)
@@ -271,6 +271,7 @@ enum {
        MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
        MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
        MCU_EXT_CMD_MUAR_UPDATE = 0x48,
+       MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a,
        MCU_EXT_CMD_SET_RX_PATH = 0x4e,
        MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
        MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
index 6771870a867c824a9092c743cdb8d183a9705b45..a2e98788f421dc88915d4b4fe06100cdf656a90c 100644 (file)
 
 #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380)
 #define MT_WF_RMAC_MIB_RXTIME_CLR      BIT(31)
-#define MT_WF_RMAC_MIB_RXTIME_EN       BIT(30)
 
 /* WFDMA0 */
 #define MT_WFDMA0_BASE                 0xd4000