arm64: dts: imx8m: add mu node
authorPeng Fan <peng.fan@nxp.com>
Mon, 1 Jun 2020 08:20:01 +0000 (16:20 +0800)
committerShawn Guo <shawnguo@kernel.org>
Tue, 23 Jun 2020 06:50:39 +0000 (14:50 +0800)
Add mu node to let A53 could communicate with M Core.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm64/boot/dts/freescale/imx8mm.dtsi
arch/arm64/boot/dts/freescale/imx8mn.dtsi
arch/arm64/boot/dts/freescale/imx8mp.dtsi
arch/arm64/boot/dts/freescale/imx8mq.dtsi

index 6a85ae340ee14a8036ae99c231f81c20f1e624f3..76f040e4be5e97ee1e649d0bcd062eaa812d8b46 100644 (file)
                                status = "disabled";
                        };
 
+                       mu: mailbox@30aa0000 {
+                               compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
+                               reg = <0x30aa0000 0x10000>;
+                               interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_MU_ROOT>;
+                               #mbox-cells = <2>;
+                       };
+
                        usdhc1: mmc@30b40000 {
                                compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
                                reg = <0x30b40000 0x10000>;
index 0625cc880ccceb42c2bc463109f3c93f70b2dd8b..9385dd7d1a2f7f03646fc7a751777a547d326e92 100644 (file)
                                status = "disabled";
                        };
 
+                       mu: mailbox@30aa0000 {
+                               compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
+                               reg = <0x30aa0000 0x10000>;
+                               interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MN_CLK_MU_ROOT>;
+                               #mbox-cells = <2>;
+                       };
+
                        usdhc1: mmc@30b40000 {
                                compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
                                reg = <0x30b40000 0x10000>;
index d35cb7ee6c354b3faeec2ce77d26d3443cd17597..f6591c69322627f675db9db228577d07b3f469fe 100644 (file)
                                status = "disabled";
                        };
 
+                       mu: mailbox@30aa0000 {
+                               compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
+                               reg = <0x30aa0000 0x10000>;
+                               interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MP_CLK_MU_ROOT>;
+                               #mbox-cells = <2>;
+                       };
+
                        i2c5: i2c@30ad0000 {
                                compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
                                #address-cells = <1>;
index 2cb8f0c74f8c2a79b75ae1cf88479895af358dcf..f70435cf9ad57c123339ebcc63b9776ed0f8af03 100644 (file)
                                status = "disabled";
                        };
 
+                       mu: mailbox@30aa0000 {
+                               compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
+                               reg = <0x30aa0000 0x10000>;
+                               interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
+                               #mbox-cells = <2>;
+                       };
+
                        usdhc1: mmc@30b40000 {
                                compatible = "fsl,imx8mq-usdhc",
                                             "fsl,imx7d-usdhc";