ARM: dts: uniphier: rename cache controller nodes to follow json-schema

Follow the standard nodename pattern
"^(cache-controller|cpu)(@[0-9a-f,]+)*$" defined in
schemas/cache-controller.yaml of dt-schema.

Otherwise, after the dt-binding is converted to json-schema,
'make ARCH=arm dtbs_check' will show warnings like this:

  l2-cache@500c0000: $nodename:0: 'l2-cache@500c0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index 197bee7d8b7fc1823357ed1b96284826b047fa7b..06e7400d29409a61ff92b4770787392a3f155237 100644 (file)
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -51,7 +51,7 @@
                ranges;
                interrupt-parent = <&intc>;
 
-               l2: l2-cache@500c0000 {
+               l2: cache-controller@500c0000 {
                        compatible = "socionext,uniphier-system-cache";
                        reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
                              <0x506c0000 0x400>;

diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index b02bc8a6346bf90242229a1461c4731453f5aa18..1c866f0306fc95dfc58fc7abbb4643bff56fa4ce 100644 (file)
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -59,7 +59,7 @@
                ranges;
                interrupt-parent = <&intc>;
 
-               l2: l2-cache@500c0000 {
+               l2: cache-controller@500c0000 {
                        compatible = "socionext,uniphier-system-cache";
                        reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
                              <0x506c0000 0x400>;

diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index f84a43a10f38ede3de039582cf3a5c6fdfaa70b3..da772429b55a7e74664dd15c69267d9a3308864c 100644 (file)
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -131,7 +131,7 @@
                ranges;
                interrupt-parent = <&intc>;
 
-               l2: l2-cache@500c0000 {
+               l2: cache-controller@500c0000 {
                        compatible = "socionext,uniphier-system-cache";
                        reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
                              <0x506c0000 0x400>;
@@ -144,7 +144,7 @@
                        next-level-cache = <&l3>;
                };
 
-               l3: l3-cache@500c8000 {
+               l3: cache-controller@500c8000 {
                        compatible = "socionext,uniphier-system-cache";
                        reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
                              <0x506c8000 0x400>;

diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 989b2a241822c509d549372083f095fa0f94f2f7..7044f8700cb2071983e1d8e2bded6b945ed76478 100644 (file)
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -157,7 +157,7 @@
                ranges;
                interrupt-parent = <&intc>;
 
-               l2: l2-cache@500c0000 {
+               l2: cache-controller@500c0000 {
                        compatible = "socionext,uniphier-system-cache";
                        reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
                              <0x506c0000 0x400>;

diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index fbfd25050a049d0a899d713ff0099117bf3994b6..09992163e1f4b1a6e87dfadf2eacaf4ec3a73402 100644 (file)
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -51,7 +51,7 @@
                ranges;
                interrupt-parent = <&intc>;
 
-               l2: l2-cache@500c0000 {
+               l2: cache-controller@500c0000 {
                        compatible = "socionext,uniphier-system-cache";
                        reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
                              <0x506c0000 0x400>;