#define SX9360_REG_GNRL_REG_2_FREQ(_r)  (SX9360_FOSC_HZ / ((_r) * 8192))
 
 #define SX9360_REG_AFE_CTRL1           0x21
+#define SX9360_REG_AFE_CTRL1_RESFILTIN_MASK GENMASK(3, 0)
+#define SX9360_REG_AFE_CTRL1_RESFILTIN_0OHMS 0
 #define SX9360_REG_AFE_PARAM0_PHR      0x22
 #define SX9360_REG_AFE_PARAM1_PHR      0x23
 #define SX9360_REG_AFE_PARAM0_PHM      0x24
        { SX9360_REG_GNRL_CTRL1, 0x00 },
        { SX9360_REG_GNRL_CTRL2, SX9360_REG_GNRL_CTRL2_PERIOD_102MS },
 
-       { SX9360_REG_AFE_CTRL1, 0x00 },
+       { SX9360_REG_AFE_CTRL1, SX9360_REG_AFE_CTRL1_RESFILTIN_0OHMS },
        { SX9360_REG_AFE_PARAM0_PHR, SX9360_REG_AFE_PARAM0_RSVD |
                SX9360_REG_AFE_PARAM0_RESOLUTION_128 },
        { SX9360_REG_AFE_PARAM1_PHR, SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF |
 
        memcpy(reg_def, &sx9360_default_regs[idx], sizeof(*reg_def));
        switch (reg_def->reg) {
+       case SX9360_REG_AFE_CTRL1:
+               ret = device_property_read_u32(dev,
+                               "semtech,input-precharge-resistor-ohms",
+                               &raw);
+               if (ret)
+                       break;
+
+               reg_def->def &= ~SX9360_REG_AFE_CTRL1_RESFILTIN_MASK;
+               reg_def->def |= FIELD_PREP(SX9360_REG_AFE_CTRL1_RESFILTIN_MASK,
+                                          raw / 2000);
+               break;
        case SX9360_REG_AFE_PARAM0_PHR:
        case SX9360_REG_AFE_PARAM0_PHM:
                ret = device_property_read_u32(dev, "semtech,resolution", &raw);