ce can also trigger interrupt, and even both ce and ue error can be
found in one ras query, distinguishing between ce and ue in interrupt
handler is uncessary.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Suggested-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
                         * But leave IP do that recovery, here we just dispatch
                         * the error.
                         */
-                       if (ret == AMDGPU_RAS_UE) {
+                       if (ret == AMDGPU_RAS_SUCCESS) {
                                /* these counts could be left as 0 if
                                 * some blocks do not count error number
                                 */
 
        if (adev->gfx.funcs->query_ras_error_count)
                adev->gfx.funcs->query_ras_error_count(adev, err_data);
        amdgpu_ras_reset_gpu(adev, 0);
-       return AMDGPU_RAS_UE;
+       return AMDGPU_RAS_SUCCESS;
 }
 
 static const struct {
 
        if (err_data->ue_count)
                amdgpu_ras_reset_gpu(adev, 0);
 
-       return AMDGPU_RAS_UE;
+       return AMDGPU_RAS_SUCCESS;
 }
 
 static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev,
 
 
        amdgpu_ras_reset_gpu(adev, 0);
 
-       return AMDGPU_RAS_UE;
+       return AMDGPU_RAS_SUCCESS;
 }
 
 static int sdma_v4_0_process_ecc_irq(struct amdgpu_device *adev,