u8 *pos;
        off_t offs;
 
-       chunk = idx / IOAT_DESCS_PER_2M;
-       idx &= (IOAT_DESCS_PER_2M - 1);
+       chunk = idx / IOAT_DESCS_PER_CHUNK;
+       idx &= (IOAT_DESCS_PER_CHUNK - 1);
        offs = idx * IOAT_DESC_SZ;
        pos = (u8 *)ioat_chan->descs[chunk].virt + offs;
        phys = ioat_chan->descs[chunk].hw + offs;
        if (!ring)
                return NULL;
 
-       ioat_chan->desc_chunks = chunks = (total_descs * IOAT_DESC_SZ) / SZ_2M;
+       chunks = (total_descs * IOAT_DESC_SZ) / IOAT_CHUNK_SIZE;
+       ioat_chan->desc_chunks = chunks;
 
        for (i = 0; i < chunks; i++) {
                struct ioat_descs *descs = &ioat_chan->descs[i];
 
                        for (idx = 0; idx < i; idx++) {
                                descs = &ioat_chan->descs[idx];
-                               dma_free_coherent(to_dev(ioat_chan), SZ_2M,
-                                                 descs->virt, descs->hw);
+                               dma_free_coherent(to_dev(ioat_chan),
+                                               IOAT_CHUNK_SIZE,
+                                               descs->virt, descs->hw);
                                descs->virt = NULL;
                                descs->hw = 0;
                        }
 
                        for (idx = 0; idx < ioat_chan->desc_chunks; idx++) {
                                dma_free_coherent(to_dev(ioat_chan),
-                                                 SZ_2M,
+                                                 IOAT_CHUNK_SIZE,
                                                  ioat_chan->descs[idx].virt,
                                                  ioat_chan->descs[idx].hw);
                                ioat_chan->descs[idx].virt = NULL;
 
        u32 msixpba;
 };
 
+#define IOAT_MAX_ORDER 16
+#define IOAT_MAX_DESCS (1 << IOAT_MAX_ORDER)
+#define IOAT_CHUNK_SIZE (SZ_2M)
+#define IOAT_DESCS_PER_CHUNK (IOAT_CHUNK_SIZE / IOAT_DESC_SZ)
+
 struct ioat_descs {
        void *virt;
        dma_addr_t hw;
        u16 produce;
        struct ioat_ring_ent **ring;
        spinlock_t prep_lock;
-       struct ioat_descs descs[2];
+       struct ioat_descs descs[IOAT_MAX_DESCS / IOAT_DESCS_PER_CHUNK];
        int desc_chunks;
        int intr_coalesce;
        int prev_intr_coalesce;
        return !!err;
 }
 
-#define IOAT_MAX_ORDER 16
-#define IOAT_MAX_DESCS 65536
-#define IOAT_DESCS_PER_2M 32768
 
 static inline u32 ioat_ring_size(struct ioatdma_chan *ioat_chan)
 {
 
        }
 
        for (i = 0; i < ioat_chan->desc_chunks; i++) {
-               dma_free_coherent(to_dev(ioat_chan), SZ_2M,
+               dma_free_coherent(to_dev(ioat_chan), IOAT_CHUNK_SIZE,
                                  ioat_chan->descs[i].virt,
                                  ioat_chan->descs[i].hw);
                ioat_chan->descs[i].virt = NULL;