if (freq == gmu->gpu_freqs[perf_index])
                        break;
 
+       gmu->current_perf_index = perf_index;
+
        __a6xx_gmu_set_freq(gmu, perf_index);
 }
 
        gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK);
        enable_irq(gmu->hfi_irq);
 
-       /* Set the GPU to the highest power frequency */
-       __a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1);
+       /* Set the GPU to the current freq */
+       __a6xx_gmu_set_freq(gmu, gmu->current_perf_index);
 
        /*
         * "enable" the GX power domain which won't actually do anything but it
        gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev,
                gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs));
 
+       gmu->current_perf_index = gmu->nr_gpu_freqs - 1;
+
        /* Build the list of RPMh votes that we'll send to the GMU */
        return a6xx_gmu_rpmh_votes_init(gmu);
 }
 
        struct clk_bulk_data *clocks;
        struct clk *core_clk;
 
+       /* current performance index set externally */
+       int current_perf_index;
+
        int nr_gpu_freqs;
        unsigned long gpu_freqs[16];
        u32 gx_arc_votes[16];