int i, r;
 
        INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
+       mutex_init(&adev->vcn.vcn_pg_lock);
+       atomic_set(&adev->vcn.total_submission_cnt, 0);
 
        switch (adev->asic_type) {
        case CHIP_RAVEN:
        }
 
        release_firmware(adev->vcn.fw);
+       mutex_destroy(&adev->vcn.vcn_pg_lock);
 
        return 0;
 }
                fences += fence[j];
        }
 
-       if (fences == 0) {
+       if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
                amdgpu_gfx_off_ctrl(adev, true);
                amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
                       AMD_PG_STATE_GATE);
 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 {
        struct amdgpu_device *adev = ring->adev;
-       bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
 
-       if (set_clocks) {
-               amdgpu_gfx_off_ctrl(adev, false);
-               amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
-                      AMD_PG_STATE_UNGATE);
-       }
+       atomic_inc(&adev->vcn.total_submission_cnt);
+       cancel_delayed_work_sync(&adev->vcn.idle_work);
+
+       mutex_lock(&adev->vcn.vcn_pg_lock);
+       amdgpu_gfx_off_ctrl(adev, false);
+       amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
+              AMD_PG_STATE_UNGATE);
 
        if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
                struct dpg_pause_state new_state;
 
                adev->vcn.pause_dpg_mode(adev, ring->me, &new_state);
        }
+       mutex_unlock(&adev->vcn.vcn_pg_lock);
 }
 
 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
 {
+       atomic_dec(&ring->adev->vcn.total_submission_cnt);
+
        schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 }