arm64: dts: qcom: sm6350: Add GPU nodes

Add Adreno, GPU SMMU and GMU nodes to hook up everything that
the A619 needs to function properly.

Co-developed-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-5-afcdfb18bb13@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index c0f34bc1d78c1c9cf121a460a28ade27196de91a..d928e64e33ae88233bc9b50d0b4a8df7220755dc 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1321,6 +1321,145 @@
                        };
                };
 
+               gpu: gpu@3d00000 {
+                       compatible = "qcom,adreno-619.0", "qcom,adreno";
+                       reg = <0 0x03d00000 0 0x40000>,
+                             <0 0x03d9e000 0 0x1000>;
+                       reg-names = "kgsl_3d0_reg_memory",
+                                   "cx_mem";
+                       interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+                       iommus = <&adreno_smmu 0>;
+                       operating-points-v2 = <&gpu_opp_table>;
+                       qcom,gmu = <&gmu>;
+                       nvmem-cells = <&gpu_speed_bin>;
+                       nvmem-cell-names = "speed_bin";
+
+                       status = "disabled";
+
+                       zap-shader {
+                               memory-region = <&pil_gpu_mem>;
+                       };
+
+                       gpu_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-850000000 {
+                                       opp-hz = /bits/ 64 <850000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+                                       opp-supported-hw = <0x02>;
+                               };
+
+                               opp-800000000 {
+                                       opp-hz = /bits/ 64 <800000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+                                       opp-supported-hw = <0x04>;
+                               };
+
+                               opp-650000000 {
+                                       opp-hz = /bits/ 64 <650000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+                                       opp-supported-hw = <0x08>;
+                               };
+
+                               opp-565000000 {
+                                       opp-hz = /bits/ 64 <565000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+                                       opp-supported-hw = <0x10>;
+                               };
+
+                               opp-430000000 {
+                                       opp-hz = /bits/ 64 <430000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+                                       opp-supported-hw = <0xff>;
+                               };
+
+                               opp-355000000 {
+                                       opp-hz = /bits/ 64 <355000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+                                       opp-supported-hw = <0xff>;
+                               };
+
+                               opp-253000000 {
+                                       opp-hz = /bits/ 64 <253000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+                                       opp-supported-hw = <0xff>;
+                               };
+                       };
+               };
+
+               adreno_smmu: iommu@3d40000 {
+                       compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
+                       reg = <0 0x03d40000 0 0x10000>;
+                       #iommu-cells = <1>;
+                       #global-interrupts = <2>;
+                       interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+
+                       clocks = <&gpucc GPU_CC_AHB_CLK>,
+                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+                                <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
+                       clock-names = "ahb",
+                                     "bus",
+                                     "iface";
+
+                       power-domains = <&gpucc GPU_CX_GDSC>;
+               };
+
+               gmu: gmu@3d6a000 {
+                       compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
+                       reg = <0 0x03d6a000 0 0x31000>,
+                             <0 0x0b290000 0 0x10000>,
+                             <0 0x0b490000 0 0x10000>;
+                       reg-names = "gmu",
+                                   "gmu_pdc",
+                                   "gmu_pdc_seq";
+
+                       interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "hfi",
+                                         "gmu";
+
+                       clocks = <&gpucc GPU_CC_AHB_CLK>,
+                                <&gpucc GPU_CC_CX_GMU_CLK>,
+                                <&gpucc GPU_CC_CXO_CLK>,
+                                <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+                       clock-names = "ahb",
+                                     "gmu",
+                                     "cxo",
+                                     "axi",
+                                     "memnoc";
+
+                       power-domains = <&gpucc GPU_CX_GDSC>,
+                                       <&gpucc GPU_GX_GDSC>;
+                       power-domain-names = "cx",
+                                            "gx";
+
+                       iommus = <&adreno_smmu 5>;
+
+                       operating-points-v2 = <&gmu_opp_table>;
+
+                       status = "disabled";
+
+                       gmu_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-200000000 {
+                                       opp-hz = /bits/ 64 <200000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+                               };
+                       };
+               };
+
                gpucc: clock-controller@3d90000 {
                        compatible = "qcom,sm6350-gpucc";
                        reg = <0 0x03d90000 0 0x9000>;