clk: qcom: videocc-sm8350: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value is known for SM8350, see [1].

[1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-16-c37eba13b5ce@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-sm8350.c
index 7246f3c994922ec34464b2745c29bb684939cd5e..8db2bb9955585bdf74de041d645e3c9dcfefabea 100644 (file)
--- a/drivers/clk/qcom/videocc-sm8350.c
+++ b/drivers/clk/qcom/videocc-sm8350.c
@@ -488,10 +488,10 @@ static struct clk_regmap *video_cc_sm8350_clocks[] = {
 static const struct qcom_reset_map video_cc_sm8350_resets[] = {
        [VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 },
        [VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 },
-       [VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 },
+       [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0xc34, .bit = 2, .udelay = 400 },
        [VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 },
        [VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 },
-       [VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 },
+       [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0xcd4, .bit = 2, .udelay = 400 },
        [VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 },
 };