ARM: dts: rockchip: Add ethernet rgmiim1 pin-control for rv1126

Add ethernet pin-control for rv1126 SoC.

Co-Developed-by: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Link: https://lore.kernel.org/r/20230111172437.5295-2-anand@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rv1126-pinctrl.dtsi
index 4bc419cc1210383cacc627248d9088ea6aff0b73..b77021772781d22699d92735428c00708dc6933b 100644 (file)
--- a/arch/arm/boot/dts/rv1126-pinctrl.dtsi
+++ b/arch/arm/boot/dts/rv1126-pinctrl.dtsi
@@ -11,6 +11,14 @@
  * by adding changes at end of this file.
  */
 &pinctrl {
+       clk_out_ethernet {
+               /omit-if-no-ref/
+               clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
+                       rockchip,pins =
+                               /* clk_out_ethernet_m1 */
+                               <2 RK_PC5 2 &pcfg_pull_none>;
+               };
+       };
        emmc {
                /omit-if-no-ref/
                emmc_rstnout: emmc-rstnout {
@@ -61,6 +69,40 @@
                                <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
                };
        };
+       rgmii {
+               /omit-if-no-ref/
+               rgmiim1_pins: rgmiim1-pins {
+                       rockchip,pins =
+                               /* rgmii_mdc_m1 */
+                               <2 RK_PC2 2 &pcfg_pull_none>,
+                               /* rgmii_mdio_m1 */
+                               <2 RK_PC1 2 &pcfg_pull_none>,
+                               /* rgmii_rxclk_m1 */
+                               <2 RK_PD3 2 &pcfg_pull_none>,
+                               /* rgmii_rxd0_m1 */
+                               <2 RK_PB5 2 &pcfg_pull_none>,
+                               /* rgmii_rxd1_m1 */
+                               <2 RK_PB6 2 &pcfg_pull_none>,
+                               /* rgmii_rxd2_m1 */
+                               <2 RK_PC7 2 &pcfg_pull_none>,
+                               /* rgmii_rxd3_m1 */
+                               <2 RK_PD0 2 &pcfg_pull_none>,
+                               /* rgmii_rxdv_m1 */
+                               <2 RK_PB4 2 &pcfg_pull_none>,
+                               /* rgmii_txclk_m1 */
+                               <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>,
+                               /* rgmii_txd0_m1 */
+                               <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>,
+                               /* rgmii_txd1_m1 */
+                               <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>,
+                               /* rgmii_txd2_m1 */
+                               <2 RK_PD1 2 &pcfg_pull_none_drv_level_3>,
+                               /* rgmii_txd3_m1 */
+                               <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>,
+                               /* rgmii_txen_m1 */
+                               <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>;
+               };
+       };
        sdmmc0 {
                /omit-if-no-ref/
                sdmmc0_bus4: sdmmc0-bus4 {