unsigned char priority[32];
};
-struct omap_intr_handler_s {
+struct OMAPIntcState {
SysBusDevice parent_obj;
qemu_irq *pins;
struct omap_intr_handler_bank_s bank[3];
};
-static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
+static void omap_inth_sir_update(OMAPIntcState *s, int is_fiq)
{
int i, j, sir_intr, p_intr, p;
uint32_t level;
s->sir_intr[is_fiq] = sir_intr;
}
-static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
+static inline void omap_inth_update(OMAPIntcState *s, int is_fiq)
{
int i;
uint32_t has_intr = 0;
static void omap_set_intr(void *opaque, int irq, int req)
{
- struct omap_intr_handler_s *ih = opaque;
+ OMAPIntcState *ih = opaque;
uint32_t rise;
struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
/* Simplified version with no edge detection */
static void omap_set_intr_noedge(void *opaque, int irq, int req)
{
- struct omap_intr_handler_s *ih = opaque;
+ OMAPIntcState *ih = opaque;
uint32_t rise;
struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
static uint64_t omap_inth_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_intr_handler_s *s = opaque;
+ OMAPIntcState *s = opaque;
int i, offset = addr;
int bank_no = offset >> 8;
int line_no;
static void omap_inth_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_intr_handler_s *s = opaque;
+ OMAPIntcState *s = opaque;
int i, offset = addr;
int bank_no = offset >> 8;
struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
static void omap_inth_reset(DeviceState *dev)
{
- struct omap_intr_handler_s *s = OMAP_INTC(dev);
+ OMAPIntcState *s = OMAP_INTC(dev);
int i;
for (i = 0; i < s->nbanks; ++i){
static void omap_intc_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
- struct omap_intr_handler_s *s = OMAP_INTC(obj);
+ OMAPIntcState *s = OMAP_INTC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
s->nbanks = 1;
static void omap_intc_realize(DeviceState *dev, Error **errp)
{
- struct omap_intr_handler_s *s = OMAP_INTC(dev);
+ OMAPIntcState *s = OMAP_INTC(dev);
if (!s->iclk) {
error_setg(errp, "omap-intc: clk not connected");
}
}
-void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk)
+void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk)
{
intc->iclk = clk;
}
-void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk)
+void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk)
{
intc->fclk = clk;
}
static Property omap_intc_properties[] = {
- DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
+ DEFINE_PROP_UINT32("size", OMAPIntcState, size, 0x100),
DEFINE_PROP_END_OF_LIST(),
};
static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_intr_handler_s *s = opaque;
+ OMAPIntcState *s = opaque;
int offset = addr;
int bank_no, line_no;
struct omap_intr_handler_bank_s *bank = NULL;
static void omap2_inth_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_intr_handler_s *s = opaque;
+ OMAPIntcState *s = opaque;
int offset = addr;
int bank_no, line_no;
struct omap_intr_handler_bank_s *bank = NULL;
static void omap2_intc_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
- struct omap_intr_handler_s *s = OMAP_INTC(obj);
+ OMAPIntcState *s = OMAP_INTC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
s->level_only = 1;
static void omap2_intc_realize(DeviceState *dev, Error **errp)
{
- struct omap_intr_handler_s *s = OMAP_INTC(dev);
+ OMAPIntcState *s = OMAP_INTC(dev);
if (!s->iclk) {
error_setg(errp, "omap2-intc: iclk not connected");
}
static Property omap2_intc_properties[] = {
- DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
+ DEFINE_PROP_UINT8("revision", OMAPIntcState,
revision, 0x21),
DEFINE_PROP_END_OF_LIST(),
};
static const TypeInfo omap_intc_type_info = {
.name = TYPE_OMAP_INTC,
.parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(omap_intr_handler),
+ .instance_size = sizeof(OMAPIntcState),
.abstract = true,
};