return __gc0310_flush_reg_array(client, &ctrl);
}
+
static int gc0310_g_focal(struct v4l2_subdev *sd, s32 *val)
{
*val = (GC0310_FOCAL_LENGTH_NUM << 16) | GC0310_FOCAL_LENGTH_DEM;
/* we should not accept the invalid value below. */
if (gain == 0) {
struct i2c_client *client = v4l2_get_subdevdata(sd);
+
v4l2_err(client, "%s: invalid value\n", __func__);
return -EINVAL;
}
static long gc0310_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
-
switch (cmd) {
case ATOMISP_IOC_S_EXPOSURE:
return gc0310_s_exposure(sd, arg);
{
int ret = 0;
struct gc0310_device *dev = to_gc0310_sensor(sd);
+
if (!dev || !dev->platform_data)
return -ENODEV;
return ret;
}
-
static int power_down(struct v4l2_subdev *sd);
static int power_up(struct v4l2_subdev *sd)
static int gc0310_s_power(struct v4l2_subdev *sd, int on)
{
int ret;
+
if (on == 0)
return power_down(sd);
else {
h_ratio = (res->height << 13) / h;
if (h_ratio == 0)
return -1;
- match = abs(((w_ratio << 13) / h_ratio) - ((int)8192));
+ match = abs(((w_ratio << 13) / h_ratio) - 8192);
- if ((w_ratio < (int)8192) || (h_ratio < (int)8192) ||
+ if ((w_ratio < 8192) || (h_ratio < 8192) ||
(match > LARGEST_ALLOWED_RATIO_MISMATCH))
return -1;
return -1;
}
-
/* TODO: remove it. */
static int startup(struct v4l2_subdev *sd)
{
struct camera_mipi_info *gc0310_info = NULL;
int ret = 0;
int idx = 0;
+
pr_info("%s S\n", __func__);
if (format->pad)
return -EINVAL;
}
- printk("%s: before gc0310_write_reg_array %s\n", __FUNCTION__,
+ printk("%s: before gc0310_write_reg_array %s\n", __func__,
gc0310_res[dev->fmt_idx].desc);
ret = startup(sd);
if (ret) {
dev_err(&client->dev, "read sensor_id_low failed\n");
return -ENODEV;
}
- id = ((((u16) high) << 8) | (u16) low);
+ id = ((((u16)high) << 8) | (u16)low);
pr_info("sensor ID = 0x%x\n", id);
if (id != GC0310_ID) {
return ret;
}
-
static int gc0310_s_config(struct v4l2_subdev *sd,
int irq, void *platform_data)
{
fse->max_height = gc0310_res[index].height;
return 0;
-
}
-
static int gc0310_g_skip_frames(struct v4l2_subdev *sd, u32 *frames)
{
struct gc0310_device *dev = to_gc0310_sensor(sd);
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct gc0310_device *dev = to_gc0310_sensor(sd);
+
dev_dbg(&client->dev, "gc0310_remove...\n");
dev->platform_data->csi_cfg(sd, 0);
mutex_init(&dev->input_lock);
dev->fmt_idx = 0;
- v4l2_i2c_subdev_init(&(dev->sd), client, &gc0310_ops);
+ v4l2_i2c_subdev_init(&dev->sd, client, &gc0310_ops);
pdata = gmin_camera_platform_data(&dev->sd,
ATOMISP_INPUT_FORMAT_RAW_8,
return 0;
}
+
static int __gc2235_write_reg_is_consecutive(struct i2c_client *client,
struct gc2235_write_ctrl *ctrl,
const struct gc2235_reg *next)
return ctrl->buffer.addr + ctrl->index == next->reg;
}
+
static int gc2235_write_reg_array(struct i2c_client *client,
const struct gc2235_reg *reglist)
{
return 0;
}
-
static int gc2235_get_intg_factor(struct i2c_client *client,
struct camera_mipi_info *info,
const struct gc2235_resolution *res)
u16 coarse_integration = (u16)coarse_itg;
int ret = 0;
u16 expo_coarse_h, expo_coarse_l, gain_val = 0xF0, gain_val2 = 0xF0;
+
expo_coarse_h = coarse_integration >> 8;
expo_coarse_l = coarse_integration & 0xff;
return ret;
}
-
static int gc2235_set_exposure(struct v4l2_subdev *sd, int exposure,
int gain, int digitgain)
{
/* we should not accept the invalid value below. */
if (gain == 0) {
struct i2c_client *client = v4l2_get_subdevdata(sd);
+
v4l2_err(client, "%s: invalid value\n", __func__);
return -EINVAL;
}
return gc2235_set_exposure(sd, exp, gain, digitgain);
}
+
static long gc2235_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
switch (cmd) {
}
return 0;
}
+
/* This returns the exposure time being used. This should only be used
* for filling in EXIF data, not for actual image processing.
*/
struct gc2235_device *dev = to_gc2235_sensor(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret = 0;
+
if (is_init == 0) {
/* force gc2235 to do a reset in res change, otherwise it
* can not output normal after switching res. and it is not
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
{
-
struct v4l2_mbus_framefmt *fmt = &format->format;
struct gc2235_device *dev = to_gc2235_sensor(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct gc2235_device *dev = to_gc2235_sensor(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret;
+
mutex_lock(&dev->input_lock);
if (enable)
return ret;
}
-
static int gc2235_s_config(struct v4l2_subdev *sd,
int irq, void *platform_data)
{
fse->max_height = gc2235_res[index].height;
return 0;
-
}
static int gc2235_g_skip_frames(struct v4l2_subdev *sd, u32 *frames)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct gc2235_device *dev = to_gc2235_sensor(sd);
+
dev_dbg(&client->dev, "gc2235_remove...\n");
dev->platform_data->csi_cfg(sd, 0);
mutex_init(&dev->input_lock);
dev->fmt_idx = 0;
- v4l2_i2c_subdev_init(&(dev->sd), client, &gc2235_ops);
+ v4l2_i2c_subdev_init(&dev->sd, client, &gc2235_ops);
gcpdev = gmin_camera_platform_data(&dev->sd,
ATOMISP_INPUT_FORMAT_RAW_10,
/* Tagged binary data container structure definitions. */
struct tbd_header {
- uint32_t tag; /*!< Tag identifier, also checks endianness */
- uint32_t size; /*!< Container size including this header */
- uint32_t version; /*!< Version, format 0xYYMMDDVV */
- uint32_t revision; /*!< Revision, format 0xYYMMDDVV */
- uint32_t config_bits; /*!< Configuration flag bits set */
- uint32_t checksum; /*!< Global checksum, header included */
+ u32 tag; /*!< Tag identifier, also checks endianness */
+ u32 size; /*!< Container size including this header */
+ u32 version; /*!< Version, format 0xYYMMDDVV */
+ u32 revision; /*!< Revision, format 0xYYMMDDVV */
+ u32 config_bits; /*!< Configuration flag bits set */
+ u32 checksum; /*!< Global checksum, header included */
} __packed;
struct tbd_record_header {
- uint32_t size; /*!< Size of record including header */
- uint8_t format_id; /*!< tbd_format_t enumeration values used */
- uint8_t packing_key; /*!< Packing method; 0 = no packing */
- uint16_t class_id; /*!< tbd_class_t enumeration values used */
+ u32 size; /*!< Size of record including header */
+ u8 format_id; /*!< tbd_format_t enumeration values used */
+ u8 packing_key; /*!< Packing method; 0 = no packing */
+ u16 class_id; /*!< tbd_class_t enumeration values used */
} __packed;
struct tbd_data_record_header {
- uint16_t next_offset;
- uint16_t flags;
- uint16_t data_offset;
- uint16_t data_size;
+ u16 next_offset;
+ u16 flags;
+ u16 data_offset;
+ u16 data_size;
} __packed;
#define TBD_CLASS_DRV_ID 2
* followed by lobyte) where the remaining data in the sequence
* will be written. */
- uint8_t *ptr = bufptr;
+ u8 *ptr = bufptr;
+
while (ptr < bufptr + size) {
struct i2c_msg msg = {
.addr = client->addr,
static int parse_and_apply(struct i2c_client *client, uint8_t *buffer,
unsigned int size)
{
- uint8_t *endptr8 = buffer + size;
+ u8 *endptr8 = buffer + size;
struct tbd_data_record_header *header =
(struct tbd_data_record_header *)buffer;
const struct firmware **fw)
{
int ret = request_firmware(fw, name, &client->dev);
+
if (ret) {
dev_err(&client->dev,
"Error %d while requesting firmware %s\n",
#define LM3554_CURRENT_LIMIT_SHIFT 5
#define LM3554_FLAGS_REG 0xD0
-#define LM3554_FLAG_TIMEOUT (1 << 0)
-#define LM3554_FLAG_THERMAL_SHUTDOWN (1 << 1)
-#define LM3554_FLAG_LED_FAULT (1 << 2)
-#define LM3554_FLAG_TX1_INTERRUPT (1 << 3)
-#define LM3554_FLAG_TX2_INTERRUPT (1 << 4)
-#define LM3554_FLAG_LED_THERMAL_FAULT (1 << 5)
-#define LM3554_FLAG_UNUSED (1 << 6)
-#define LM3554_FLAG_INPUT_VOLTAGE_LOW (1 << 7)
+#define LM3554_FLAG_TIMEOUT BIT(0)
+#define LM3554_FLAG_THERMAL_SHUTDOWN BIT(1)
+#define LM3554_FLAG_LED_FAULT BIT(2)
+#define LM3554_FLAG_TX1_INTERRUPT BIT(3)
+#define LM3554_FLAG_TX2_INTERRUPT BIT(4)
+#define LM3554_FLAG_LED_THERMAL_FAULT BIT(5)
+#define LM3554_FLAG_UNUSED BIT(6)
+#define LM3554_FLAG_INPUT_VOLTAGE_LOW BIT(7)
#define LM3554_CONFIG_REG_1 0xE0
#define LM3554_ENVM_TX2_SHIFT 5
NULL);
if (flash->ctrl_handler.error) {
-
dev_err(&client->dev, "ctrl_handler error.\n");
goto fail2;
}
msg[0].buf = data;
/* high byte goes out first */
- data[0] = (u16) (reg >> 8);
- data[1] = (u16) (reg & 0xff);
+ data[0] = (u16)(reg >> 8);
+ data[1] = (u16)(reg & 0xff);
msg[1].addr = client->addr;
msg[1].len = data_length;
return 0;
}
-
static int __mt9m114_flush_reg_array(struct i2c_client *client,
struct mt9m114_write_ctrl *ctrl)
{
}
return -EINVAL;
-
}
static int mt9m114_set_suspend(struct v4l2_subdev *sd)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
+
return mt9m114_write_reg_array(client,
mt9m114_standby_reg, POST_POLLING);
}
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret;
- if (NULL == dev->platform_data) {
+ if (!dev->platform_data) {
dev_err(&client->dev, "no camera_sensor_platform_data");
return -ENODEV;
}
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret;
- if (NULL == dev->platform_data) {
+ if (!dev->platform_data) {
dev_err(&client->dev, "no camera_sensor_platform_data");
return -ENODEV;
}
return -EINVAL;
}
- if (h_size != NULL)
+ if (h_size)
*h_size = hsize;
- if (v_size != NULL)
+ if (v_size)
*v_size = vsize;
return 0;
u32 reg_val;
int ret;
- if (info == NULL)
+ if (!info)
return -EINVAL;
ret = mt9m114_read_reg(client, MISENSOR_32BIT,
struct v4l2_mbus_framefmt *fmt = &format->format;
int width, height;
int ret;
+
if (format->pad)
return -EINVAL;
fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
struct camera_mipi_info *mt9m114_info = NULL;
int ret;
+
if (format->pad)
return -EINVAL;
dev->streamon = 0;
dev->first_exp = MT9M114_DEFAULT_FIRST_EXP;
mt9m114_info = v4l2_get_subdev_hostdata(sd);
- if (mt9m114_info == NULL)
+ if (!mt9m114_info)
return -EINVAL;
mt9m114_try_res(&width, &height);
struct i2c_client *c = v4l2_get_subdevdata(sd);
int ret;
u32 data;
+
ret = mt9m114_read_reg(c, MISENSOR_16BIT,
(u32)MISENSOR_READ_MODE, &data);
if (ret)
static long mt9m114_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
-
switch (cmd) {
case ATOMISP_IOC_S_EXPOSURE:
return mt9m114_s_exposure(sd, arg);
*value = coarse;
return 0;
}
+
#ifndef CSS15
/*
* This function will return the sensor supported max exposure zone number.
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret;
- if (NULL == platform_data)
+ if (!platform_data)
return -ENODEV;
dev->platform_data =
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_frame_size_enum *fse)
{
-
unsigned int index = fse->index;
if (index >= N_RES)
int index;
struct mt9m114_device *snr = to_mt9m114_sensor(sd);
- if (frames == NULL)
+ if (!frames)
return -EINVAL;
for (index = 0; index < N_RES; index++) {
#include "ov2680.h"
-static int h_flag = 0;
-static int v_flag = 0;
+static int h_flag;
+static int v_flag;
static enum atomisp_bayer_order ov2680_bayer_order_mapping[] = {
atomisp_bayer_order_bggr,
atomisp_bayer_order_grbg,
return -EINVAL;
}
- memset(msg, 0 , sizeof(msg));
+ memset(msg, 0, sizeof(msg));
msg[0].addr = client->addr;
msg[0].flags = 0;
const struct ov2680_reg *next = reglist;
struct ov2680_write_ctrl ctrl;
int err;
+
dev_dbg(&client->dev, "++++write reg array\n");
ctrl.index = 0;
for (; next->type != OV2680_TOK_TERM; next++) {
* If next address is not consecutive, data needs to be
* flushed before proceed.
*/
- dev_dbg(&client->dev, "+++ov2680_write_reg_array reg=%x->%x\n", next->reg,next->val);
+ dev_dbg(&client->dev, "+++ov2680_write_reg_array reg=%x->%x\n", next->reg, next->val);
if (!__ov2680_write_reg_is_consecutive(client, &ctrl,
next)) {
err = __ov2680_flush_reg_array(client, &ctrl);
return __ov2680_flush_reg_array(client, &ctrl);
}
+
static int ov2680_g_focal(struct v4l2_subdev *sd, s32 *val)
{
-
*val = (OV2680_FOCAL_LENGTH_NUM << 16) | OV2680_FOCAL_LENGTH_DEM;
return 0;
}
{
struct ov2680_device *dev = to_ov2680_sensor(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
+
dev_dbg(&client->dev, "++++ov2680_g_bin_factor_x\n");
*val = ov2680_res[dev->fmt_idx].bin_factor_x;
return 0;
}
-
static int ov2680_get_intg_factor(struct i2c_client *client,
struct camera_mipi_info *info,
const struct ov2680_resolution *res)
unsigned int pix_clk_freq_hz;
u16 reg_val;
int ret;
+
dev_dbg(&client->dev, "++++ov2680_get_intg_factor\n");
if (!info)
return -EINVAL;
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct ov2680_device *dev = to_ov2680_sensor(sd);
u16 vts;
- int ret,exp_val;
+ int ret, exp_val;
dev_dbg(&client->dev,
"+++++++__ov2680_set_exposure coarse_itg %d, gain %d, digitgain %d++\n",
/* group hold */
ret = ov2680_write_reg(client, OV2680_8BIT,
- OV2680_GROUP_ACCESS, 0x00);
+ OV2680_GROUP_ACCESS, 0x00);
if (ret) {
dev_err(&client->dev, "%s: write %x error, aborted\n",
__func__, OV2680_GROUP_ACCESS);
/* Increase the VTS to match exposure + MARGIN */
if (coarse_itg > vts - OV2680_INTEGRATION_TIME_MARGIN)
- vts = (u16) coarse_itg + OV2680_INTEGRATION_TIME_MARGIN;
+ vts = (u16)coarse_itg + OV2680_INTEGRATION_TIME_MARGIN;
ret = ov2680_write_reg(client, OV2680_16BIT, OV2680_TIMING_VTS_H, vts);
if (ret) {
/* we should not accept the invalid value below */
if (analog_gain == 0) {
struct i2c_client *client = v4l2_get_subdevdata(sd);
+
v4l2_err(client, "%s: invalid value\n", __func__);
return -EINVAL;
}
return ov2680_set_exposure(sd, coarse_itg, analog_gain, digital_gain);
}
-
-
-
-
static long ov2680_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
-
switch (cmd) {
case ATOMISP_IOC_S_EXPOSURE:
return ov2680_s_exposure(sd, arg);
int ret;
u16 val;
u8 index;
+
dev_dbg(&client->dev, "@%s: value:%d\n", __func__, value);
ret = ov2680_read_reg(client, OV2680_8BIT, OV2680_FLIP_REG, &val);
if (ret)
OV2680_FLIP_REG, val);
if (ret)
return ret;
- index = (v_flag>0?OV2680_FLIP_BIT:0) | (h_flag>0?OV2680_MIRROR_BIT:0);
+ index = (v_flag > 0 ? OV2680_FLIP_BIT : 0) | (h_flag > 0 ? OV2680_MIRROR_BIT : 0);
ov2680_info = v4l2_get_subdev_hostdata(sd);
if (ov2680_info) {
ov2680_info->raw_bayer_order = ov2680_bayer_order_mapping[index];
int ret;
u16 val;
u8 index;
+
dev_dbg(&client->dev, "@%s: value:%d\n", __func__, value);
ret = ov2680_read_reg(client, OV2680_8BIT, OV2680_MIRROR_REG, &val);
OV2680_MIRROR_REG, val);
if (ret)
return ret;
- index = (v_flag>0?OV2680_FLIP_BIT:0) | (h_flag>0?OV2680_MIRROR_BIT:0);
+ index = (v_flag > 0 ? OV2680_FLIP_BIT : 0) | (h_flag > 0 ? OV2680_MIRROR_BIT : 0);
ov2680_info = v4l2_get_subdev_hostdata(sd);
if (ov2680_info) {
ov2680_info->raw_bayer_order = ov2680_bayer_order_mapping[index];
{
int ret = 0;
struct ov2680_device *dev = to_ov2680_sensor(sd);
+
if (!dev || !dev->platform_data)
return -ENODEV;
{
int ret;
- if (on == 0){
+ if (on == 0) {
ret = power_down(sd);
} else {
ret = power_up(sd);
h_ratio = (res->height << 13) / h;
if (h_ratio == 0)
return -1;
- match = abs(((w_ratio << 13) / h_ratio) - ((int)8192));
-
+ match = abs(((w_ratio << 13) / h_ratio) - 8192);
- if ((w_ratio < (int)8192) || (h_ratio < (int)8192) ||
+ if ((w_ratio < 8192) || (h_ratio < 8192) ||
(match > LARGEST_ALLOWED_RATIO_MISMATCH))
return -1;
struct camera_mipi_info *ov2680_info = NULL;
int ret = 0;
int idx = 0;
+
dev_dbg(&client->dev, "+++++ov2680_s_mbus_fmt+++++l\n");
if (format->pad)
return -EINVAL;
if (v_flag)
ov2680_v_flip(sd, v_flag);
- v4l2_info(client, "\n%s idx %d \n", __func__, dev->fmt_idx);
+ v4l2_info(client, "\n%s idx %d\n", __func__, dev->fmt_idx);
/*ret = startup(sd);
* if (ret)
}
ret = ov2680_read_reg(client, OV2680_8BIT,
OV2680_SC_CMMN_CHIP_ID_L, &low);
- id = ((((u16) high) << 8) | (u16) low);
+ id = ((((u16)high) << 8) | (u16)low);
if (id != OV2680_ID) {
dev_err(&client->dev, "sensor ID error 0x%x\n", id);
ret = ov2680_read_reg(client, OV2680_8BIT,
OV2680_SC_CMMN_SUB_ID, &high);
- revision = (u8) high & 0x0f;
+ revision = (u8)high & 0x0f;
dev_info(&client->dev, "sensor_revision id = 0x%x, rev= %d\n",
id, revision);
int ret;
mutex_lock(&dev->input_lock);
- if(enable )
- dev_dbg(&client->dev, "ov2680_s_stream one \n");
+ if (enable)
+ dev_dbg(&client->dev, "ov2680_s_stream one\n");
else
- dev_dbg(&client->dev, "ov2680_s_stream off \n");
+ dev_dbg(&client->dev, "ov2680_s_stream off\n");
ret = ov2680_write_reg(client, OV2680_8BIT, OV2680_SW_STREAM,
enable ? OV2680_START_STREAMING :
return ret;
}
-
static int ov2680_s_config(struct v4l2_subdev *sd,
int irq, void *platform_data)
{
fse->max_height = ov2680_res[index].height;
return 0;
-
}
static int ov2680_g_skip_frames(struct v4l2_subdev *sd, u32 *frames)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct ov2680_device *dev = to_ov2680_sensor(sd);
+
dev_dbg(&client->dev, "ov2680_remove...\n");
dev->platform_data->csi_cfg(sd, 0);
mutex_init(&dev->input_lock);
dev->fmt_idx = 0;
- v4l2_i2c_subdev_init(&(dev->sd), client, &ov2680_ops);
+ v4l2_i2c_subdev_init(&dev->sd, client, &ov2680_ops);
pdata = gmin_camera_platform_data(&dev->sd,
ATOMISP_INPUT_FORMAT_RAW_10,
if (!pdata) {
ret = -EINVAL;
goto out_free;
- }
+ }
ret = ov2680_s_config(&dev->sd, client->irq, pdata);
if (ret)
if (ret)
{
ov2680_remove(client);
- dev_dbg(&client->dev, "+++ remove ov2680 \n");
+ dev_dbg(&client->dev, "+++ remove ov2680\n");
}
return ret;
out_free:
- dev_dbg(&client->dev, "+++ out free \n");
+ dev_dbg(&client->dev, "+++ out free\n");
v4l2_device_unregister_subdev(&dev->sd);
kfree(dev);
return ret;
return -EINVAL;
}
- memset(msg, 0 , sizeof(msg));
+ memset(msg, 0, sizeof(msg));
msg[0].addr = client->addr;
msg[0].flags = 0;
return __ov2722_flush_reg_array(client, &ctrl);
}
+
static int ov2722_g_focal(struct v4l2_subdev *sd, s32 *val)
{
*val = (OV2722_FOCAL_LENGTH_NUM << 16) | OV2722_FOCAL_LENGTH_DEM;
return ret;
pre_pll_clk_div = (pre_pll_clk_div & 0x70) >> 4;
- if (0 == pre_pll_clk_div)
+ if (!pre_pll_clk_div)
return -EINVAL;
pll_multiplier = pll_multiplier & 0x7f;
/* we should not accept the invalid value below. */
if (gain == 0) {
struct i2c_client *client = v4l2_get_subdevdata(sd);
+
v4l2_err(client, "%s: invalid value\n", __func__);
return -EINVAL;
}
static long ov2722_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
-
switch (cmd) {
case ATOMISP_IOC_S_EXPOSURE:
return ov2722_s_exposure(sd, arg);
container_of(ctrl->handler, struct ov2722_device, ctrl_handler);
int ret = 0;
unsigned int val;
+
switch (ctrl->id) {
case V4L2_CID_EXPOSURE_ABSOLUTE:
ret = ov2722_q_exposure(&dev->sd, &ctrl->val);
static int ov2722_s_power(struct v4l2_subdev *sd, int on)
{
int ret;
+
if (on == 0)
return power_down(sd);
else {
struct camera_mipi_info *ov2722_info = NULL;
int ret = 0;
int idx;
+
if (format->pad)
return -EINVAL;
if (!fmt)
ret = startup(sd);
if (ret) {
int i = 0;
+
dev_err(&client->dev, "ov2722 startup err, retry to power up\n");
for (i = 0; i < OV2722_POWER_UP_RETRY_NUM; i++) {
dev_err(&client->dev,
mutex_unlock(&dev->input_lock);
return ret;
}
+
static int ov2722_get_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
ret = ov2722_read_reg(client, OV2722_8BIT,
OV2722_SC_CMMN_SUB_ID, &high);
- revision = (u8) high & 0x0f;
+ revision = (u8)high & 0x0f;
dev_dbg(&client->dev, "sensor_revision = 0x%x\n", revision);
dev_dbg(&client->dev, "detect ov2722 success\n");
fse->max_height = ov2722_res[index].height;
return 0;
-
}
-
static int ov2722_g_skip_frames(struct v4l2_subdev *sd, u32 *frames)
{
struct ov2722_device *dev = to_ov2722_sensor(sd);
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct ov2722_device *dev = to_ov2722_sensor(sd);
+
dev_dbg(&client->dev, "ov2722_remove...\n");
dev->platform_data->csi_cfg(sd, 0);
{
struct v4l2_ctrl_handler *hdl;
unsigned int i;
+
hdl = &dev->ctrl_handler;
v4l2_ctrl_handler_init(&dev->ctrl_handler, ARRAY_SIZE(ov2722_controls));
for (i = 0; i < ARRAY_SIZE(ov2722_controls); i++)
mutex_init(&dev->input_lock);
dev->fmt_idx = 0;
- v4l2_i2c_subdev_init(&(dev->sd), client, &ov2722_ops);
+ v4l2_i2c_subdev_init(&dev->sd, client, &ov2722_ops);
ovpdev = gmin_camera_platform_data(&dev->sd,
ATOMISP_INPUT_FORMAT_RAW_10,
.regs = gc0310_VGA_30fps,
},
};
+
#define N_RES_PREVIEW (ARRAY_SIZE(gc0310_res_preview))
static struct gc0310_resolution *gc0310_res = gc0310_res_preview;
static unsigned long N_RES = N_RES_PREVIEW;
#endif
-
{ GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
+
/*
* Register settings for various resolution
*/
};
static struct gc2235_resolution gc2235_res_preview[] = {
-
{
.desc = "gc2235_1600_900_30fps",
.width = 1600,
},
};
+
#define N_RES_PREVIEW (ARRAY_SIZE(gc2235_res_preview))
/*
},
};
+
#define N_RES_STILL (ARRAY_SIZE(gc2235_res_still))
static struct gc2235_resolution gc2235_res_video[] = {
},
};
+
#define N_RES_VIDEO (ARRAY_SIZE(gc2235_res_video))
#endif
#define MISENSOR_TOK_POLL 0xfc00 /* token indicating poll instruction */
#define MISENSOR_TOK_RMW 0x0010 /* RMW operation */
#define MISENSOR_TOK_MASK 0xfff0
-#define MISENSOR_AWB_STEADY (1<<0) /* awb steady */
-#define MISENSOR_AE_READY (1<<3) /* ae status ready */
+#define MISENSOR_AWB_STEADY BIT(0) /* awb steady */
+#define MISENSOR_AE_READY BIT(3) /* ae status ready */
/* mask to set sensor read_mode via misensor_rmw_reg */
#define MISENSOR_R_MODE_MASK 0x0330
#define MT9M114_COARSE_INTG_TIME_MIN 1
#define MT9M114_COARSE_INTG_TIME_MAX_MARGIN 6
-
/* ulBPat; */
-#define MT9M114_BPAT_RGRGGBGB (1 << 0)
-#define MT9M114_BPAT_GRGRBGBG (1 << 1)
-#define MT9M114_BPAT_GBGBRGRG (1 << 2)
-#define MT9M114_BPAT_BGBGGRGR (1 << 3)
+#define MT9M114_BPAT_RGRGGBGB BIT(0)
+#define MT9M114_BPAT_GRGRBGBG BIT(1)
+#define MT9M114_BPAT_GBGBRGRG BIT(2)
+#define MT9M114_BPAT_BGBGGRGR BIT(3)
#define MT9M114_FOCAL_LENGTH_NUM 208 /*2.08mm*/
#define MT9M114_FOCAL_LENGTH_DEM 100
MT9M114_RES_864P,
MT9M114_RES_960P,
};
+
#define MT9M114_RES_960P_SIZE_H 1296
#define MT9M114_RES_960P_SIZE_V 976
#define MT9M114_RES_720P_SIZE_H 1280
PRE_POLLING,
POST_POLLING,
};
+
/*
* struct misensor_reg - MI sensor register format
* @length: length of the register
.bin_mode = 0,
},
};
+
#define N_RES (ARRAY_SIZE(mt9m114_res))
#if 0 /* Currently unused */
{MISENSOR_TOK_TERM, 0, 0},
};
+
#if 0 /* Currently unused */
static struct misensor_reg const mt9m114_antiflicker_50hz[] = {
{MISENSOR_16BIT, 0x098E, 0xC88B},
#define OV2680_START_STREAMING 0x01
#define OV2680_STOP_STREAMING 0x00
-
#define OV2680_INVALID_CONFIG 0xffffffff
-
struct regval_list {
u16 reg_num;
u8 value;
{OV2680_TOK_TERM, 0, 0}
};
-
#if 0 /* None of the definitions below are used currently */
/*
* 176x144 30fps VBlanking 1lane 10Bit (binning)
{OV2680_TOK_TERM, 0, 0}
};
-
/*
* 656x496 30fps VBlanking 1lane 10Bit (binning)
*/
{OV2680_8BIT, 0x3821, 0x00}, //miror/flip
// {OV2680_8BIT, 0x5090, 0x0c},
{OV2680_TOK_TERM, 0, 0}
- };
+ };
/*
* 1456*1096 30fps VBlanking 1lane 10bit(no-scaling)
*/
- static struct ov2680_reg const ov2680_1456x1096_30fps[]= {
+ static struct ov2680_reg const ov2680_1456x1096_30fps[] = {
{OV2680_8BIT, 0x3086, 0x00},
{OV2680_8BIT, 0x3501, 0x48},
{OV2680_8BIT, 0x3502, 0xe0},
{OV2680_8BIT, 0x4009, 0x09},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_TOK_TERM, 0, 0}
- };
+ };
#endif
/*
* 1616x1216 30fps VBlanking 1lane 10Bit
static struct ov2680_resolution ov2680_res_preview[] = {
{
.desc = "ov2680_1616x1216_30fps",
- .width = 1616,
+ .width = 1616,
.height = 1216,
.pix_clk_freq = 66,
.fps = 30,
.skip_frames = 3,
.regs = ov2680_1616x1216_30fps,
},
- {
+ {
.desc = "ov2680_1616x916_30fps",
.width = 1616,
.height = 916,
.regs = ov2680_1616x916_30fps,
},
};
+
#define N_RES_PREVIEW (ARRAY_SIZE(ov2680_res_preview))
static struct ov2680_resolution *ov2680_res = ov2680_res_preview;
{OV2722_8BIT, 0x3509, 0x00},
{OV2722_TOK_TERM, 0, 0}
};
+
#if 0
static struct ov2722_reg const ov2722_1M3_30fps[] = {
{OV2722_8BIT, 0x3718, 0x10},
.mipi_freq = 345600,
},
};
+
#define N_RES_PREVIEW (ARRAY_SIZE(ov2722_res_preview))
/*
.mipi_freq = 345600,
},
};
+
#define N_RES_STILL (ARRAY_SIZE(ov2722_res_still))
struct ov2722_resolution ov2722_res_video[] = {
.mipi_freq = 345600,
},
};
+
#define N_RES_VIDEO (ARRAY_SIZE(ov2722_res_video))
#endif
#include <linux/types.h>
-
#define AD5823_VCM_ADDR 0x0c
#define AD5823_REG_RESET 0x01
return 0;
}
-
-static const uint32_t ov5693_embedded_effective_size = 28;
+static const u32 ov5693_embedded_effective_size = 28;
/* i2c read/write stuff */
static int ov5693_read_reg(struct i2c_client *client,
return __ov5693_flush_reg_array(client, &ctrl);
}
+
static int ov5693_g_focal(struct v4l2_subdev *sd, s32 *val)
{
*val = (OV5693_FOCAL_LENGTH_NUM << 16) | OV5693_FOCAL_LENGTH_DEM;
u16 reg_val;
int ret;
- if (info == NULL)
+ if (!info)
return -EINVAL;
/* pixel clock */
}
/* Increase the VTS to match exposure + MARGIN */
if (coarse_itg > vts - OV5693_INTEGRATION_TIME_MARGIN)
- vts = (u16) coarse_itg + OV5693_INTEGRATION_TIME_MARGIN;
+ vts = (u16)coarse_itg + OV5693_INTEGRATION_TIME_MARGIN;
ret = ov5693_write_reg(client, OV5693_8BIT,
OV5693_TIMING_VTS_H, (vts >> 8) & 0xFF);
u16 *pVal = NULL;
for (index = 0; index <= size; index++) {
- pVal = (u16 *) (buf + index);
+ pVal = (u16 *)(buf + index);
ret =
ov5693_read_reg(client, OV5693_8BIT, addr + index,
pVal);
priv->size = dev->otp_size;
return 0;
-
}
static long ov5693_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
-
switch (cmd) {
case ATOMISP_IOC_S_EXPOSURE:
return ov5693_s_exposure(sd, arg);
if (!fmt)
return -EINVAL;
ov5693_info = v4l2_get_subdev_hostdata(sd);
- if (ov5693_info == NULL)
+ if (!ov5693_info)
return -EINVAL;
mutex_lock(&dev->input_lock);
for (i = 0; i < OV5693_POWER_UP_RETRY_NUM; i++) {
dev_err(&client->dev,
"ov5693 retry to power up %d/%d times, result: ",
- i+1, OV5693_POWER_UP_RETRY_NUM);
+ i + 1, OV5693_POWER_UP_RETRY_NUM);
power_down(sd);
ret = power_up(sd);
if (!ret) {
mutex_unlock(&dev->input_lock);
return ret;
}
+
static int ov5693_get_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
}
ret = ov5693_read_reg(client, OV5693_8BIT,
OV5693_SC_CMMN_CHIP_ID_L, &low);
- id = ((((u16) high) << 8) | (u16) low);
+ id = ((((u16)high) << 8) | (u16)low);
if (id != OV5693_ID) {
dev_err(&client->dev, "sensor ID error 0x%x\n", id);
ret = ov5693_read_reg(client, OV5693_8BIT,
OV5693_SC_CMMN_SUB_ID, &high);
- revision = (u8) high & 0x0f;
+ revision = (u8)high & 0x0f;
dev_dbg(&client->dev, "sensor_revision = 0x%x\n", revision);
dev_dbg(&client->dev, "detect ov5693 success\n");
return ret;
}
-
static int ov5693_s_config(struct v4l2_subdev *sd,
int irq, void *platform_data)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret = 0;
- if (platform_data == NULL)
+ if (!platform_data)
return -ENODEV;
dev->platform_data =
fse->max_height = ov5693_res[index].height;
return 0;
-
}
static const struct v4l2_subdev_video_ops ov5693_video_ops = {
mutex_init(&dev->input_lock);
dev->fmt_idx = 0;
- v4l2_i2c_subdev_init(&(dev->sd), client, &ov5693_ops);
+ v4l2_i2c_subdev_init(&dev->sd, client, &ov5693_ops);
pdata = gmin_camera_platform_data(&dev->sd,
ATOMISP_INPUT_FORMAT_RAW_10,
*/
#define ENABLE_NON_PREVIEW 0
-
#define OV5693_POWER_UP_RETRY_NUM 5
/* Defines for register writes and register array processing */
#define OV5693_OTP_START_ADDR 0x3D00
#define OV5693_OTP_END_ADDR 0x3D0F
#define OV5693_OTP_DATA_SIZE 320
-#define OV5693_OTP_PROGRAM_REG 0x3D80
+#define OV5693_OTP_PROGRAM_REG 0x3D80
#define OV5693_OTP_READ_REG 0x3D81 // 1:Enable 0:disable
#define OV5693_OTP_BANK_REG 0x3D84 //otp bank and mode
#define OV5693_OTP_READY_REG_DONE 1
};
-
/*
* 336x256 30fps 17ms VBlanking 2lane 10Bit (Scaling)
DS from 2564x1956
{OV5693_TOK_TERM, 0, 0}
};
-
static struct ov5693_reg const ov5693_736x496[] = {
{OV5693_8BIT, 0x3501, 0x3d},
{OV5693_8BIT, 0x3502, 0x00},
{OV5693_TOK_TERM, 0, 0}
};
-
/*
* 1940x1096 30fps 8.8ms VBlanking 2lane 10bit (Scaling)
*/
.regs = ov5693_2576x1936_30fps,
},
};
+
#define N_RES_PREVIEW (ARRAY_SIZE(ov5693_res_preview))
/*
.regs = ov5693_2592x1944_30fps,
},
};
+
#define N_RES_STILL (ARRAY_SIZE(ov5693_res_still))
struct ov5693_resolution ov5693_res_video[] = {
.regs = ov5693_2592x1944_30fps,
},
};
+
#define N_RES_VIDEO (ARRAY_SIZE(ov5693_res_video))
#endif
};
struct atomisp_dvs_grid_info {
- uint32_t enable;
- uint32_t width;
- uint32_t aligned_width;
- uint32_t height;
- uint32_t aligned_height;
- uint32_t bqs_per_grid_cell;
- uint32_t num_hor_coefs;
- uint32_t num_ver_coefs;
+ u32 enable;
+ u32 width;
+ u32 aligned_width;
+ u32 height;
+ u32 aligned_height;
+ u32 bqs_per_grid_cell;
+ u32 num_hor_coefs;
+ u32 num_ver_coefs;
};
struct atomisp_dvs_envelop {
};
struct atomisp_grid_info {
- uint32_t enable;
- uint32_t use_dmem;
- uint32_t has_histogram;
- uint32_t s3a_width;
- uint32_t s3a_height;
- uint32_t aligned_width;
- uint32_t aligned_height;
- uint32_t s3a_bqs_per_grid_cell;
- uint32_t deci_factor_log2;
- uint32_t elem_bit_depth;
+ u32 enable;
+ u32 use_dmem;
+ u32 has_histogram;
+ u32 s3a_width;
+ u32 s3a_height;
+ u32 aligned_width;
+ u32 aligned_height;
+ u32 s3a_bqs_per_grid_cell;
+ u32 deci_factor_log2;
+ u32 elem_bit_depth;
};
struct atomisp_dis_vector {
int y;
};
-
/* DVS 2.0 Coefficient types. This structure contains 4 pointers to
* arrays that contain the coeffients for each type.
*/
struct atomisp_dis_statistics {
struct atomisp_dvs2_statistics dvs2_stat;
- uint32_t exp_id;
+ u32 exp_id;
};
struct atomisp_3a_rgby_output {
- uint32_t r;
- uint32_t g;
- uint32_t b;
- uint32_t y;
+ u32 r;
+ u32 g;
+ u32 b;
+ u32 y;
};
/*
/* to specify which type of metadata to get */
enum atomisp_metadata_type type;
void __user *data;
- uint32_t width;
- uint32_t height;
- uint32_t stride; /* in bytes */
- uint32_t exp_id; /* exposure ID */
- uint32_t *effective_width; /* mipi packets valid data size */
+ u32 width;
+ u32 height;
+ u32 stride; /* in bytes */
+ u32 exp_id; /* exposure ID */
+ u32 *effective_width; /* mipi packets valid data size */
};
struct atomisp_metadata {
void __user *data;
- uint32_t width;
- uint32_t height;
- uint32_t stride; /* in bytes */
- uint32_t exp_id; /* exposure ID */
- uint32_t *effective_width; /* mipi packets valid data size */
+ u32 width;
+ u32 height;
+ u32 stride; /* in bytes */
+ u32 exp_id; /* exposure ID */
+ u32 *effective_width; /* mipi packets valid data size */
};
struct atomisp_ext_isp_ctrl {
- uint32_t id;
- uint32_t data;
+ u32 id;
+ u32 data;
};
struct atomisp_3a_statistics {
struct atomisp_grid_info grid_info;
struct atomisp_3a_output __user *data;
struct atomisp_3a_rgby_output __user *rgby_data;
- uint32_t exp_id; /* exposure ID */
- uint32_t isp_config_id; /* isp config ID */
+ u32 exp_id; /* exposure ID */
+ u32 isp_config_id; /* isp config ID */
};
/**
/* metadata config */
struct atomisp_metadata_config {
- uint32_t metadata_height;
- uint32_t metadata_stride;
+ u32 metadata_height;
+ u32 metadata_stride;
};
/*
* Generic resolution structure.
*/
struct atomisp_resolution {
- uint32_t width; /** Width */
- uint32_t height; /** Height */
+ u32 width; /** Width */
+ u32 height; /** Height */
};
/*
* This specifies the coordinates (x,y)
*/
struct atomisp_zoom_point {
- int32_t x; /** x coordinate */
- int32_t y; /** y coordinate */
+ s32 x; /** x coordinate */
+ s32 y; /** y coordinate */
};
/*
};
struct atomisp_dz_config {
- uint32_t dx; /** Horizontal zoom factor */
- uint32_t dy; /** Vertical zoom factor */
+ u32 dx; /** Horizontal zoom factor */
+ u32 dy; /** Vertical zoom factor */
struct atomisp_zoom_region zoom_region; /** region for zoom */
};
};
struct atomisp_dvs_6axis_config {
- uint32_t exp_id;
- uint32_t width_y;
- uint32_t height_y;
- uint32_t width_uv;
- uint32_t height_uv;
- uint32_t *xcoords_y;
- uint32_t *ycoords_y;
- uint32_t *xcoords_uv;
- uint32_t *ycoords_uv;
+ u32 exp_id;
+ u32 width_y;
+ u32 height_y;
+ u32 width_uv;
+ u32 height_uv;
+ u32 *xcoords_y;
+ u32 *ycoords_y;
+ u32 *xcoords_uv;
+ u32 *ycoords_uv;
};
struct atomisp_formats_config {
- uint32_t video_full_range_flag;
+ u32 video_full_range_flag;
};
struct atomisp_parameters {
* Unique ID to track which config was actually applied to a particular
* frame, driver will send this id back with output frame together.
*/
- uint32_t isp_config_id;
+ u32 isp_config_id;
/*
* Switch to control per_frame setting:
* 1: this is a per_frame setting
* PLEASE KEEP THIS AT THE END OF THE STRUCTURE!!
*/
- uint32_t per_frame_setting;
+ u32 per_frame_setting;
};
#define ATOMISP_GAMMA_TABLE_SIZE 1024
};
#define ATOMISP_NUM_SC_COLORS 4
-#define ATOMISP_SC_FLAG_QUERY (1 << 0)
+#define ATOMISP_SC_FLAG_QUERY BIT(0)
struct atomisp_shading_table {
__u32 enable;
unsigned int crop_vertical_end;
unsigned int output_width; /* input size to ISP after binning/scaling */
unsigned int output_height;
- uint8_t binning_factor_x; /* horizontal binning factor used */
- uint8_t binning_factor_y; /* vertical binning factor used */
- uint16_t hts;
+ u8 binning_factor_x; /* horizontal binning factor used */
+ u8 binning_factor_y; /* vertical binning factor used */
+ u16 hts;
};
struct atomisp_exposure {
};
/* Masks */
-#define ATOMISP_FOCUS_STATUS_MOVING (1U << 0)
-#define ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE (1U << 1)
+#define ATOMISP_FOCUS_STATUS_MOVING BIT(0)
+#define ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE BIT(1)
#define ATOMISP_FOCUS_STATUS_HOME_POSITION (3U << 2)
enum atomisp_camera_port {
__u32 type; /* Binary type */
__u32 reserved[3]; /* Set to zero */
};
+
/*
* Set Senor run mode
*/
__u32 mode;
};
-#define ATOMISP_ACC_FW_LOAD_FL_PREVIEW (1 << 0)
-#define ATOMISP_ACC_FW_LOAD_FL_COPY (1 << 1)
-#define ATOMISP_ACC_FW_LOAD_FL_VIDEO (1 << 2)
-#define ATOMISP_ACC_FW_LOAD_FL_CAPTURE (1 << 3)
-#define ATOMISP_ACC_FW_LOAD_FL_ACC (1 << 4)
-#define ATOMISP_ACC_FW_LOAD_FL_ENABLE (1 << 16)
+#define ATOMISP_ACC_FW_LOAD_FL_PREVIEW BIT(0)
+#define ATOMISP_ACC_FW_LOAD_FL_COPY BIT(1)
+#define ATOMISP_ACC_FW_LOAD_FL_VIDEO BIT(2)
+#define ATOMISP_ACC_FW_LOAD_FL_CAPTURE BIT(3)
+#define ATOMISP_ACC_FW_LOAD_FL_ACC BIT(4)
+#define ATOMISP_ACC_FW_LOAD_FL_ENABLE BIT(16)
#define ATOMISP_ACC_FW_LOAD_TYPE_NONE 0 /* Normal binary: don't use */
#define ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT 1 /* Stage on output */
/* Query sensor's 2A status */
#define V4L2_CID_2A_STATUS (V4L2_CID_CAMERA_LASTP1 + 18)
-#define V4L2_2A_STATUS_AE_READY (1 << 0)
-#define V4L2_2A_STATUS_AWB_READY (1 << 1)
+#define V4L2_2A_STATUS_AE_READY BIT(0)
+#define V4L2_2A_STATUS_AWB_READY BIT(1)
#define V4L2_CID_FMT_AUTO (V4L2_CID_CAMERA_LASTP1 + 19)
#include "atomisp_platform.h"
int atomisp_register_i2c_module(struct v4l2_subdev *subdev,
- struct camera_sensor_platform_data *plat_data,
- enum intel_v4l2_subdev_type type);
+ struct camera_sensor_platform_data *plat_data,
+ enum intel_v4l2_subdev_type type);
struct v4l2_subdev *atomisp_gmin_find_subdev(struct i2c_adapter *adapter,
struct i2c_board_info *board_info);
int atomisp_gmin_remove_subdev(struct v4l2_subdev *sd);
int gmin_get_var_int(struct device *dev, const char *var, int def);
int camera_sensor_csi(struct v4l2_subdev *sd, u32 port,
- u32 lanes, u32 format, u32 bayer_order, int flag);
+ u32 lanes, u32 format, u32 bayer_order, int flag);
struct camera_sensor_platform_data *gmin_camera_platform_data(
struct v4l2_subdev *subdev,
enum atomisp_input_format csi_format,
#define N_ATOMISP_INPUT_FORMAT (ATOMISP_INPUT_FORMAT_USER_DEF8 + 1)
-
-
enum intel_v4l2_subdev_type {
RAW_CAMERA = 1,
SOC_CAMERA = 2,
enum atomisp_bayer_order raw_bayer_order;
struct atomisp_sensor_mode_data data;
enum atomisp_input_format metadata_format;
- uint32_t metadata_width;
- uint32_t metadata_height;
- const uint32_t *metadata_effective_width;
+ u32 metadata_width;
+ u32 metadata_height;
+ const u32 *metadata_effective_width;
};
-extern const struct atomisp_platform_data *atomisp_get_platform_data(void);
-extern const struct atomisp_camera_caps *atomisp_get_default_camera_caps(void);
+const struct atomisp_platform_data *atomisp_get_platform_data(void);
+const struct atomisp_camera_caps *atomisp_get_default_camera_caps(void);
/* API from old platform_camera.h, new CPUID implementation */
#define __IS_SOC(x) (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && \
struct i2c_client;
struct firmware;
-extern int load_msr_list(struct i2c_client *client, char *path,
+int load_msr_list(struct i2c_client *client, char *path,
const struct firmware **fw);
-extern int apply_msr_data(struct i2c_client *client, const struct firmware *fw);
-extern void release_msr_list(struct i2c_client *client,
+int apply_msr_data(struct i2c_client *client, const struct firmware *fw);
+void release_msr_list(struct i2c_client *client,
const struct firmware *fw);
-
#endif /* ifndef __LIBMSRLISTHELPER_H__ */
#define LM3554_CLAMP_PERCENTAGE(val) \
clamp(val, LM3554_MIN_PERCENT, LM3554_MAX_PERCENT)
-#define LM3554_VALUE_TO_PERCENT(v, step) (((((unsigned long)(v))*(step))+50)/100)
-#define LM3554_PERCENT_TO_VALUE(p, step) (((((unsigned long)(p))*100)+(step>>1))/(step))
+#define LM3554_VALUE_TO_PERCENT(v, step) (((((unsigned long)(v)) * (step)) + 50) / 100)
+#define LM3554_PERCENT_TO_VALUE(p, step) (((((unsigned long)(p)) * 100) + (step >> 1)) / (step))
/* Product specific limits
* TODO: get these from platform data */
/* Flash brightness, input is percentage, output is [0..15] */
#define LM3554_FLASH_STEP \
- ((100ul*(LM3554_MAX_PERCENT)+((LM3554_FLASH_MAX_LVL)>>1))/((LM3554_FLASH_MAX_LVL)))
+ ((100ul * (LM3554_MAX_PERCENT) + ((LM3554_FLASH_MAX_LVL) >> 1)) / ((LM3554_FLASH_MAX_LVL)))
#define LM3554_FLASH_DEFAULT_BRIGHTNESS \
LM3554_VALUE_TO_PERCENT(13, LM3554_FLASH_STEP)
};
#endif /* _LM3554_H_ */
-
int atomisp_acc_s_mapped_arg(struct atomisp_sub_device *asd,
struct atomisp_acc_s_mapped_arg *arg);
-
/*
* Start acceleration.
* Return immediately, acceleration is left running in background.
#include "error_support.h"
#include "hrt/bits.h"
-
/* We should never need to run the flash for more than 2 frames.
* At 15fps this means 133ms. We set the timeout a bit longer.
* Each flash driver is supposed to set its own timeout, but
return 0;
}
+
int atomisp_freq_scaling(struct atomisp_device *isp,
enum atomisp_dfs_mode mode,
bool force)
v4l2_event_queue(asd->subdev.devnode, &event);
}
-
static void print_csi_rx_errors(enum mipi_port_id port,
struct atomisp_device *isp)
{
static void clear_irq_reg(struct atomisp_device *isp)
{
u32 msg_ret;
+
pci_read_config_dword(isp->pdev, PCI_INTERRUPT_CTRL, &msg_ret);
msg_ret |= 1 << INTR_IIR;
pci_write_config_dword(isp->pdev, PCI_INTERRUPT_CTRL, msg_ret);
}
if (irq_infos & IA_CSS_IRQ_INFO_ISYS_EVENTS_READY) {
- while (ia_css_dequeue_isys_event(&(eof_event.event)) ==
+ while (ia_css_dequeue_isys_event(&eof_event.event) ==
IA_CSS_SUCCESS) {
/* EOF Event does not have the css_pipe returned */
asd = __get_asd_from_port(isp, eof_event.event.port);
void atomisp_clear_css_buffer_counters(struct atomisp_sub_device *asd)
{
int i;
+
memset(asd->s3a_bufs_in_css, 0, sizeof(asd->s3a_bufs_in_css));
for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++)
memset(asd->metadata_bufs_in_css[i], 0,
/* need to know the atomisp pipe for frame buffers */
pipe = __atomisp_get_pipe(asd, stream_id, css_pipe_id, buf_type);
- if (pipe == NULL) {
+ if (!pipe) {
dev_err(isp->dev, "error getting atomisp pipe\n");
return;
}
* HAL will be unblocked.
*/
acc_pipe = asd->stream_env[i].pipes[CSS_PIPE_ID_ACC];
- if (acc_pipe != NULL) {
+ if (acc_pipe) {
acc_pipeline = ia_css_pipe_get_pipeline(acc_pipe);
if (acc_pipeline) {
struct ia_css_pipeline_stage *stage;
+
for (stage = acc_pipeline->stages; stage;
stage = stage->next) {
const struct ia_css_fw_info *fw;
+
fw = stage->firmware;
atomisp_acc_done(asd, fw->handle);
}
if (ret)
dev_warn(isp->dev,
"can't start streaming on sensor!\n");
-
}
if (depth_mode) {
#else
for (i = 0; i < isp->num_of_streams; i++) {
struct atomisp_sub_device *asd = &isp->asd[i];
+
pipe_wdt_cnt[i][0] +=
atomic_read(&asd->video_out_capture.wdt_count);
pipe_wdt_cnt[i][1] +=
if (css_recover) {
#endif
unsigned int old_dbglevel = dbg_level;
+
atomisp_css_debug_dump_sp_sw_debug_info();
atomisp_css_debug_dump_debug_info(__func__);
dbg_level = old_dbglevel;
dev_err(isp->dev, "%s, raw_buffer_locked_count %d\n",
__func__, asd->raw_buffer_locked_count);
- for (j = 0; j <= ATOMISP_MAX_EXP_ID/32; j++)
+ for (j = 0; j <= ATOMISP_MAX_EXP_ID / 32; j++)
dev_err(isp->dev, "%s, raw_buffer_bitmap[%d]: 0x%x\n",
__func__, j,
asd->raw_buffer_bitmap[j]);
} else {
for (i = 0; i < isp->num_of_streams; i++) {
struct atomisp_sub_device *asd = &isp->asd[i];
+
if (asd->streaming ==
ATOMISP_DEVICE_STREAMING_ENABLED) {
atomisp_clear_css_buffer_counters(asd);
#ifdef ISP2401
for (i = 0; i < isp->num_of_streams; i++) {
struct atomisp_sub_device *asd = &isp->asd[i];
+
if (asd->streaming ==
ATOMISP_DEVICE_STREAMING_ENABLED) {
atomisp_wdt_refresh(asd,
/* Disable wdt */
for (i = 0; i < isp->num_of_streams; i++) {
struct atomisp_sub_device *asd = &isp->asd[i];
+
atomisp_wdt_stop(asd, true);
}
atomisp_wdt_refresh_pipe(&asd->video_out_video_capture, delay);
}
-
void atomisp_wdt_stop_pipe(struct atomisp_video_pipe *pipe, bool sync)
#endif
{
struct atomisp_device *isp = asd->isp;
struct v4l2_control ctrl;
- if (isp->flash == NULL)
+ if (!isp->flash)
return;
if (asd->params.flash_state != ATOMISP_FLASH_REQUESTED &&
if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED)
continue;
atomisp_setup_flash(asd);
-
}
out:
rt_mutex_unlock(&isp->mutex);
return -EINVAL;
}
}
+
/*
* raw format match between SH format and V4L2 format
*/
{
struct atomisp_device *isp = asd->isp;
int err;
- uint16_t stream_id = atomisp_source_pad_to_stream_id(asd, source_pad);
+ u16 stream_id = atomisp_source_pad_to_stream_id(asd, source_pad);
if (atomisp_css_get_grid_info(asd, pipe_id, source_pad))
return;
if (flag == 0) {
/* Get gdc table from current setup */
struct atomisp_css_morph_table tab = {0};
+
atomisp_css_get_morph_table(asd, &tab);
config->width = tab.width;
pipe_cfg->bayer_ds_out_res.height /
input_config->effective_res.height + 1) / 2;
-
if (!asd->params.video_dis_en) {
/*
* We adjust the ispfilter_bq to:
w_padding = w_padding *
pipe_cfg->bayer_ds_out_res.width /
input_config->effective_res.width + 1;
- w_padding = roundup(w_padding/2, 1);
+ w_padding = roundup(w_padding / 2, 1);
bq_res->gdc_shift_bq.width_bq = bq_res->ispfilter_bq.width_bq / 2
+ w_padding;
mipi_info = atomisp_to_sensor_mipi_info(
isp->inputs[asd->input_curr].camera);
- if (mipi_info == NULL)
+ if (!mipi_info)
return -EINVAL;
- if (mipi_info->metadata_effective_width != NULL) {
+ if (mipi_info->metadata_effective_width) {
for (i = 0; i < md->height; i++)
md->effective_width[i] =
mipi_info->metadata_effective_width[i];
mipi_info = atomisp_to_sensor_mipi_info(
isp->inputs[asd->input_curr].camera);
- if (mipi_info == NULL)
+ if (!mipi_info)
return -EINVAL;
- if (mipi_info->metadata_effective_width != NULL) {
+ if (mipi_info->metadata_effective_width) {
for (i = 0; i < md->height; i++)
md->effective_width[i] =
mipi_info->metadata_effective_width[i];
asd->sensor_array_res.height,
out_res.width, out_res.height);
-
if ((dz_config->zoom_region.origin.x +
dz_config->zoom_region.resolution.width
> eff_res.width) ||
return 0;
}
-
/*
* Function to check the zoom region whether is effective
*/
{
struct atomisp_resolution config;
bool flag = false;
- unsigned int w , h;
+ unsigned int w, h;
memset(&config, 0, sizeof(struct atomisp_resolution));
from_user))
return -EFAULT;
css_param->update_flag.wb_config =
- (struct atomisp_wb_config *) &css_param->wb_config;
+ (struct atomisp_wb_config *)&css_param->wb_config;
}
if (arg->ob_config && (from_user || !cur_config->ob_config)) {
from_user))
return -EFAULT;
css_param->update_flag.ob_config =
- (struct atomisp_ob_config *) &css_param->ob_config;
+ (struct atomisp_ob_config *)&css_param->ob_config;
}
if (arg->dp_config && (from_user || !cur_config->dp_config)) {
from_user))
return -EFAULT;
css_param->update_flag.dp_config =
- (struct atomisp_dp_config *) &css_param->dp_config;
+ (struct atomisp_dp_config *)&css_param->dp_config;
}
if (asd->run_mode->val != ATOMISP_RUN_MODE_VIDEO) {
from_user))
return -EFAULT;
css_param->update_flag.nr_config =
- (struct atomisp_nr_config *) &css_param->nr_config;
+ (struct atomisp_nr_config *)&css_param->nr_config;
}
if (arg->ee_config && (from_user || !cur_config->ee_config)) {
from_user))
return -EFAULT;
css_param->update_flag.ee_config =
- (struct atomisp_ee_config *) &css_param->ee_config;
+ (struct atomisp_ee_config *)&css_param->ee_config;
}
if (arg->tnr_config && (from_user || !cur_config->tnr_config)) {
from_user))
return -EFAULT;
css_param->update_flag.a3a_config =
- (struct atomisp_3a_config *) &css_param->s3a_config;
+ (struct atomisp_3a_config *)&css_param->s3a_config;
}
if (arg->ctc_config && (from_user || !cur_config->ctc_config)) {
from_user))
return -EFAULT;
css_param->update_flag.fc_config =
- (struct atomisp_fc_config *) &css_param->fc_config;
+ (struct atomisp_fc_config *)&css_param->fc_config;
}
if (arg->macc_config && (from_user || !cur_config->macc_config)) {
from_user))
return -EFAULT;
css_param->update_flag.aa_config =
- (struct atomisp_aa_config *) &css_param->aa_config;
+ (struct atomisp_aa_config *)&css_param->aa_config;
}
if (arg->anr_config && (from_user || !cur_config->anr_config)) {
from_user))
return -EFAULT;
css_param->update_flag.xnr_table =
- (struct atomisp_xnr_table *) &css_param->xnr_table;
+ (struct atomisp_xnr_table *)&css_param->xnr_table;
}
if (arg->r_gamma_table && (from_user || !cur_config->r_gamma_table)) {
from_user))
return -EFAULT;
css_param->update_flag.anr_thres =
- (struct atomisp_anr_thres *) &css_param->anr_thres;
+ (struct atomisp_anr_thres *)&css_param->anr_thres;
}
if (from_user)
atomisp_css_shading_table_free(shading_table);
return -EFAULT;
}
-
}
#ifndef ISP2401
shading_table->sensor_width = source_st->sensor_width;
#endif
/* No need to update shading table if it is the same */
- if (old_table != NULL &&
+ if (old_table &&
old_table->sensor_width == shading_table->sensor_width &&
old_table->sensor_height == shading_table->sensor_height &&
old_table->width == shading_table->width &&
/* set LSC to CSS */
css_param->shading_table = shading_table;
css_param->update_flag.shading_table =
- (struct atomisp_shading_table *) shading_table;
- asd->params.sc_en = shading_table != NULL;
+ (struct atomisp_shading_table *)shading_table;
+ asd->params.sc_en = shading_table;
if (old_table)
atomisp_css_shading_table_free(old_table);
}
#ifndef ISP2401
- if (coefs->hor_coefs.odd_real == NULL ||
- coefs->hor_coefs.odd_imag == NULL ||
- coefs->hor_coefs.even_real == NULL ||
- coefs->hor_coefs.even_imag == NULL ||
- coefs->ver_coefs.odd_real == NULL ||
- coefs->ver_coefs.odd_imag == NULL ||
- coefs->ver_coefs.even_real == NULL ||
- coefs->ver_coefs.even_imag == NULL)
+ if (!coefs->hor_coefs.odd_real ||
+ !coefs->hor_coefs.odd_imag ||
+ !coefs->hor_coefs.even_real ||
+ !coefs->hor_coefs.even_imag ||
+ !coefs->ver_coefs.odd_real ||
+ !coefs->ver_coefs.odd_imag ||
+ !coefs->ver_coefs.even_real ||
+ !coefs->ver_coefs.even_imag)
#else
- if (dvs2_coefs.hor_coefs.odd_real == NULL ||
- dvs2_coefs.hor_coefs.odd_imag == NULL ||
- dvs2_coefs.hor_coefs.even_real == NULL ||
- dvs2_coefs.hor_coefs.even_imag == NULL ||
- dvs2_coefs.ver_coefs.odd_real == NULL ||
- dvs2_coefs.ver_coefs.odd_imag == NULL ||
- dvs2_coefs.ver_coefs.even_real == NULL ||
- dvs2_coefs.ver_coefs.even_imag == NULL)
+ if (!dvs2_coefs.hor_coefs.odd_real ||
+ !dvs2_coefs.hor_coefs.odd_imag ||
+ !dvs2_coefs.hor_coefs.even_real ||
+ !dvs2_coefs.hor_coefs.even_imag ||
+ !dvs2_coefs.ver_coefs.odd_real ||
+ !dvs2_coefs.ver_coefs.odd_imag ||
+ !dvs2_coefs.ver_coefs.even_real ||
+ !dvs2_coefs.ver_coefs.even_imag)
#endif
return -EINVAL;
atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info);
int ret = -EFAULT;
- if (stream == NULL) {
+ if (!stream) {
dev_err(asd->isp->dev, "%s: internal error!", __func__);
return -EINVAL;
}
css_param->dvs_6axis = dvs_6axis_config;
css_param->update_flag.dvs_6axis_config =
- (struct atomisp_dvs_6axis_config *) dvs_6axis_config;
+ (struct atomisp_dvs_6axis_config *)dvs_6axis_config;
return 0;
error:
if (old_morph_table)
atomisp_css_morph_table_free(old_morph_table);
css_param->update_flag.morph_table =
- (struct atomisp_morph_table *) morph_table;
+ (struct atomisp_morph_table *)morph_table;
return 0;
error:
if (ret)
return ret;
ret = atomisp_css_cp_dvs2_coefs(asd,
- (struct ia_css_dvs2_coefficients *) arg->dvs2_coefs,
+ (struct ia_css_dvs2_coefficients *)arg->dvs2_coefs,
css_param, false);
if (ret)
return ret;
struct atomisp_css_params *css_param = &asd->params.css_param;
int ret;
- if (asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream == NULL) {
+ if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) {
dev_err(asd->isp->dev, "%s: internal error!\n", __func__);
return -EINVAL;
}
goto apply_parameter_failed;
ret = atomisp_css_cp_dvs2_coefs(asd,
- (struct ia_css_dvs2_coefficients *) arg->dvs2_coefs,
+ (struct ia_css_dvs2_coefficients *)arg->dvs2_coefs,
css_param, true);
if (ret)
goto apply_parameter_failed;
atomisp_css_get_dvs_grid_info(
&asd->params.curr_grid_info);
- if (&config->info == NULL) {
+ if (!&config->info) {
dev_err(isp->dev, "ERROR: NULL pointer in grid_info\n");
return -EINVAL;
}
return 0;
}
-
control.id = V4L2_CID_COLORFX;
control.value = *effect;
ret =
int atomisp_bad_pixel(struct atomisp_sub_device *asd, int flag,
__s32 *value)
{
-
if (flag == 0) {
*value = asd->params.bad_pixel_en;
return 0;
int atomisp_fixed_pattern(struct atomisp_sub_device *asd, int flag,
__s32 *value)
{
-
if (flag == 0) {
*value = asd->params.fpn_en;
return 0;
case CSS_FRAME_FORMAT_YUYV:
case CSS_FRAME_FORMAT_RAW:
case CSS_FRAME_FORMAT_RGB565:
- return bytesperline/2;
+ return bytesperline / 2;
case CSS_FRAME_FORMAT_RGBA888:
- return bytesperline/4;
+ return bytesperline / 4;
/* The following cases could be removed, but we leave them
in to document the formats that are included. */
case CSS_FRAME_FORMAT_NV11:
struct atomisp_css_frame *raw_black_frame = NULL;
int ret;
- if (arg == NULL)
+ if (!arg)
return -EINVAL;
ret = atomisp_v4l2_framebuffer_to_css_frame(arg, &raw_black_frame);
mipi_info = atomisp_to_sensor_mipi_info(
isp->inputs[asd->input_curr].camera);
- if (mipi_info == NULL)
+ if (!mipi_info)
return -EINVAL;
memcpy(config, &mipi_info->data, sizeof(*config));
}
static void __atomisp_update_stream_env(struct atomisp_sub_device *asd,
- uint16_t stream_index, struct atomisp_input_stream_info *stream_info)
+ u16 stream_index, struct atomisp_input_stream_info *stream_info)
{
int i;
}
}
-static void __atomisp_init_stream_info(uint16_t stream_index,
+static void __atomisp_init_stream_info(u16 stream_index,
struct atomisp_input_stream_info *stream_info)
{
int i;
const struct atomisp_format_bridge *fmt;
struct atomisp_input_stream_info *stream_info =
(struct atomisp_input_stream_info *)snr_mbus_fmt->reserved;
- uint16_t stream_index;
+ u16 stream_index;
int source_pad = atomisp_subdev_source_pad(vdev);
int ret;
- if (isp->inputs[asd->input_curr].camera == NULL)
+ if (!isp->inputs[asd->input_curr].camera)
return -EINVAL;
stream_index = atomisp_source_pad_to_stream_id(asd, source_pad);
fmt = atomisp_get_format_bridge(f->fmt.pix.pixelformat);
- if (fmt == NULL) {
+ if (!fmt) {
dev_err(isp->dev, "unsupported pixelformat!\n");
fmt = atomisp_output_fmts;
}
snr_mbus_fmt->width, snr_mbus_fmt->height);
fmt = atomisp_get_format_bridge_from_mbus(snr_mbus_fmt->code);
- if (fmt == NULL) {
+ if (!fmt) {
dev_err(isp->dev, "unknown sensor format 0x%8.8x\n",
snr_mbus_fmt->code);
return -EINVAL;
/* Set the flag when resolution requested is
* beyond the max value supported by sensor
*/
- if (res_overflow != NULL)
+ if (res_overflow)
*res_overflow = true;
}
input_format = fc->css_stream_fmt;
} else {
struct v4l2_mbus_framefmt *sink;
+
sink = atomisp_subdev_get_ffmt(&asd->subdev, NULL,
V4L2_SUBDEV_FORMAT_ACTIVE,
ATOMISP_SUBDEV_PAD_SINK);
int (*configure_pp_input)(struct atomisp_sub_device *asd,
unsigned int width, unsigned int height) =
configure_pp_input_nop;
- uint16_t stream_index = atomisp_source_pad_to_stream_id(asd, source_pad);
+ u16 stream_index = atomisp_source_pad_to_stream_id(asd, source_pad);
const struct atomisp_in_fmt_conv *fc;
int ret;
ATOMISP_SUBDEV_PAD_SINK, V4L2_SEL_TGT_CROP);
format = atomisp_get_format_bridge(pix->pixelformat);
- if (format == NULL)
+ if (!format)
return -EINVAL;
if (isp->inputs[asd->input_curr].type != TEST_PATTERN &&
asd->copy_mode = false;
dev_dbg(asd->isp->dev, "copy_mode: %d\n", asd->copy_mode);
-
}
static int atomisp_set_fmt_to_snr(struct video_device *vdev,
struct atomisp_device *isp = asd->isp;
struct atomisp_input_stream_info *stream_info =
(struct atomisp_input_stream_info *)ffmt->reserved;
- uint16_t stream_index = ATOMISP_INPUT_STREAM_GENERAL;
+ u16 stream_index = ATOMISP_INPUT_STREAM_GENERAL;
int source_pad = atomisp_subdev_source_pad(vdev);
struct v4l2_subdev_fh fh;
int ret;
stream_index = atomisp_source_pad_to_stream_id(asd, source_pad);
format = atomisp_get_format_bridge(pixelformat);
- if (format == NULL)
+ if (!format)
return -EINVAL;
v4l2_fill_mbus_format(ffmt, &f->fmt.pix, format->mbus_code);
struct v4l2_mbus_framefmt isp_sink_fmt;
struct v4l2_mbus_framefmt isp_source_fmt = {0};
struct v4l2_rect isp_sink_crop;
- uint16_t source_pad = atomisp_subdev_source_pad(vdev);
+ u16 source_pad = atomisp_subdev_source_pad(vdev);
struct v4l2_subdev_fh fh;
int ret;
v4l2_fh_init(&fh.vfh, vdev);
format_bridge = atomisp_get_format_bridge(f->fmt.pix.pixelformat);
- if (format_bridge == NULL)
+ if (!format_bridge)
return -EINVAL;
pipe->sh_fmt = format_bridge->sh_fmt;
(asd->isp->inputs[asd->input_curr].camera_caps->
sensor[asd->sensor_curr].stream_num > 1)) {
/* For M10MO outputing YUV preview images. */
- uint16_t video_index =
+ u16 video_index =
atomisp_source_pad_to_stream_id(asd,
ATOMISP_SUBDEV_PAD_SOURCE_VIDEO);
output_info.padded_width, 8);
pipe->pix.sizeimage =
PAGE_ALIGN(f->fmt.pix.height * pipe->pix.bytesperline);
-
}
if (f->fmt.pix.field == V4L2_FIELD_ANY)
f->fmt.pix.field = V4L2_FIELD_NONE;
}
format_bridge = atomisp_get_format_bridge(f->fmt.pix.pixelformat);
- if (format_bridge == NULL) {
+ if (!format_bridge) {
dev_dbg(isp->dev, "atomisp_get_format_bridge err! fmt:0x%x\n",
f->fmt.pix.pixelformat);
return -EINVAL;
asd->params.sc_en = true;
out:
- if (free_table != NULL)
+ if (free_table)
atomisp_css_shading_table_free(free_table);
return ret;
int atomisp_ospm_dphy_up(struct atomisp_device *isp)
{
unsigned long flags;
+
dev_dbg(isp->dev, "%s\n", __func__);
spin_lock_irqsave(&isp->lock, flags);
return 0;
}
-
int atomisp_exif_makernote(struct atomisp_sub_device *asd,
struct atomisp_makernote_info *config)
{
V4L2_CID_START_ZSL_CAPTURE);
if (c) {
int ret;
+
dev_dbg(asd->isp->dev, "%s trigger ZSL capture request\n",
__func__);
/* TODO: use the cvf_config */
void atomisp_init_raw_buffer_bitmap(struct atomisp_sub_device *asd)
{
unsigned long flags;
+
spin_lock_irqsave(&asd->raw_buffer_bitmap_lock, flags);
memset(asd->raw_buffer_bitmap, 0, sizeof(asd->raw_buffer_bitmap));
asd->raw_buffer_locked_count = 0;
{
bool value;
- if (enable == NULL)
+ if (!enable)
return -EINVAL;
value = *enable > 0 ? true : false;
int atomisp_get_fmt(struct video_device *vdev, struct v4l2_format *f);
-
/* This function looks up the closest available resolution. */
int atomisp_try_fmt(struct video_device *vdev, struct v4l2_format *f,
bool *res_overflow);
struct atomisp_css_buffer *isp_css_buffer);
int atomisp_css_allocate_stat_buffers(struct atomisp_sub_device *asd,
- uint16_t stream_id,
+ u16 stream_id,
struct atomisp_s3a_buf *s3a_buf,
struct atomisp_dis_buf *dis_buf,
struct atomisp_metadata_buf *md_buf);
enum atomisp_css_frame_format format);
int atomisp_get_css_frame_info(struct atomisp_sub_device *asd,
- uint16_t source_pad,
+ u16 source_pad,
struct atomisp_css_frame_info *frame_info);
int atomisp_css_video_configure_viewfinder(struct atomisp_sub_device *asd,
static uint8_t atomisp_css2_hw_load_8(hrt_address addr)
{
unsigned long flags;
- uint8_t ret;
+ u8 ret;
spin_lock_irqsave(&mmio_lock, flags);
ret = _hrt_master_port_load_8(addr);
static uint16_t atomisp_css2_hw_load_16(hrt_address addr)
{
unsigned long flags;
- uint16_t ret;
+ u16 ret;
spin_lock_irqsave(&mmio_lock, flags);
ret = _hrt_master_port_load_16(addr);
static uint32_t atomisp_css2_hw_load_32(hrt_address addr)
{
unsigned long flags;
- uint32_t ret;
+ u32 ret;
spin_lock_irqsave(&mmio_lock, flags);
ret = _hrt_master_port_load_32(addr);
spin_lock_irqsave(&mmio_lock, flags);
for (i = 0; i < n; i++, _to++, _from++)
- _hrt_master_port_store_8(_to , *_from);
+ _hrt_master_port_store_8(_to, *_from);
spin_unlock_irqrestore(&mmio_lock, flags);
}
{
*data = atomisp_css2_hw_load_32(addr);
}
+
static int hmm_get_mmu_base_addr(unsigned int *mmu_base_addr)
{
- if (sh_mmu_mrfld.get_pd_base == NULL) {
+ if (!sh_mmu_mrfld.get_pd_base) {
dev_err(atomisp_dev, "get mmu base address failed.\n");
return -EINVAL;
}
asd->stream_prepared = false;
return 0;
}
+
static int __create_stream(struct atomisp_sub_device *asd,
struct atomisp_stream_env *stream_env)
{
for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) {
if (asd->stream_env[i].stream) {
-
dev_err(isp->dev,
"cannot destroy css pipes for stream[%d].\n",
i);
atomisp_isp_parameters_clean_up(&asd->params.config);
}
-
void atomisp_css_update_isp_params_on_pipe(struct atomisp_sub_device *asd,
struct ia_css_pipe *pipe)
{
}
int atomisp_css_allocate_stat_buffers(struct atomisp_sub_device *asd,
- uint16_t stream_id,
+ u16 stream_id,
struct atomisp_s3a_buf *s3a_buf,
struct atomisp_dis_buf *dis_buf,
struct atomisp_metadata_buf *md_buf)
|| asd->params.curr_grid_info.s3a_grid.height == 0)
&& asd->params.metadata_width_size == md_width) {
dev_dbg(isp->dev,
- "grid info change escape. memcmp=%d, s3a_user_stat=%d,"
- "dvs_stat=%d, s3a.width=%d, s3a.height=%d, metadata width =%d\n",
+ "grid info change escape. memcmp=%d, s3a_user_stat=%d,dvs_stat=%d, s3a.width=%d, s3a.height=%d, metadata width =%d\n",
!memcmp(&old_info, &asd->params.curr_grid_info,
sizeof(old_info)),
!!asd->params.s3a_user_stat, !!asd->params.dvs_stat,
else
ia_css_get_dvs2_statistics(asd->params.dvs_stat,
isp_css_buffer->css_buffer.data.stats_dvs);
-
}
}
enum atomisp_input_format format,
int isys_stream)
{
-
struct ia_css_stream_config *s_config =
&asd->stream_env[stream_id].stream_config;
enum atomisp_input_stream_id stream_id,
enum atomisp_input_format format)
{
-
struct ia_css_stream_config *s_config =
&asd->stream_env[stream_id].stream_config;
else
size_mem_words = CSS_MIPI_FRAME_BUFFER_SIZE_1;
dev_warn(asd->isp->dev,
- "ia_css_mipi_frame_calculate_size failed,"
- "applying pre-defined MIPI buffer size %u.\n",
+ "ia_css_mipi_frame_calculate_size failed,applying pre-defined MIPI buffer size %u.\n",
size_mem_words);
}
s_config->mipi_buffer_config.size_mem_words = size_mem_words;
WARN_ON(1);
return IA_CSS_PIPE_MODE_PREVIEW;
}
-
}
static void __configure_output(struct atomisp_sub_device *asd,
}
int atomisp_get_css_frame_info(struct atomisp_sub_device *asd,
- uint16_t source_pad,
+ u16 source_pad,
struct atomisp_css_frame_info *frame_info)
{
struct ia_css_pipe_info info;
struct atomisp_css_ctc_table *ctc_table)
{
int i;
- uint16_t *vamem_ptr = ctc_table->data.vamem_1;
+ u16 *vamem_ptr = ctc_table->data.vamem_1;
int data_size = IA_CSS_VAMEM_1_CTC_TABLE_SIZE;
bool valid = false;
try again. */
return -EAGAIN;
- if (coefs->hor_coefs.odd_real == NULL ||
- coefs->hor_coefs.odd_imag == NULL ||
- coefs->hor_coefs.even_real == NULL ||
- coefs->hor_coefs.even_imag == NULL ||
- coefs->ver_coefs.odd_real == NULL ||
- coefs->ver_coefs.odd_imag == NULL ||
- coefs->ver_coefs.even_real == NULL ||
- coefs->ver_coefs.even_imag == NULL ||
- asd->params.css_param.dvs2_coeff->hor_coefs.odd_real == NULL ||
- asd->params.css_param.dvs2_coeff->hor_coefs.odd_imag == NULL ||
- asd->params.css_param.dvs2_coeff->hor_coefs.even_real == NULL ||
- asd->params.css_param.dvs2_coeff->hor_coefs.even_imag == NULL ||
- asd->params.css_param.dvs2_coeff->ver_coefs.odd_real == NULL ||
- asd->params.css_param.dvs2_coeff->ver_coefs.odd_imag == NULL ||
- asd->params.css_param.dvs2_coeff->ver_coefs.even_real == NULL ||
- asd->params.css_param.dvs2_coeff->ver_coefs.even_imag == NULL)
+ if (!coefs->hor_coefs.odd_real ||
+ !coefs->hor_coefs.odd_imag ||
+ !coefs->hor_coefs.even_real ||
+ !coefs->hor_coefs.even_imag ||
+ !coefs->ver_coefs.odd_real ||
+ !coefs->ver_coefs.odd_imag ||
+ !coefs->ver_coefs.even_real ||
+ !coefs->ver_coefs.even_imag ||
+ !asd->params.css_param.dvs2_coeff->hor_coefs.odd_real ||
+ !asd->params.css_param.dvs2_coeff->hor_coefs.odd_imag ||
+ !asd->params.css_param.dvs2_coeff->hor_coefs.even_real ||
+ !asd->params.css_param.dvs2_coeff->hor_coefs.even_imag ||
+ !asd->params.css_param.dvs2_coeff->ver_coefs.odd_real ||
+ !asd->params.css_param.dvs2_coeff->ver_coefs.odd_imag ||
+ !asd->params.css_param.dvs2_coeff->ver_coefs.even_real ||
+ !asd->params.css_param.dvs2_coeff->ver_coefs.even_imag)
return -EINVAL;
if (copy_from_user(asd->params.css_param.dvs2_coeff->hor_coefs.odd_real,
asd->params.css_param.dz_config.dy = zoom;
asd->params.css_param.update_flag.dz_config =
- (struct atomisp_dz_config *) &asd->params.css_param.dz_config;
+ (struct atomisp_dz_config *)&asd->params.css_param.dz_config;
asd->params.css_update_params_needed = true;
}
return 0;
}
-
/*
* Function to set/get image stablization statistics
*/
struct atomisp_dis_buf *dis_buf;
unsigned long flags;
- if (asd->params.dvs_stat->hor_prod.odd_real == NULL ||
- asd->params.dvs_stat->hor_prod.odd_imag == NULL ||
- asd->params.dvs_stat->hor_prod.even_real == NULL ||
- asd->params.dvs_stat->hor_prod.even_imag == NULL ||
- asd->params.dvs_stat->ver_prod.odd_real == NULL ||
- asd->params.dvs_stat->ver_prod.odd_imag == NULL ||
- asd->params.dvs_stat->ver_prod.even_real == NULL ||
- asd->params.dvs_stat->ver_prod.even_imag == NULL)
+ if (!asd->params.dvs_stat->hor_prod.odd_real ||
+ !asd->params.dvs_stat->hor_prod.odd_imag ||
+ !asd->params.dvs_stat->hor_prod.even_real ||
+ !asd->params.dvs_stat->hor_prod.even_imag ||
+ !asd->params.dvs_stat->ver_prod.odd_real ||
+ !asd->params.dvs_stat->ver_prod.odd_imag ||
+ !asd->params.dvs_stat->ver_prod.even_real ||
+ !asd->params.dvs_stat->ver_prod.even_imag)
return -EINVAL;
/* isp needs to be streaming to get DIS statistics */
if (nm == 0)
return -EPERM;
- if (bd == NULL)
+ if (!bd)
return -EPERM;
for (i = 1; i < sh_css_num_binaries; i++)
dev_dbg(atomisp_dev, "Num%d binary id is %d, name is %s\n", i,
- bd[i-1].header.info.isp.sp.id, bd[i-1].name);
+ bd[i - 1].header.info.isp.sp.id, bd[i - 1].name);
return 0;
}
return ret;
}
+
void atomisp_en_dz_capt_pipe(struct atomisp_sub_device *asd, bool enable)
{
ia_css_en_dz_capt_pipe(
return 0;
}
-
static int get_atomisp_metadata_stat32(struct atomisp_metadata *kp,
struct atomisp_metadata32 __user *up)
{
return 0;
}
-
static int put_atomisp_metadata_stat32(struct atomisp_metadata *kp,
struct atomisp_metadata32 __user *up)
{
struct atomisp_overlay32 __user *up)
{
compat_uptr_t frame;
+
if (!access_ok(up, sizeof(struct atomisp_overlay32)) ||
get_user(frame, &up->frame) ||
get_user(kp->bg_y, &up->bg_y) ||
struct atomisp_acc_fw_load_to_pipe32 __user *up)
{
compat_uptr_t data;
+
if (!access_ok(up, sizeof(struct atomisp_acc_fw_load_to_pipe32)) ||
get_user(kp->flags, &up->flags) ||
get_user(kp->fw_handle, &up->fw_handle) ||
struct atomisp_acc_fw_load_to_pipe32 __user *up)
{
compat_uptr_t data = (compat_uptr_t)((uintptr_t)kp->data);
+
if (!access_ok(up, sizeof(struct atomisp_acc_fw_load_to_pipe32)) ||
put_user(kp->flags, &up->flags) ||
put_user(kp->fw_handle, &up->fw_handle) ||
struct atomisp_sensor_ae_bracketing_lut32 __user *up)
{
compat_uptr_t lut;
+
if (!access_ok(up, sizeof(struct atomisp_sensor_ae_bracketing_lut32)) ||
get_user(kp->lut_size, &up->lut_size) ||
get_user(lut, &up->lut))
long atomisp_compat_ioctl32(struct file *file,
unsigned int cmd, unsigned long arg)
{
-
struct video_device *vdev = video_devdata(file);
struct atomisp_device *isp = video_get_drvdata(vdev);
long ret = -ENOIOCTLCMD;
struct atomisp_dis_statistics32 {
struct atomisp_dvs2_statistics32 dvs2_stat;
- uint32_t exp_id;
+ u32 exp_id;
};
struct atomisp_dis_coefficients32 {
struct atomisp_grid_info grid_info;
compat_uptr_t data;
compat_uptr_t rgby_data;
- uint32_t exp_id;
- uint32_t isp_config_id;
+ u32 exp_id;
+ u32 isp_config_id;
};
struct atomisp_metadata_with_type32 {
/* to specify which type of metadata to get */
enum atomisp_metadata_type type;
compat_uptr_t data;
- uint32_t width;
- uint32_t height;
- uint32_t stride; /* in bytes */
- uint32_t exp_id; /* exposure ID */
+ u32 width;
+ u32 height;
+ u32 stride; /* in bytes */
+ u32 exp_id; /* exposure ID */
compat_uptr_t effective_width;
};
struct atomisp_metadata32 {
compat_uptr_t data;
- uint32_t width;
- uint32_t height;
- uint32_t stride;
- uint32_t exp_id;
+ u32 width;
+ u32 height;
+ u32 stride;
+ u32 exp_id;
compat_uptr_t effective_width;
};
* Unique ID to track which config was actually applied to a particular
* frame, driver will send this id back with output frame together.
*/
- uint32_t isp_config_id;
- uint32_t per_frame_setting;
+ u32 isp_config_id;
+ u32 per_frame_setting;
};
struct atomisp_acc_fw_load_to_pipe32 {
};
struct atomisp_dvs_6axis_config32 {
- uint32_t exp_id;
- uint32_t width_y;
- uint32_t height_y;
- uint32_t width_uv;
- uint32_t height_uv;
+ u32 exp_id;
+ u32 width_y;
+ u32 height_y;
+ u32 width_uv;
+ u32 height_uv;
compat_uptr_t xcoords_y;
compat_uptr_t ycoords_y;
compat_uptr_t xcoords_uv;
static struct v4l2_mbus_framefmt *__csi2_get_format(struct
atomisp_mipi_csi2_device
- *csi2,
+ * csi2,
struct
- v4l2_subdev_pad_config *cfg,
+ v4l2_subdev_pad_config * cfg,
enum
v4l2_subdev_format_whence
which, unsigned int pad)
*/
static int csi2_set_stream(struct v4l2_subdev *sd, int enable)
{
- return 0;
+ return 0;
}
/* subdev core operations */
static const short int coeff_dat_settle[] = { 85, -2 };
static const int TERMEN_DEFAULT = 0 * 0;
static const int SETTLE_DEFAULT = 0x480;
+
static const hrt_address csi2_port_base[] = {
[ATOMISP_CAMERA_PORT_PRIMARY] = CSI2_PORT_A_BASE,
[ATOMISP_CAMERA_PORT_SECONDARY] = CSI2_PORT_B_BASE,
mipi_freq, SETTLE_DEFAULT);
for (n = 0; n < csi2_port_lanes[port] + 1; n++) {
hrt_address base = csi2_port_base[port] + csi2_lane_base[n];
+
atomisp_store_uint32(base + CSI2_REG_RX_CSI_DLY_CNT_TERMEN,
n == 0 ? clk_termen : dat_termen);
atomisp_store_uint32(base + CSI2_REG_RX_CSI_DLY_CNT_SETTLE,
atomisp_mipi_csi2_cleanup(isp);
return ret;
}
-
#define CSI2_PAD_SOURCE 1
#define CSI2_PADS_NUM 2
-#define CSI2_OUTPUT_ISP_SUBDEV (1 << 0)
-#define CSI2_OUTPUT_MEMORY (1 << 1)
+#define CSI2_OUTPUT_ISP_SUBDEV BIT(0)
+#define CSI2_OUTPUT_MEMORY BIT(1)
struct atomisp_device;
struct v4l2_device;
unsigned int run_mode;
};
-
struct atomisp_dfs_config {
unsigned int lowest_freq;
unsigned int max_freq_at_vmin;
unsigned int dbgopt;
};
-#define OPTION_BIN_LIST (1<<0)
-#define OPTION_BIN_RUN (1<<1)
-#define OPTION_MEM_STAT (1<<2)
+#define OPTION_BIN_LIST BIT(0)
+#define OPTION_BIN_RUN BIT(1)
+#define OPTION_MEM_STAT BIT(2)
#define OPTION_VALID (OPTION_BIN_LIST \
| OPTION_BIN_RUN \
| OPTION_MEM_STAT)
/* only support file injection on subdev0 */
struct atomisp_sub_device *asd = &isp->asd[0];
struct v4l2_mbus_framefmt *isp_sink_fmt;
+
if (format->pad)
return -EINVAL;
isp_sink_fmt = atomisp_subdev_get_ffmt(&asd->subdev, NULL,
struct v4l2_subdev_format *format)
{
struct v4l2_mbus_framefmt *fmt = &format->format;
+
if (format->pad)
return -EINVAL;
file_input_get_fmt(sd, cfg, format);
file_dev->isp = isp;
file_dev->work_queue = alloc_workqueue(isp->v4l2_dev.name, 0, 1);
- if (file_dev->work_queue == NULL) {
+ if (!file_dev->work_queue) {
dev_err(isp->dev, "Failed to initialize file inject workq\n");
return -ENOMEM;
}
return 0;
}
-
/* queue all available buffers to css */
int atomisp_qbuffers_to_css(struct atomisp_sub_device *asd)
{
asd->sensor_array_res.width = 0;
atomisp_css_init_struct(asd);
}
+
/*
* file operation functions
*/
unsigned int atomisp_dev_users(struct atomisp_device *isp)
{
unsigned int i, sum;
+
for (i = 0, sum = 0; i < isp->num_of_streams; i++)
sum += atomisp_subdev_users(&isp->asd[i]);
v4l2_fh_init(&fh.vfh, vdev);
req.count = 0;
- if (isp == NULL)
+ if (!isp)
return -EBADF;
mutex_lock(&isp->streamoff_mutex);
*/
if (!isp->sw_contex.file_input && asd->fmt_auto->val) {
struct v4l2_mbus_framefmt isp_sink_fmt = { 0 };
+
atomisp_subdev_set_ffmt(&asd->subdev, fh.pad,
V4L2_SUBDEV_FORMAT_ACTIVE,
ATOMISP_SUBDEV_PAD_SINK, &isp_sink_fmt);
/* clear the sink pad for file input */
if (isp->sw_contex.file_input && asd->fmt_auto->val) {
struct v4l2_mbus_framefmt isp_sink_fmt = { 0 };
+
atomisp_subdev_set_ffmt(&asd->subdev, fh.pad,
V4L2_SUBDEV_FORMAT_ACTIVE,
ATOMISP_SUBDEV_PAD_SINK, &isp_sink_fmt);
mutex_lock(&q->vb_lock);
for (i = 0; i < VIDEO_MAX_FRAME; i++) {
struct videobuf_buffer *buf = q->bufs[i];
- if (buf == NULL)
+
+ if (!buf)
continue;
map = kzalloc(sizeof(struct videobuf_mapping), GFP_KERNEL);
buf->boff == offset) {
vm_mem = buf->priv;
ret = frame_mmap(isp, vm_mem->vaddr, vma);
- vma->vm_flags |= VM_IO|VM_DONTEXPAND|VM_DONTDUMP;
+ vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP;
break;
}
}
ia_css_ptr load = in_frame->data;
ia_css_ptr store = load;
- buffer = kmalloc(width*sizeof(load), GFP_KERNEL);
+ buffer = kmalloc_array(width, sizeof(load), GFP_KERNEL);
if (!buffer)
return -ENOMEM;
load += ISP_LEFT_PAD;
for (i = 0; i < height; i++) {
- ret = hmm_load(load, buffer, width*sizeof(load));
+ ret = hmm_load(load, buffer, width * sizeof(load));
if (ret < 0)
goto remove_pad_error;
- ret = hmm_store(store, buffer, width*sizeof(store));
+ ret = hmm_store(store, buffer, width * sizeof(store));
if (ret < 0)
goto remove_pad_error;
goto error;
}
raw_virt_addr = asd->raw_output_frame;
- if (raw_virt_addr == NULL) {
+ if (!raw_virt_addr) {
dev_err(isp->dev, "Failed to request RAW frame\n");
ret = -EINVAL;
goto error;
goto error;
}
raw_virt_addr->data_bytes = origin_size;
- vma->vm_flags |= VM_IO|VM_DONTEXPAND|VM_DONTDUMP;
+ vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP;
rt_mutex_unlock(&isp->mutex);
return 0;
}
#endif
.poll = atomisp_poll,
};
-
#endif
#define DIV_NEAREST_STEP(n, d, step) \
- round_down((2 * (n) + (d) * (step))/(2 * (d)), (step))
+ round_down((2 * (n) + (d) * (step)) / (2 * (d)), (step))
struct atomisp_input_subdev {
unsigned int type;
int running_freq;
};
-
#define ATOMISP_DEVICE_STREAMING_DISABLED 0
#define ATOMISP_DEVICE_STREAMING_ENABLED 1
#define ATOMISP_DEVICE_STREAMING_STOPPING 2
#define atomisp_is_wdt_running(a) timer_pending(&(a)->wdt)
#ifdef ISP2401
-extern void atomisp_wdt_refresh_pipe(struct atomisp_video_pipe *pipe,
+void atomisp_wdt_refresh_pipe(struct atomisp_video_pipe *pipe,
unsigned int delay);
#endif
-extern void atomisp_wdt_refresh(struct atomisp_sub_device *asd, unsigned int delay);
+void atomisp_wdt_refresh(struct atomisp_sub_device *asd, unsigned int delay);
#ifndef ISP2401
-extern void atomisp_wdt_start(struct atomisp_sub_device *asd);
+void atomisp_wdt_start(struct atomisp_sub_device *asd);
#else
-extern void atomisp_wdt_start(struct atomisp_video_pipe *pipe);
-extern void atomisp_wdt_stop_pipe(struct atomisp_video_pipe *pipe, bool sync);
+void atomisp_wdt_start(struct atomisp_video_pipe *pipe);
+void atomisp_wdt_stop_pipe(struct atomisp_video_pipe *pipe, bool sync);
#endif
-extern void atomisp_wdt_stop(struct atomisp_sub_device *asd, bool sync);
+void atomisp_wdt_stop(struct atomisp_sub_device *asd, bool sync);
#endif /* __ATOMISP_INTERNAL_H__ */
#include <linux/delay.h>
#include <linux/pci.h>
-
#include <media/v4l2-ioctl.h>
#include <media/v4l2-event.h>
#include <media/videobuf-vmalloc.h>
.default_value = 0,
},
};
+
static const u32 ctrls_num = ARRAY_SIZE(ci_v4l2_controls);
/*
return 0;
}
+
/*
* get input are used to get current primary/secondary camera
*/
return 0;
}
+
/*
* set input are used to set current primary/secondary camera
*/
* 1: already in use
* 2: if in use, whether it is used by other streams
*/
- if (isp->inputs[input].asd != NULL && isp->inputs[input].asd != asd) {
+ if (isp->inputs[input].asd && isp->inputs[input].asd != asd) {
dev_err(isp->dev,
"%s, camera is already used by stream: %d\n", __func__,
isp->inputs[input].asd->index);
{
struct videobuf_vmalloc_memory *vm_mem;
- if (vb == NULL)
+ if (!vb)
return;
vm_mem = vb->priv;
struct atomisp_css_frame_info frame_info;
struct atomisp_css_frame *frame;
struct videobuf_vmalloc_memory *vm_mem;
- uint16_t source_pad = atomisp_subdev_source_pad(vdev);
- uint16_t stream_id = atomisp_source_pad_to_stream_id(asd, source_pad);
+ u16 source_pad = atomisp_subdev_source_pad(vdev);
+ u16 stream_id = atomisp_source_pad_to_stream_id(asd, source_pad);
int ret = 0, i = 0;
if (req->count == 0) {
*/
if (buf->memory == V4L2_MEMORY_USERPTR) {
struct hrt_userbuffer_attr attributes;
+
vb = pipe->capq.bufs[buf->index];
vm_mem = vb->priv;
if (!vm_mem) {
asd->pending_capture_request++;
dev_dbg(isp->dev, "Add one pending capture request.\n");
#else
- if (asd->re_trigger_capture) {
+ if (asd->re_trigger_capture) {
ret = atomisp_css_offline_capture_configure(asd,
asd->params.offline_parm.num_captures,
asd->params.offline_parm.skip_frames,
dev_dbg(isp->dev, "%s Trigger capture again ret=%d\n",
__func__, ret);
- } else {
+ } else {
asd->pending_capture_request++;
asd->re_trigger_capture = false;
dev_dbg(isp->dev, "Add one pending capture request.\n");
- }
+ }
#endif
}
rt_mutex_unlock(&isp->mutex);
*/
for (i = 0; i < isp->num_of_streams; i++) {
int sensor_index = isp->asd[i].input_curr;
+
if (isp->inputs[sensor_index].camera_caps->
sensor[isp->asd[i].sensor_curr].is_slave)
slave = sensor_index;
for (i = 0; i < isp->num_of_streams; i++) {
int sensor_index = isp->asd[i].input_curr;
+
if (isp->inputs[sensor_index].camera_caps->
sensor[isp->asd[i].sensor_curr].is_slave) {
v4l2_event_queue(isp->asd[i].subdev.devnode, &event);
/* manually to 128 in case of 13MPx snapshot and to 1 otherwise. */
static void atomisp_dma_burst_len_cfg(struct atomisp_sub_device *asd)
{
-
struct v4l2_mbus_framefmt *sink;
+
sink = atomisp_subdev_get_ffmt(&asd->subdev, NULL,
V4L2_SUBDEV_FORMAT_ACTIVE,
ATOMISP_SUBDEV_PAD_SINK);
- if (sink->width * sink->height >= 4096*3072)
+ if (sink->width * sink->height >= 4096 * 3072)
atomisp_store_uint32(DMA_BURST_SIZE_REG, 0x7F);
else
atomisp_store_uint32(DMA_BURST_SIZE_REG, 0x00);
sensor_start_stream = atomisp_sensor_start_stream(asd);
spin_lock_irqsave(&pipe->irq_lock, irqflags);
- if (list_empty(&(pipe->capq.stream))) {
+ if (list_empty(&pipe->capq.stream)) {
spin_unlock_irqrestore(&pipe->irq_lock, irqflags);
dev_dbg(isp->dev, "no buffer in the queue\n");
ret = -EINVAL;
ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW &&
atomisp_subdev_source_pad(vdev) !=
ATOMISP_SUBDEV_PAD_SOURCE_VIDEO) {
-
if (isp->inputs[asd->input_curr].camera_caps->multi_stream_ctrl) {
v4l2_subdev_call(isp->inputs[asd->input_curr].camera,
video, s_stream, 0);
if (isp->sw_contex.power_state == ATOM_ISP_POWER_UP) {
unsigned int i;
bool recreate_streams[MAX_STREAM_NUM] = {0};
+
if (isp->isp_timeout)
dev_err(isp->dev, "%s: Resetting with WA activated",
__func__);
rt_mutex_unlock(&isp->mutex);
return ret;
}
+
/*
* To query the attributes of a control.
* applications set the id field of a struct v4l2_queryctrl and call the
&& !atomisp_is_mbuscode_raw(src->code);
}
-uint16_t atomisp_subdev_source_pad(struct video_device * vdev)
+uint16_t atomisp_subdev_source_pad(struct video_device *vdev)
{
struct media_link *link;
- uint16_t ret = 0;
+ u16 ret = 0;
+
list_for_each_entry(link, &vdev->entity.links, list) {
if (link->source) {
ret = link->source->index;
struct v4l2_rect *atomisp_subdev_get_rect(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
- uint32_t which, uint32_t pad,
+ u32 which, uint32_t pad,
uint32_t target)
{
struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd);
static void isp_subdev_propagate(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
- uint32_t which, uint32_t pad, uint32_t target,
+ u32 which, uint32_t pad, uint32_t target,
uint32_t flags)
{
struct v4l2_mbus_framefmt *ffmt[ATOMISP_SUBDEV_PADS_NUM];
int atomisp_subdev_set_selection(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
- uint32_t which, uint32_t pad, uint32_t target,
- uint32_t flags, struct v4l2_rect *r)
+ u32 which, uint32_t pad, uint32_t target,
+ u32 flags, struct v4l2_rect *r)
{
struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd);
struct atomisp_device *isp = isp_sd->isp;
struct v4l2_mbus_framefmt *ffmt[ATOMISP_SUBDEV_PADS_NUM];
- uint16_t vdev_pad = atomisp_subdev_source_pad(sd->devnode);
+ u16 vdev_pad = atomisp_subdev_source_pad(sd->devnode);
struct v4l2_rect *crop[ATOMISP_SUBDEV_PADS_NUM],
*comp[ATOMISP_SUBDEV_PADS_NUM];
enum atomisp_input_stream_id stream_id;
struct v4l2_subdev_selection *sel)
{
int rval = isp_subdev_validate_rect(sd, sel->pad, sel->target);
+
if (rval)
return rval;
void atomisp_subdev_set_ffmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg, uint32_t which,
- uint32_t pad, struct v4l2_mbus_framefmt *ffmt)
+ u32 pad, struct v4l2_mbus_framefmt *ffmt)
{
struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd);
struct atomisp_device *isp = isp_sd->isp;
struct v4l2_mbus_framefmt *__ffmt =
atomisp_subdev_get_ffmt(sd, cfg, which, pad);
- uint16_t vdev_pad = atomisp_subdev_source_pad(sd->devnode);
+ u16 vdev_pad = atomisp_subdev_source_pad(sd->devnode);
enum atomisp_input_stream_id stream_id;
dev_dbg(isp->dev, "ffmt: pad %s w %d h %d code 0x%8.8x which %s\n",
{
struct atomisp_sub_device *asd;
int i, j, ret = 0;
+
isp->num_of_streams = 2;
for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
for (j = 0; j < isp->num_of_streams; j++) {
struct atomisp_in_fmt_conv {
u32 code;
- uint8_t bpp; /* bits per pixel */
- uint8_t depth; /* uncompressed */
+ u8 bpp; /* bits per pixel */
+ u8 depth; /* uncompressed */
enum atomisp_input_format atomisp_in_fmt;
enum atomisp_css_bayer_order bayer_order;
enum atomisp_input_format css_stream_fmt;
struct atomisp_device *isp;
struct v4l2_pix_format pix;
- uint32_t sh_fmt;
+ u32 sh_fmt;
struct atomisp_sub_device *asd;
* translate to ia_css_frame * and then set to CSS.
*/
void *output_frame;
- uint32_t isp_config_id;
+ u32 isp_config_id;
/* Indicates which parameters need to be updated. */
struct atomisp_parameters update_flag;
struct ia_css_3a_statistics *s3a_user_stat;
void *metadata_user[ATOMISP_METADATA_TYPE_NUM];
- uint32_t metadata_width_size;
+ u32 metadata_width_size;
struct ia_css_dvs2_statistics *dvs_stat;
struct atomisp_css_dvs_6axis *dvs_6axis;
- uint32_t exp_id;
+ u32 exp_id;
int dvs_hor_coef_bytes;
int dvs_ver_coef_bytes;
int dvs_ver_proj_bytes;
struct v4l2_subdev subdev;
struct media_pad pads[ATOMISP_SUBDEV_PADS_NUM];
struct atomisp_pad_format fmt[ATOMISP_SUBDEV_PADS_NUM];
- uint16_t capture_pad; /* main capture pad; defines much of isp config */
+ u16 capture_pad; /* main capture pad; defines much of isp config */
enum atomisp_subdev_input_entity input;
unsigned int output;
bool copy_mode; /* CSI2+ use copy mode */
bool yuvpp_mode; /* CSI2+ yuvpp pipe */
- int raw_buffer_bitmap[ATOMISP_MAX_EXP_ID/32 + 1]; /* Record each Raw Buffer lock status */
+ int raw_buffer_bitmap[ATOMISP_MAX_EXP_ID / 32 + 1]; /* Record each Raw Buffer lock status */
int raw_buffer_locked_count;
spinlock_t raw_buffer_bitmap_lock;
uint32_t pad);
struct v4l2_rect *atomisp_subdev_get_rect(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
- uint32_t which, uint32_t pad,
+ u32 which, uint32_t pad,
uint32_t target);
int atomisp_subdev_set_selection(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
- uint32_t which, uint32_t pad, uint32_t target,
- uint32_t flags, struct v4l2_rect *r);
+ u32 which, uint32_t pad, uint32_t target,
+ u32 flags, struct v4l2_rect *r);
/* Actually set the format */
void atomisp_subdev_set_ffmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg, uint32_t which,
- uint32_t pad, struct v4l2_mbus_framefmt *ffmt);
+ u32 pad, struct v4l2_mbus_framefmt *ffmt);
int atomisp_update_run_mode(struct atomisp_sub_device *asd);
void atomisp_tpg_cleanup(struct atomisp_device *isp)
{
-
}
int atomisp_tpg_init(struct atomisp_device *isp)
),
TP_printk(
- "<%s> User ptr memory:%d pages,\tISP private memory used:%d"
- " pages:\tsysFP system size:%d,\treserved size:%d"
- "\tcamFP sysUse:%d,\tdycUse:%d,\tresUse:%d.\n",
+ "<%s> User ptr memory:%d pages,\tISP private memory used:%d pages:\tsysFP system size:%d,\treserved size:%d\tcamFP sysUse:%d,\tdycUse:%d,\tresUse:%d.\n",
__entry->name, __entry->uptr_size, __entry->counter,
__entry->sys_size, __entry->sys_res_size, __entry->cam_sys_use,
__entry->cam_dyc_use, __entry->cam_res_use)
return 0;
}
-
/*
* WA for DDR DVFS enable/disable
* By default, ISP will force DDR DVFS 1600MHz before disable DVFS
}
}
-
/* Workaround for pmu_nc_set_power_state not ready in MRFLD */
int atomisp_mrfld_power_up(struct atomisp_device *isp)
{
int ret, raw_index = -1;
pdata = atomisp_get_platform_data();
- if (pdata == NULL) {
+ if (!pdata) {
dev_err(isp->dev, "no platform data available\n");
return 0;
}
i2c_get_adapter(subdevs->v4l2_subdev.i2c_adapter_id);
int sensor_num, i;
- if (adapter == NULL) {
+ if (!adapter) {
dev_err(isp->dev,
"Failed to find i2c adapter for subdev %s\n",
board_info->type);
continue;
}
- if (subdev == NULL) {
+ if (!subdev) {
dev_warn(isp->dev, "Subdev %s detection fail\n",
board_info->type);
continue;
dev_dbg(isp->dev, "unknown subdev probed\n");
break;
}
-
}
/*
asd->delayed_init_workq =
alloc_workqueue(isp->v4l2_dev.name, WQ_CPU_INTENSIVE,
1);
- if (asd->delayed_init_workq == NULL) {
+ if (!asd->delayed_init_workq) {
dev_err(isp->dev,
"Failed to initialize delayed init workq\n");
ret = -ENOMEM;
goto error_isp_subdev;
}
-
return 0;
error_isp_subdev:
atomic_set(&isp->wdt_work_queued, 0);
isp->wdt_work_queue = alloc_workqueue(isp->v4l2_dev.name, 0, 1);
- if (isp->wdt_work_queue == NULL) {
+ if (!isp->wdt_work_queue) {
dev_err(isp->dev, "Failed to initialize wdt work queue\n");
err = -ENOMEM;
goto alloc_fail;
atomisp_dev = &dev->dev;
pdata = atomisp_get_platform_data();
- if (pdata == NULL)
+ if (!pdata)
dev_warn(&dev->dev, "no platform data available\n");
err = pcim_enable_device(dev);
(ATOMISP_HW_REVISION_ISP2400
<< ATOMISP_HW_REVISION_SHIFT) |
ATOMISP_HW_STEPPING_B0;
-#ifdef FIXME
+#ifdef FIXME
if (INTEL_MID_BOARD(3, TABLET, BYT, BLK, PRO, CRV2) ||
INTEL_MID_BOARD(3, TABLET, BYT, BLK, ENG, CRV2)) {
isp->dfs = &dfs_config_byt_cr;
isp->hpll_freq = HPLL_FREQ_2000MHZ;
} else
-#endif
+#endif
{
isp->dfs = &dfs_config_byt;
isp->hpll_freq = HPLL_FREQ_1600MHZ;
* @param elems An array of elements.
* @param desc The descriptor set to the size using ia_css_circbuf_desc_init().
*/
-extern void ia_css_circbuf_create(
+void ia_css_circbuf_create(
ia_css_circbuf_t *cb,
ia_css_circbuf_elem_t *elems,
ia_css_circbuf_desc_t *desc);
*
* @param cb The pointer to the circular buffer.
*/
-extern void ia_css_circbuf_destroy(
+void ia_css_circbuf_destroy(
ia_css_circbuf_t *cb);
/**
*
* @return the pop-out value.
*/
-extern uint32_t ia_css_circbuf_pop(
+uint32_t ia_css_circbuf_pop(
ia_css_circbuf_t *cb);
/**
*
* @return the extracted value.
*/
-extern uint32_t ia_css_circbuf_extract(
+uint32_t ia_css_circbuf_extract(
ia_css_circbuf_t *cb,
int offset);
ia_css_circbuf_elem_t *elem,
uint32_t val)
{
- OP___assert(elem != NULL);
+ OP___assert(elem);
elem->val = val;
}
static inline void ia_css_circbuf_elem_init(
ia_css_circbuf_elem_t *elem)
{
- OP___assert(elem != NULL);
+ OP___assert(elem);
ia_css_circbuf_elem_set_val(elem, 0);
}
ia_css_circbuf_elem_t *src,
ia_css_circbuf_elem_t *dest)
{
- OP___assert(src != NULL);
- OP___assert(dest != NULL);
+ OP___assert(src);
+ OP___assert(dest);
ia_css_circbuf_elem_set_val(dest, src->val);
}
*/
static inline uint8_t ia_css_circbuf_get_pos_at_offset(
ia_css_circbuf_t *cb,
- uint32_t base,
+ u32 base,
int offset)
{
- uint8_t dest;
+ u8 dest;
- OP___assert(cb != NULL);
- OP___assert(cb->desc != NULL);
+ OP___assert(cb);
+ OP___assert(cb->desc);
OP___assert(cb->desc->size > 0);
/* step 1: adjudst the offset */
*/
static inline int ia_css_circbuf_get_offset(
ia_css_circbuf_t *cb,
- uint32_t src_pos,
+ u32 src_pos,
uint32_t dest_pos)
{
int offset;
- OP___assert(cb != NULL);
- OP___assert(cb->desc != NULL);
+ OP___assert(cb);
+ OP___assert(cb->desc);
offset = (int)(dest_pos - src_pos);
offset += (offset < 0) ? cb->desc->size : 0;
static inline uint32_t ia_css_circbuf_get_size(
ia_css_circbuf_t *cb)
{
- OP___assert(cb != NULL);
- OP___assert(cb->desc != NULL);
+ OP___assert(cb);
+ OP___assert(cb->desc);
return cb->desc->size;
}
{
int num;
- OP___assert(cb != NULL);
- OP___assert(cb->desc != NULL);
+ OP___assert(cb);
+ OP___assert(cb->desc);
num = ia_css_circbuf_get_offset(cb, cb->desc->start, cb->desc->end);
static inline bool ia_css_circbuf_is_empty(
ia_css_circbuf_t *cb)
{
- OP___assert(cb != NULL);
- OP___assert(cb->desc != NULL);
+ OP___assert(cb);
+ OP___assert(cb->desc);
return ia_css_circbuf_desc_is_empty(cb->desc);
}
*/
static inline bool ia_css_circbuf_is_full(ia_css_circbuf_t *cb)
{
- OP___assert(cb != NULL);
- OP___assert(cb->desc != NULL);
+ OP___assert(cb);
+ OP___assert(cb->desc);
return ia_css_circbuf_desc_is_full(cb->desc);
}
ia_css_circbuf_t *cb,
ia_css_circbuf_elem_t elem)
{
- OP___assert(cb != NULL);
- OP___assert(cb->desc != NULL);
+ OP___assert(cb);
+ OP___assert(cb->desc);
/* Cannot continue as the queue is full*/
assert(!ia_css_circbuf_is_full(cb));
{
ia_css_circbuf_elem_t elem;
- OP___assert(cb != NULL);
+ OP___assert(cb);
/* set up an element */
ia_css_circbuf_elem_init(&elem);
static inline uint32_t ia_css_circbuf_get_free_elems(
ia_css_circbuf_t *cb)
{
- OP___assert(cb != NULL);
- OP___assert(cb->desc != NULL);
+ OP___assert(cb);
+ OP___assert(cb->desc);
return ia_css_circbuf_desc_get_free_elems(cb->desc);
}
*
* @return the elements value.
*/
-extern uint32_t ia_css_circbuf_peek(
+uint32_t ia_css_circbuf_peek(
ia_css_circbuf_t *cb,
int offset);
*
* @return the elements value.
*/
-extern uint32_t ia_css_circbuf_peek_from_start(
+uint32_t ia_css_circbuf_peek_from_start(
ia_css_circbuf_t *cb,
int offset);
* @param sz_delta delta increase for new size
* @param elems (optional) pointers to new additional elements
* cb element array size will not be increased dynamically,
- * but new elements should be added at the end to existing
- * cb element array which if of max_size >= new size
+ * but new elements should be added at the end to existing
+ * cb element array which if of max_size >= new size
*
* @return true on successfully increasing the size
- * false on failure
+ * false on failure
*/
-extern bool ia_css_circbuf_increase_size(
+bool ia_css_circbuf_increase_size(
ia_css_circbuf_t *cb,
unsigned int sz_delta,
ia_css_circbuf_elem_t *elems);
*/
typedef struct ia_css_circbuf_desc_s ia_css_circbuf_desc_t;
struct ia_css_circbuf_desc_s {
- uint8_t size; /* the maximum number of elements*/
- uint8_t step; /* number of bytes per element */
- uint8_t start; /* index of the oldest element */
- uint8_t end; /* index at which to write the new element */
+ u8 size; /* the maximum number of elements*/
+ u8 step; /* number of bytes per element */
+ u8 start; /* index of the oldest element */
+ u8 end; /* index at which to write the new element */
};
+
#define SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT \
(4 * sizeof(uint8_t))
*/
typedef struct ia_css_circbuf_elem_s ia_css_circbuf_elem_t;
struct ia_css_circbuf_elem_s {
- uint32_t val; /* the value stored in the element */
+ u32 val; /* the value stored in the element */
};
+
#define SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT \
(sizeof(uint32_t))
static inline bool ia_css_circbuf_desc_is_empty(
ia_css_circbuf_desc_t *cb_desc)
{
- OP___assert(cb_desc != NULL);
+ OP___assert(cb_desc);
return (cb_desc->end == cb_desc->start);
}
static inline bool ia_css_circbuf_desc_is_full(
ia_css_circbuf_desc_t *cb_desc)
{
- OP___assert(cb_desc != NULL);
+ OP___assert(cb_desc);
return (OP_std_modadd(cb_desc->end, 1, cb_desc->size) == cb_desc->start);
}
ia_css_circbuf_desc_t *cb_desc,
int8_t size)
{
- OP___assert(cb_desc != NULL);
+ OP___assert(cb_desc);
cb_desc->size = size;
}
*/
static inline uint8_t ia_css_circbuf_desc_get_pos_at_offset(
ia_css_circbuf_desc_t *cb_desc,
- uint32_t base,
+ u32 base,
int offset)
{
- uint8_t dest;
- OP___assert(cb_desc != NULL);
+ u8 dest;
+
+ OP___assert(cb_desc);
OP___assert(cb_desc->size > 0);
/* step 1: adjust the offset */
*/
static inline int ia_css_circbuf_desc_get_offset(
ia_css_circbuf_desc_t *cb_desc,
- uint32_t src_pos,
+ u32 src_pos,
uint32_t dest_pos)
{
int offset;
- OP___assert(cb_desc != NULL);
+
+ OP___assert(cb_desc);
offset = (int)(dest_pos - src_pos);
offset += (offset < 0) ? cb_desc->size : 0;
ia_css_circbuf_desc_t *cb_desc)
{
int num;
- OP___assert(cb_desc != NULL);
+
+ OP___assert(cb_desc);
num = ia_css_circbuf_desc_get_offset(cb_desc,
cb_desc->start,
static inline uint32_t ia_css_circbuf_desc_get_free_elems(
ia_css_circbuf_desc_t *cb_desc)
{
- uint32_t num;
- OP___assert(cb_desc != NULL);
+ u32 num;
+
+ OP___assert(cb_desc);
num = ia_css_circbuf_desc_get_offset(cb_desc,
cb_desc->start,
* @param chunk_dest The position to which the first element in the chunk would be shift.
*/
static inline void ia_css_circbuf_shift_chunk(ia_css_circbuf_t *cb,
- uint32_t chunk_src,
+ u32 chunk_src,
uint32_t chunk_dest);
/*
ia_css_circbuf_elem_t *elems,
ia_css_circbuf_desc_t *desc)
{
- uint32_t i;
+ u32 i;
OP___assert(desc);
*/
uint32_t ia_css_circbuf_pop(ia_css_circbuf_t *cb)
{
- uint32_t ret;
+ u32 ret;
ia_css_circbuf_elem_t elem;
assert(!ia_css_circbuf_is_empty(cb));
uint32_t ia_css_circbuf_extract(ia_css_circbuf_t *cb, int offset)
{
int max_offset;
- uint32_t val;
- uint32_t pos;
- uint32_t src_pos;
- uint32_t dest_pos;
+ u32 val;
+ u32 pos;
+ u32 src_pos;
+ u32 dest_pos;
/* get the maximum offest */
max_offset = ia_css_circbuf_get_offset(cb, cb->desc->start, cb->desc->end);
unsigned int sz_delta,
ia_css_circbuf_elem_t *elems)
{
- uint8_t curr_size;
- uint8_t curr_end;
+ u8 curr_size;
+ u8 curr_end;
unsigned int i = 0;
if (!cb || sz_delta == 0)
*/
static inline void
ia_css_circbuf_shift_chunk(ia_css_circbuf_t *cb,
- uint32_t chunk_src, uint32_t chunk_dest)
+ u32 chunk_src, uint32_t chunk_dest)
{
int chunk_offset;
int chunk_sz;
/* shift each element to its terminal position */
for (i = 0; i < chunk_sz; i++) {
-
/* copy the element from the source to the destination */
ia_css_circbuf_elem_cpy(&cb->elems[chunk_src],
&cb->elems[chunk_dest]);
/* adjust the source/terminal positions */
chunk_src = ia_css_circbuf_get_pos_at_offset(cb, chunk_src, -1);
chunk_dest = ia_css_circbuf_get_pos_at_offset(cb, chunk_dest, -1);
-
}
/* adjust the index "start" */
cb->desc->start = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->start, chunk_offset);
}
-
* \param[in] size Size of the refcount list.
* \return ia_css_err
*/
-extern enum ia_css_err ia_css_refcount_init(uint32_t size);
+enum ia_css_err ia_css_refcount_init(uint32_t size);
/*! \brief Function for de-initializing refcount list
*
* \return None
*/
-extern void ia_css_refcount_uninit(void);
+void ia_css_refcount_uninit(void);
/*! \brief Function for increasing reference by 1.
*
* \param[in] ptr Data of the object (ptr).
* \return hrt_vaddress (saved address)
*/
-extern hrt_vaddress ia_css_refcount_increment(int32_t id, hrt_vaddress ptr);
+hrt_vaddress ia_css_refcount_increment(s32 id, hrt_vaddress ptr);
/*! \brief Function for decrease reference by 1.
*
* - true, if it is successful.
* - false, otherwise.
*/
-extern bool ia_css_refcount_decrement(int32_t id, hrt_vaddress ptr);
+bool ia_css_refcount_decrement(s32 id, hrt_vaddress ptr);
/*! \brief Function to check if reference count is 1.
*
* - true, if it is successful.
* - false, otherwise.
*/
-extern bool ia_css_refcount_is_single(hrt_vaddress ptr);
+bool ia_css_refcount_is_single(hrt_vaddress ptr);
/*! \brief Function to clear reference list objects.
*
*
* return None
*/
-extern void ia_css_refcount_clear(int32_t id,
+void ia_css_refcount_clear(s32 id,
clear_func clear_func_ptr);
/*! \brief Function to verify if object is valid
* - true, if valid
* - false, if invalid
*/
-extern bool ia_css_refcount_is_valid(hrt_vaddress ptr);
+bool ia_css_refcount_is_valid(hrt_vaddress ptr);
#endif /* _IA_CSS_REFCOUNT_H_ */
/* TODO: enable for other memory aswell
now only for hrt_vaddress */
struct ia_css_refcount_entry {
- uint32_t count;
+ u32 count;
hrt_vaddress data;
- int32_t id;
+ s32 id;
};
struct ia_css_refcount_list {
- uint32_t size;
+ u32 size;
struct ia_css_refcount_entry *items;
};
static struct ia_css_refcount_entry *refcount_find_entry(hrt_vaddress ptr,
bool firstfree)
{
- uint32_t i;
+ u32 i;
if (ptr == 0)
return NULL;
- if (myrefcount.items == NULL) {
+ if (!myrefcount.items) {
ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
"refcount_find_entry(): Ref count not initiliazed!\n");
return NULL;
}
for (i = 0; i < myrefcount.size; i++) {
-
if ((&myrefcount.items[i])->data == 0) {
if (firstfree) {
/* for new entry */
"ia_css_refcount_init(): Size of 0 for Ref count init!\n");
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
- if (myrefcount.items != NULL) {
+ if (myrefcount.items) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_init(): Ref count is already initialized\n");
return IA_CSS_ERR_INTERNAL_ERROR;
void ia_css_refcount_uninit(void)
{
struct ia_css_refcount_entry *entry;
- uint32_t i;
+ u32 i;
+
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_uninit() entry\n");
for (i = 0; i < myrefcount.size; i++) {
"ia_css_refcount_uninit() leave\n");
}
-hrt_vaddress ia_css_refcount_increment(int32_t id, hrt_vaddress ptr)
+hrt_vaddress ia_css_refcount_increment(s32 id, hrt_vaddress ptr)
{
struct ia_css_refcount_entry *entry;
if (!entry) {
entry = refcount_find_entry(ptr, true);
- assert(entry != NULL);
- if (entry == NULL)
+ assert(entry);
+ if (!entry)
return mmgr_NULL;
entry->id = id;
}
return ptr;
}
-bool ia_css_refcount_decrement(int32_t id, hrt_vaddress ptr)
+bool ia_css_refcount_decrement(s32 id, hrt_vaddress ptr)
{
struct ia_css_refcount_entry *entry;
return true;
}
-void ia_css_refcount_clear(int32_t id, clear_func clear_func_ptr)
+void ia_css_refcount_clear(s32 id, clear_func clear_func_ptr)
{
struct ia_css_refcount_entry *entry;
- uint32_t i;
- uint32_t count = 0;
+ u32 i;
+ u32 count = 0;
- assert(clear_func_ptr != NULL);
+ assert(clear_func_ptr);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_refcount_clear(%x)\n",
id);
entry = myrefcount.items + i;
if ((entry->data != mmgr_NULL) && (entry->id == id)) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
- "ia_css_refcount_clear:"
- " %x: 0x%x\n", id, entry->data);
+ "ia_css_refcount_clear: %x: 0x%x\n",
+ id, entry->data);
if (clear_func_ptr) {
/* clear using provided function */
clear_func_ptr(entry->data);
} else {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
- "ia_css_refcount_clear: "
- "using hmm_free: "
- "no clear_func\n");
+ "ia_css_refcount_clear: using hmm_free: no clear_func\n");
hmm_free(entry->data);
}
#ifndef ISP2401
entry = refcount_find_entry(ptr, false);
- return entry != NULL;
+ return entry;
}
-
* @return None
*
*/
-extern void ia_css_pipe_get_copy_binarydesc(
+void ia_css_pipe_get_copy_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *copy_descr,
struct ia_css_frame_info *in_info,
* @return None
*
*/
-extern void ia_css_pipe_get_vfpp_binarydesc(
+void ia_css_pipe_get_vfpp_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *vf_pp_descr,
struct ia_css_frame_info *in_info,
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
-extern enum ia_css_err sh_css_bds_factor_get_numerator_denominator(
+enum ia_css_err sh_css_bds_factor_get_numerator_denominator(
unsigned int bds_factor,
unsigned int *bds_factor_numerator,
unsigned int *bds_factor_denominator);
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
-extern enum ia_css_err ia_css_pipe_get_preview_binarydesc(
+enum ia_css_err ia_css_pipe_get_preview_binarydesc(
struct ia_css_pipe * const pipe,
struct ia_css_binary_descr *preview_descr,
struct ia_css_frame_info *in_info,
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
-extern enum ia_css_err ia_css_pipe_get_video_binarydesc(
+enum ia_css_err ia_css_pipe_get_video_binarydesc(
struct ia_css_pipe * const pipe,
struct ia_css_binary_descr *video_descr,
struct ia_css_frame_info *in_info,
* @return None
*
*/
-extern void ia_css_pipe_get_capturepp_binarydesc(
+void ia_css_pipe_get_capturepp_binarydesc(
struct ia_css_pipe * const pipe,
struct ia_css_binary_descr *capture_pp_descr,
struct ia_css_frame_info *in_info,
* @return None
*
*/
-extern void ia_css_pipe_get_primary_binarydesc(
+void ia_css_pipe_get_primary_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *prim_descr,
struct ia_css_frame_info *in_info,
* @return None
*
*/
-extern void ia_css_pipe_get_pre_gdc_binarydesc(
+void ia_css_pipe_get_pre_gdc_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *gdc_descr,
struct ia_css_frame_info *in_info,
* @return None
*
*/
-extern void ia_css_pipe_get_gdc_binarydesc(
+void ia_css_pipe_get_gdc_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *gdc_descr,
struct ia_css_frame_info *in_info,
* @return None
*
*/
-extern void ia_css_pipe_get_post_gdc_binarydesc(
+void ia_css_pipe_get_post_gdc_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *post_gdc_descr,
struct ia_css_frame_info *in_info,
* @return None
*
*/
-extern void ia_css_pipe_get_pre_de_binarydesc(
+void ia_css_pipe_get_pre_de_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *pre_de_descr,
struct ia_css_frame_info *in_info,
* @return None
*
*/
-extern void ia_css_pipe_get_pre_anr_binarydesc(
+void ia_css_pipe_get_pre_anr_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *pre_anr_descr,
struct ia_css_frame_info *in_info,
* @return None
*
*/
-extern void ia_css_pipe_get_anr_binarydesc(
+void ia_css_pipe_get_anr_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *anr_descr,
struct ia_css_frame_info *in_info,
* @return None
*
*/
-extern void ia_css_pipe_get_post_anr_binarydesc(
+void ia_css_pipe_get_post_anr_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *post_anr_descr,
struct ia_css_frame_info *in_info,
* @return None
*
*/
-extern void ia_css_pipe_get_ldc_binarydesc(
+void ia_css_pipe_get_ldc_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *ldc_descr,
struct ia_css_frame_info *in_info,
#include "ia_css_pipeline.h"
#include "ia_css_pipeline_common.h"
-extern void ia_css_pipe_get_generic_stage_desc(
+void ia_css_pipe_get_generic_stage_desc(
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_binary *binary,
struct ia_css_frame *out_frame[],
struct ia_css_frame *in_frame,
struct ia_css_frame *vf_frame);
-extern void ia_css_pipe_get_firmwares_stage_desc(
+void ia_css_pipe_get_firmwares_stage_desc(
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_binary *binary,
struct ia_css_frame *out_frame[],
const struct ia_css_fw_info *fw,
unsigned int mode);
-extern void ia_css_pipe_get_acc_stage_desc(
+void ia_css_pipe_get_acc_stage_desc(
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_binary *binary,
struct ia_css_fw_info *fw);
-extern void ia_css_pipe_get_sp_func_stage_desc(
+void ia_css_pipe_get_sp_func_stage_desc(
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_frame *out_frame,
enum ia_css_pipeline_stage_sp_func sp_func,
- unsigned max_input_width);
+ unsigned int max_input_width);
#endif /*__IA_CSS_PIPE_STAGEDESC__H__ */
-
* @return bits per pixel for the underlying stream
*
*/
-extern unsigned int ia_css_pipe_util_pipe_input_format_bpp(
+unsigned int ia_css_pipe_util_pipe_input_format_bpp(
const struct ia_css_pipe * const pipe);
-extern void ia_css_pipe_util_create_output_frames(
+void ia_css_pipe_util_create_output_frames(
struct ia_css_frame *frames[]);
-extern void ia_css_pipe_util_set_output_frames(
+void ia_css_pipe_util_set_output_frames(
struct ia_css_frame *frames[],
unsigned int idx,
struct ia_css_frame *frame);
{
unsigned int i;
/* in_info, out_info, vf_info can be NULL */
- assert(pipe != NULL);
- assert(descr != NULL);
+ assert(pipe);
+ assert(descr);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"pipe_binarydesc_get_offline() enter:\n");
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
unsigned int i;
/* out_info can be NULL */
- assert(pipe != NULL);
- assert(in_info != NULL);
+ assert(pipe);
+ assert(in_info);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
copy_descr->isp_pipe_version = IA_CSS_PIPE_VERSION_1;
IA_CSS_LEAVE_PRIVATE("");
}
+
void ia_css_pipe_get_vfpp_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *vf_pp_descr,
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
unsigned int i;
/* out_info can be NULL ??? */
- assert(pipe != NULL);
- assert(in_info != NULL);
+ assert(pipe);
+ assert(in_info);
IA_CSS_ENTER_PRIVATE("");
in_info->raw_bit_depth = 0;
/* Loop over all bds factors until a match is found */
for (i = 0; i < ARRAY_SIZE(bds_factors_list); i++) {
- unsigned num = bds_factors_list[i].numerator;
- unsigned den = bds_factors_list[i].denominator;
+ unsigned int num = bds_factors_list[i].numerator;
+ unsigned int den = bds_factors_list[i].denominator;
/* See width-wise and height-wise if this bds_factor
* satisfies the condition */
int mode = IA_CSS_BINARY_MODE_PREVIEW;
unsigned int i;
- assert(pipe != NULL);
- assert(in_info != NULL);
- assert(out_info != NULL);
- assert(vf_info != NULL);
+ assert(pipe);
+ assert(in_info);
+ assert(out_info);
+ assert(vf_info);
IA_CSS_ENTER_PRIVATE("");
/*
bool stream_dz_config = false;
/* vf_info can be NULL */
- assert(pipe != NULL);
- assert(in_info != NULL);
+ assert(pipe);
+ assert(in_info);
/* assert(vf_info != NULL); */
IA_CSS_ENTER_PRIVATE("");
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
struct ia_css_frame_info *this_vf_info = NULL;
- assert(pipe != NULL);
- assert(in_info != NULL);
+ assert(pipe);
+ assert(in_info);
/* Note: if the following assert fails, the number of ports has been
* changed; in that case an additional initializer must be added
* a few lines below after which this assert can be updated.
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
- assert(pipe != NULL);
- assert(in_info != NULL);
- assert(vf_info != NULL);
+ assert(pipe);
+ assert(in_info);
+ assert(vf_info);
IA_CSS_ENTER_PRIVATE("");
-
/* the in_info is only used for resolution to enable
bayer down scaling. */
if (pipe->out_yuv_ds_input_info.res.width)
}
/* lookup table for high quality primary binaries */
-static unsigned int primary_hq_binary_modes[NUM_PRIMARY_HQ_STAGES] =
-{
+static unsigned int primary_hq_binary_modes[NUM_PRIMARY_HQ_STAGES] = {
IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE0,
IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE1,
IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE2,
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
- assert(pipe != NULL);
- assert(in_info != NULL);
- assert(out_info != NULL);
+ assert(pipe);
+ assert(in_info);
+ assert(out_info);
assert(stage_idx < NUM_PRIMARY_HQ_STAGES);
/* vf_info can be NULL - example video_binarydescr */
/*assert(vf_info != NULL);*/
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
- assert(pipe != NULL);
- assert(in_info != NULL);
- assert(out_info != NULL);
+ assert(pipe);
+ assert(in_info);
+ assert(out_info);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
- assert(pipe != NULL);
- assert(in_info != NULL);
- assert(out_info != NULL);
+ assert(pipe);
+ assert(in_info);
+ assert(out_info);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
- assert(pipe != NULL);
- assert(in_info != NULL);
- assert(out_info != NULL);
- assert(vf_info != NULL);
+ assert(pipe);
+ assert(in_info);
+ assert(out_info);
+ assert(vf_info);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
- assert(pipe != NULL);
- assert(in_info != NULL);
- assert(out_info != NULL);
+ assert(pipe);
+ assert(in_info);
+ assert(out_info);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
- assert(pipe != NULL);
- assert(in_info != NULL);
- assert(out_info != NULL);
+ assert(pipe);
+ assert(in_info);
+ assert(out_info);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
- assert(pipe != NULL);
- assert(in_info != NULL);
- assert(out_info != NULL);
+ assert(pipe);
+ assert(in_info);
+ assert(out_info);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
IA_CSS_LEAVE_PRIVATE("");
}
-
void ia_css_pipe_get_post_anr_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *post_anr_descr,
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
- assert(pipe != NULL);
- assert(in_info != NULL);
- assert(out_info != NULL);
- assert(vf_info != NULL);
+ assert(pipe);
+ assert(in_info);
+ assert(out_info);
+ assert(vf_info);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
- assert(pipe != NULL);
- assert(in_info != NULL);
- assert(out_info != NULL);
+ assert(pipe);
+ assert(in_info);
+ assert(out_info);
IA_CSS_ENTER_PRIVATE("");
#ifndef ISP2401
struct ia_css_frame *vf_frame)
{
unsigned int i;
+
IA_CSS_ENTER_PRIVATE("stage_desc = %p, binary = %p, out_frame = %p, in_frame = %p, vf_frame = %p",
stage_desc, binary, out_frame, in_frame, vf_frame);
- assert(stage_desc != NULL && binary != NULL && binary->info != NULL);
- if (stage_desc == NULL || binary == NULL || binary->info == NULL) {
+ assert(stage_desc && binary && binary->info);
+ if (!stage_desc || !binary || !binary->info) {
IA_CSS_ERROR("invalid arguments");
goto ERR;
}
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_frame *out_frame,
enum ia_css_pipeline_stage_sp_func sp_func,
- unsigned max_input_width)
+ unsigned int max_input_width)
{
unsigned int i;
}
stage_desc->vf_frame = NULL;
}
-
unsigned int ia_css_pipe_util_pipe_input_format_bpp(
const struct ia_css_pipe * const pipe)
{
- assert(pipe != NULL);
- assert(pipe->stream != NULL);
+ assert(pipe);
+ assert(pipe->stream);
return ia_css_util_input_format_bpp(pipe->stream->config.input_config.format,
pipe->stream->config.pixels_per_clock == 2);
{
unsigned int i;
- assert(frames != NULL);
+ assert(frames);
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
frames[i] = NULL;
}
frames[idx] = frame;
}
-
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
-extern enum ia_css_err ia_css_util_check_vf_info(
+enum ia_css_err ia_css_util_check_vf_info(
const struct ia_css_frame_info * const info);
/* @brief check input configuration.
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
-extern enum ia_css_err ia_css_util_check_input(
+enum ia_css_err ia_css_util_check_input(
const struct ia_css_stream_config * const stream_config,
bool must_be_raw,
bool must_be_yuv);
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
-extern enum ia_css_err ia_css_util_check_vf_out_info(
+enum ia_css_err ia_css_util_check_vf_out_info(
const struct ia_css_frame_info * const out_info,
const struct ia_css_frame_info * const vf_info);
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
-extern enum ia_css_err ia_css_util_check_res(
+enum ia_css_err ia_css_util_check_res(
unsigned int width,
unsigned int height);
* equal than those of b, false otherwise
*
*/
-extern bool ia_css_util_res_leq(
+bool ia_css_util_res_leq(
struct ia_css_resolution a,
struct ia_css_resolution b);
*
* @returns true if resolution is zero
*/
-extern bool ia_css_util_resolution_is_zero(
+bool ia_css_util_resolution_is_zero(
const struct ia_css_resolution resolution);
/**
*
* @returns true if resolution is even
*/
-extern bool ia_css_util_resolution_is_even(
+bool ia_css_util_resolution_is_even(
const struct ia_css_resolution resolution);
#endif
* @return bits per pixel based on given parameters.
*
*/
-extern unsigned int ia_css_util_input_format_bpp(
+unsigned int ia_css_util_input_format_bpp(
enum atomisp_input_format stream_format,
bool two_ppc);
* @return true if the input format is raw or false otherwise
*
*/
-extern bool ia_css_util_is_input_format_raw(
+bool ia_css_util_is_input_format_raw(
enum atomisp_input_format stream_format);
/* @brief check if input format it yuv
* @return true if the input format is yuv or false otherwise
*
*/
-extern bool ia_css_util_is_input_format_yuv(
+bool ia_css_util_is_input_format_yuv(
enum atomisp_input_format stream_format);
#endif /* __IA_CSS_UTIL_H__ */
-
/* for ia_css_binary_max_vf_width() */
#include "ia_css_binary.h"
-
enum ia_css_err ia_css_convert_errno(
int in_err)
{
bool two_ppc)
{
unsigned int rval = 0;
+
switch (format) {
case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY:
case ATOMISP_INPUT_FORMAT_YUV420_8:
default:
rval = 0;
break;
-
}
return rval;
}
{
enum ia_css_err err;
unsigned int max_vf_width;
- assert(info != NULL);
+
+ assert(info);
err = ia_css_frame_check_info(info);
if (err != IA_CSS_SUCCESS)
return err;
max_vf_width = ia_css_binary_max_vf_width();
- if (max_vf_width != 0 && info->res.width > max_vf_width*2)
+ if (max_vf_width != 0 && info->res.width > max_vf_width * 2)
return IA_CSS_ERR_INVALID_ARGUMENTS;
return IA_CSS_SUCCESS;
}
{
enum ia_css_err err;
- assert(out_info != NULL);
- assert(vf_info != NULL);
+ assert(out_info);
+ assert(vf_info);
err = ia_css_frame_check_info(out_info);
if (err != IA_CSS_SUCCESS)
bool must_be_raw,
bool must_be_yuv)
{
- assert(stream_config != NULL);
+ assert(stream_config);
- if (stream_config == NULL)
+ if (!stream_config)
return IA_CSS_ERR_INVALID_ARGUMENTS;
#ifdef IS_ISP_2400_SYSTEM
return IA_CSS_SUCCESS;
}
-
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_iterator() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.iterator.size;
offset = binary->info->mem_offsets.offsets.config->dmem.iterator.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_copy_output() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.copy_output.size;
offset = binary->info->mem_offsets.offsets.config->dmem.copy_output.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_crop() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.crop.size;
offset = binary->info->mem_offsets.offsets.config->dmem.crop.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_fpn() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.fpn.size;
offset = binary->info->mem_offsets.offsets.config->dmem.fpn.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_dvs() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.dvs.size;
offset = binary->info->mem_offsets.offsets.config->dmem.dvs.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_qplane() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.qplane.size;
offset = binary->info->mem_offsets.offsets.config->dmem.qplane.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output0() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output0.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output0.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output1() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output1.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output1.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_sc() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.sc.size;
offset = binary->info->mem_offsets.offsets.config->dmem.sc.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_raw() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.raw.size;
offset = binary->info->mem_offsets.offsets.config->dmem.raw.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_tnr() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.tnr.size;
offset = binary->info->mem_offsets.offsets.config->dmem.tnr.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_ref() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.ref.size;
offset = binary->info->mem_offsets.offsets.config->dmem.ref.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.vf.size;
offset = binary->info->mem_offsets.offsets.config->dmem.vf.offset;
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() leave:\n");
}
-
static void
ia_css_process_aa(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.aa.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.aa.size;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset;
if (size) {
struct sh_css_isp_aa_params *t = (struct sh_css_isp_aa_params *)
static void
ia_css_process_anr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.anr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.anr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr() leave:\n");
}
-
}
}
static void
ia_css_process_anr2(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr2() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr2() leave:\n");
}
-
}
}
static void
ia_css_process_bh(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bh.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.bh.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bh.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.bh.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() leave:\n");
}
-
}
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->hmem0.bh.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->hmem0.bh.size;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() leave:\n");
}
-
}
}
static void
ia_css_process_cnr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_cnr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_cnr() leave:\n");
}
-
}
}
static void
ia_css_process_crop(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.crop.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.crop.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.crop.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.crop.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_crop() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_crop() leave:\n");
}
-
}
}
static void
ia_css_process_csc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.csc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.csc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.csc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.csc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_csc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_csc() leave:\n");
}
-
}
}
static void
ia_css_process_dp(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.dp.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.dp.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.dp.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.dp.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_dp() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_dp() leave:\n");
}
-
}
}
static void
ia_css_process_bnr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bnr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bnr() leave:\n");
}
-
}
}
static void
ia_css_process_de(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.de.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.de.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.de.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.de.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_de() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_de() leave:\n");
}
-
}
}
static void
ia_css_process_ecd(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ecd() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ecd() leave:\n");
}
-
}
}
static void
ia_css_process_formats(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.formats.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.formats.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.formats.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.formats.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_formats() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_formats() leave:\n");
}
-
}
}
static void
ia_css_process_fpn(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fpn() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fpn() leave:\n");
}
-
}
}
static void
ia_css_process_gc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.gc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.gc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.gc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.gc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() leave:\n");
}
-
}
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() leave:\n");
}
-
}
}
static void
ia_css_process_ce(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ce.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.ce.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ce.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.ce.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ce() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ce() leave:\n");
}
-
}
}
static void
ia_css_process_yuv2rgb(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yuv2rgb() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yuv2rgb() leave:\n");
}
-
}
}
static void
ia_css_process_rgb2yuv(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_rgb2yuv() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_rgb2yuv() leave:\n");
}
-
}
}
static void
ia_css_process_r_gamma(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_r_gamma() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_r_gamma() leave:\n");
}
-
}
}
static void
ia_css_process_g_gamma(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_g_gamma() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_g_gamma() leave:\n");
}
-
}
}
static void
ia_css_process_b_gamma(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_b_gamma() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_b_gamma() leave:\n");
}
-
}
}
static void
ia_css_process_uds(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.uds.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.uds.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.uds.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.uds.offset;
if (size) {
struct sh_css_sp_uds_params *p;
+
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_uds() enter:\n");
p = (struct sh_css_sp_uds_params *)
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_uds() leave:\n");
}
-
}
}
static void
ia_css_process_raa(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.raa.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.raa.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.raa.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.raa.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_raa() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_raa() leave:\n");
}
-
}
}
static void
ia_css_process_s3a(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_s3a() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_s3a() leave:\n");
}
-
}
}
static void
ia_css_process_ob(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ob.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.ob.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ob.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.ob.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() leave:\n");
}
-
}
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.ob.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.ob.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.ob.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.ob.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() leave:\n");
}
-
}
}
static void
ia_css_process_output(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.output.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.output.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.output.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.output.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_output() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_output() leave:\n");
}
-
}
}
static void
ia_css_process_sc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.sc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.sc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sc() leave:\n");
}
-
}
}
static void
ia_css_process_bds(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bds.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.bds.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bds.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.bds.offset;
if (size) {
struct sh_css_isp_bds_params *p;
+
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bds() enter:\n");
p = (struct sh_css_isp_bds_params *)
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bds() leave:\n");
}
-
}
}
static void
ia_css_process_tnr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_tnr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_tnr() leave:\n");
}
-
}
}
static void
ia_css_process_macc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.macc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.macc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.macc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.macc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_macc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_macc() leave:\n");
}
-
}
}
static void
ia_css_process_sdis_horicoef(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horicoef() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horicoef() leave:\n");
}
-
}
}
static void
ia_css_process_sdis_vertcoef(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertcoef() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertcoef() leave:\n");
}
-
}
}
static void
ia_css_process_sdis_horiproj(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horiproj() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horiproj() leave:\n");
}
-
}
}
static void
ia_css_process_sdis_vertproj(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertproj() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertproj() leave:\n");
}
-
}
}
static void
ia_css_process_sdis2_horicoef(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horicoef() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horicoef() leave:\n");
}
-
}
}
static void
ia_css_process_sdis2_vertcoef(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertcoef() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertcoef() leave:\n");
}
-
}
}
static void
ia_css_process_sdis2_horiproj(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horiproj() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horiproj() leave:\n");
}
-
}
}
static void
ia_css_process_sdis2_vertproj(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertproj() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertproj() leave:\n");
}
-
}
}
static void
ia_css_process_wb(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.wb.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.wb.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.wb.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.wb.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_wb() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_wb() leave:\n");
}
-
}
}
static void
ia_css_process_nr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.nr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.nr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.nr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.nr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_nr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_nr() leave:\n");
}
-
}
}
static void
ia_css_process_yee(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.yee.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.yee.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.yee.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.yee.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yee() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yee() leave:\n");
}
-
}
}
static void
ia_css_process_ynr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ynr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ynr() leave:\n");
}
-
}
}
static void
ia_css_process_fc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.fc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.fc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.fc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.fc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fc() leave:\n");
}
-
}
}
static void
ia_css_process_ctc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() leave:\n");
}
-
}
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() leave:\n");
}
-
}
}
static void
ia_css_process_xnr_table(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr_table() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr_table() leave:\n");
}
-
}
}
static void
ia_css_process_xnr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr() leave:\n");
}
-
}
}
static void
ia_css_process_xnr3(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() leave:\n");
}
-
}
#ifdef ISP2401
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() leave:\n");
}
-
}
#endif
}
/* Code generated by genparam/gencode.c:gen_param_process_table() */
-void (* ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
- unsigned pipe_id,
+void (*ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params) = {
ia_css_process_aa,
static void
ia_css_get_dp_config(const struct ia_css_isp_parameters *params,
struct ia_css_dp_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_dp_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_dp_config() enter: config=%p\n",
+ config);
*config = params->dp_config;
ia_css_set_dp_config(struct ia_css_isp_parameters *params,
const struct ia_css_dp_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_dp_config() enter:\n");
ia_css_dp_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dp_config = *config;
params->config_changed[IA_CSS_DP_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_dp_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_dp_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_wb_config(const struct ia_css_isp_parameters *params,
struct ia_css_wb_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_wb_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_wb_config() enter: config=%p\n",
+ config);
*config = params->wb_config;
ia_css_set_wb_config(struct ia_css_isp_parameters *params,
const struct ia_css_wb_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_wb_config() enter:\n");
ia_css_wb_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->wb_config = *config;
params->config_changed[IA_CSS_WB_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_wb_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_wb_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_tnr_config(const struct ia_css_isp_parameters *params,
struct ia_css_tnr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_tnr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_tnr_config() enter: config=%p\n",
+ config);
*config = params->tnr_config;
ia_css_set_tnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_tnr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_tnr_config() enter:\n");
ia_css_tnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->tnr_config = *config;
params->config_changed[IA_CSS_TNR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_tnr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_tnr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_ob_config(const struct ia_css_isp_parameters *params,
struct ia_css_ob_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ob_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ob_config() enter: config=%p\n",
+ config);
*config = params->ob_config;
ia_css_set_ob_config(struct ia_css_isp_parameters *params,
const struct ia_css_ob_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ob_config() enter:\n");
ia_css_ob_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->ob_config = *config;
params->config_changed[IA_CSS_OB_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ob_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ob_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_de_config(const struct ia_css_isp_parameters *params,
struct ia_css_de_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_de_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_de_config() enter: config=%p\n",
+ config);
*config = params->de_config;
ia_css_set_de_config(struct ia_css_isp_parameters *params,
const struct ia_css_de_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_de_config() enter:\n");
ia_css_de_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->de_config = *config;
params->config_changed[IA_CSS_DE_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_de_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_de_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_anr_config(const struct ia_css_isp_parameters *params,
struct ia_css_anr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr_config() enter: config=%p\n",
+ config);
*config = params->anr_config;
ia_css_set_anr_config(struct ia_css_isp_parameters *params,
const struct ia_css_anr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_anr_config() enter:\n");
ia_css_anr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->anr_config = *config;
params->config_changed[IA_CSS_ANR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_anr2_config(const struct ia_css_isp_parameters *params,
struct ia_css_anr_thres *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr2_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr2_config() enter: config=%p\n",
+ config);
*config = params->anr_thres;
ia_css_set_anr2_config(struct ia_css_isp_parameters *params,
const struct ia_css_anr_thres *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_anr2_config() enter:\n");
ia_css_anr2_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->anr_thres = *config;
params->config_changed[IA_CSS_ANR2_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr2_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr2_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_ce_config(const struct ia_css_isp_parameters *params,
struct ia_css_ce_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ce_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ce_config() enter: config=%p\n",
+ config);
*config = params->ce_config;
ia_css_set_ce_config(struct ia_css_isp_parameters *params,
const struct ia_css_ce_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ce_config() enter:\n");
ia_css_ce_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->ce_config = *config;
params->config_changed[IA_CSS_CE_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ce_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ce_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_ecd_config(const struct ia_css_isp_parameters *params,
struct ia_css_ecd_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ecd_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ecd_config() enter: config=%p\n",
+ config);
*config = params->ecd_config;
ia_css_set_ecd_config(struct ia_css_isp_parameters *params,
const struct ia_css_ecd_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ecd_config() enter:\n");
ia_css_ecd_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->ecd_config = *config;
params->config_changed[IA_CSS_ECD_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ecd_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ecd_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_ynr_config(const struct ia_css_isp_parameters *params,
struct ia_css_ynr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ynr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ynr_config() enter: config=%p\n",
+ config);
*config = params->ynr_config;
ia_css_set_ynr_config(struct ia_css_isp_parameters *params,
const struct ia_css_ynr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ynr_config() enter:\n");
ia_css_ynr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->ynr_config = *config;
params->config_changed[IA_CSS_YNR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ynr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ynr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_fc_config(const struct ia_css_isp_parameters *params,
struct ia_css_fc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_fc_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_fc_config() enter: config=%p\n",
+ config);
*config = params->fc_config;
ia_css_set_fc_config(struct ia_css_isp_parameters *params,
const struct ia_css_fc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_fc_config() enter:\n");
ia_css_fc_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->fc_config = *config;
params->config_changed[IA_CSS_FC_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_fc_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_fc_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_cnr_config(const struct ia_css_isp_parameters *params,
struct ia_css_cnr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_cnr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_cnr_config() enter: config=%p\n",
+ config);
*config = params->cnr_config;
ia_css_set_cnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_cnr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_cnr_config() enter:\n");
ia_css_cnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->cnr_config = *config;
params->config_changed[IA_CSS_CNR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_cnr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_cnr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_macc_config(const struct ia_css_isp_parameters *params,
struct ia_css_macc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_macc_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_macc_config() enter: config=%p\n",
+ config);
*config = params->macc_config;
ia_css_set_macc_config(struct ia_css_isp_parameters *params,
const struct ia_css_macc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_macc_config() enter:\n");
ia_css_macc_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->macc_config = *config;
params->config_changed[IA_CSS_MACC_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_macc_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_macc_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_ctc_config(const struct ia_css_isp_parameters *params,
struct ia_css_ctc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ctc_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ctc_config() enter: config=%p\n",
+ config);
*config = params->ctc_config;
ia_css_set_ctc_config(struct ia_css_isp_parameters *params,
const struct ia_css_ctc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ctc_config() enter:\n");
ia_css_ctc_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->ctc_config = *config;
params->config_changed[IA_CSS_CTC_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ctc_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ctc_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_aa_config(const struct ia_css_isp_parameters *params,
struct ia_css_aa_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_aa_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_aa_config() enter: config=%p\n",
+ config);
*config = params->aa_config;
ia_css_set_aa_config(struct ia_css_isp_parameters *params,
const struct ia_css_aa_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_aa_config() enter:\n");
params->aa_config = *config;
params->config_changed[IA_CSS_AA_ID] = true;
params->config_changed[IA_CSS_AA_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_aa_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_aa_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_yuv2rgb_config(const struct ia_css_isp_parameters *params,
struct ia_css_cc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_yuv2rgb_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_yuv2rgb_config() enter: config=%p\n",
+ config);
*config = params->yuv2rgb_cc_config;
ia_css_set_yuv2rgb_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_yuv2rgb_config() enter:\n");
ia_css_yuv2rgb_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->yuv2rgb_cc_config = *config;
params->config_changed[IA_CSS_YUV2RGB_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_yuv2rgb_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_yuv2rgb_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_rgb2yuv_config(const struct ia_css_isp_parameters *params,
struct ia_css_cc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_rgb2yuv_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_rgb2yuv_config() enter: config=%p\n",
+ config);
*config = params->rgb2yuv_cc_config;
ia_css_set_rgb2yuv_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_rgb2yuv_config() enter:\n");
ia_css_rgb2yuv_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->rgb2yuv_cc_config = *config;
params->config_changed[IA_CSS_RGB2YUV_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_rgb2yuv_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_rgb2yuv_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_csc_config(const struct ia_css_isp_parameters *params,
struct ia_css_cc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_csc_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_csc_config() enter: config=%p\n",
+ config);
*config = params->cc_config;
ia_css_set_csc_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_csc_config() enter:\n");
ia_css_csc_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->cc_config = *config;
params->config_changed[IA_CSS_CSC_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_csc_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_csc_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_nr_config(const struct ia_css_isp_parameters *params,
struct ia_css_nr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_nr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_nr_config() enter: config=%p\n",
+ config);
*config = params->nr_config;
ia_css_set_nr_config(struct ia_css_isp_parameters *params,
const struct ia_css_nr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_nr_config() enter:\n");
ia_css_nr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->nr_config = *config;
params->config_changed[IA_CSS_NR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_nr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_nr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_gc_config(const struct ia_css_isp_parameters *params,
struct ia_css_gc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_gc_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_gc_config() enter: config=%p\n",
+ config);
*config = params->gc_config;
ia_css_set_gc_config(struct ia_css_isp_parameters *params,
const struct ia_css_gc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_gc_config() enter:\n");
ia_css_gc_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->gc_config = *config;
params->config_changed[IA_CSS_GC_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_gc_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_gc_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis_horicoef_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horicoef_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horicoef_config() enter: config=%p\n",
+ config);
*config = params->dvs_coefs;
ia_css_set_sdis_horicoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_horicoef_config() enter:\n");
ia_css_sdis_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs_coefs = *config;
params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horicoef_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horicoef_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis_vertcoef_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertcoef_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertcoef_config() enter: config=%p\n",
+ config);
*config = params->dvs_coefs;
ia_css_set_sdis_vertcoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_vertcoef_config() enter:\n");
ia_css_sdis_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs_coefs = *config;
params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertcoef_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertcoef_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis_horiproj_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horiproj_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horiproj_config() enter: config=%p\n",
+ config);
*config = params->dvs_coefs;
ia_css_set_sdis_horiproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_horiproj_config() enter:\n");
ia_css_sdis_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs_coefs = *config;
params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horiproj_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horiproj_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis_vertproj_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertproj_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertproj_config() enter: config=%p\n",
+ config);
*config = params->dvs_coefs;
ia_css_set_sdis_vertproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_vertproj_config() enter:\n");
ia_css_sdis_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs_coefs = *config;
params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertproj_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertproj_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis2_horicoef_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs2_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horicoef_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horicoef_config() enter: config=%p\n",
+ config);
*config = params->dvs2_coefs;
ia_css_set_sdis2_horicoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_horicoef_config() enter:\n");
ia_css_sdis2_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs2_coefs = *config;
params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horicoef_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horicoef_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis2_vertcoef_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs2_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertcoef_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertcoef_config() enter: config=%p\n",
+ config);
*config = params->dvs2_coefs;
ia_css_set_sdis2_vertcoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_vertcoef_config() enter:\n");
ia_css_sdis2_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs2_coefs = *config;
params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertcoef_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertcoef_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis2_horiproj_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs2_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horiproj_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horiproj_config() enter: config=%p\n",
+ config);
*config = params->dvs2_coefs;
ia_css_set_sdis2_horiproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_horiproj_config() enter:\n");
ia_css_sdis2_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs2_coefs = *config;
params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horiproj_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horiproj_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis2_vertproj_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs2_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertproj_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertproj_config() enter: config=%p\n",
+ config);
*config = params->dvs2_coefs;
ia_css_set_sdis2_vertproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_vertproj_config() enter:\n");
ia_css_sdis2_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs2_coefs = *config;
params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertproj_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertproj_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_r_gamma_config(const struct ia_css_isp_parameters *params,
struct ia_css_rgb_gamma_table *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_r_gamma_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_r_gamma_config() enter: config=%p\n",
+ config);
*config = params->r_gamma_table;
ia_css_set_r_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_r_gamma_config() enter:\n");
ia_css_r_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->r_gamma_table = *config;
params->config_changed[IA_CSS_R_GAMMA_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_r_gamma_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_r_gamma_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_g_gamma_config(const struct ia_css_isp_parameters *params,
struct ia_css_rgb_gamma_table *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_g_gamma_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_g_gamma_config() enter: config=%p\n",
+ config);
*config = params->g_gamma_table;
ia_css_set_g_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_g_gamma_config() enter:\n");
ia_css_g_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->g_gamma_table = *config;
params->config_changed[IA_CSS_G_GAMMA_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_g_gamma_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_g_gamma_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_b_gamma_config(const struct ia_css_isp_parameters *params,
struct ia_css_rgb_gamma_table *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_b_gamma_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_b_gamma_config() enter: config=%p\n",
+ config);
*config = params->b_gamma_table;
ia_css_set_b_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_b_gamma_config() enter:\n");
ia_css_b_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->b_gamma_table = *config;
params->config_changed[IA_CSS_B_GAMMA_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_b_gamma_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_b_gamma_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_xnr_table_config(const struct ia_css_isp_parameters *params,
struct ia_css_xnr_table *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_table_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_table_config() enter: config=%p\n",
+ config);
*config = params->xnr_table;
ia_css_set_xnr_table_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr_table *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr_table_config() enter:\n");
ia_css_xnr_table_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->xnr_table = *config;
params->config_changed[IA_CSS_XNR_TABLE_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_table_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_table_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_formats_config(const struct ia_css_isp_parameters *params,
struct ia_css_formats_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_formats_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_formats_config() enter: config=%p\n",
+ config);
*config = params->formats_config;
ia_css_set_formats_config(struct ia_css_isp_parameters *params,
const struct ia_css_formats_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_formats_config() enter:\n");
ia_css_formats_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->formats_config = *config;
params->config_changed[IA_CSS_FORMATS_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_formats_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_formats_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_xnr_config(const struct ia_css_isp_parameters *params,
struct ia_css_xnr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_config() enter: config=%p\n",
+ config);
*config = params->xnr_config;
ia_css_set_xnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr_config() enter:\n");
ia_css_xnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->xnr_config = *config;
params->config_changed[IA_CSS_XNR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_xnr3_config(const struct ia_css_isp_parameters *params,
struct ia_css_xnr3_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr3_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr3_config() enter: config=%p\n",
+ config);
*config = params->xnr3_config;
ia_css_set_xnr3_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr3_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr3_config() enter:\n");
ia_css_xnr3_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->xnr3_config = *config;
params->config_changed[IA_CSS_XNR3_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr3_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr3_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_s3a_config(const struct ia_css_isp_parameters *params,
struct ia_css_3a_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_s3a_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_s3a_config() enter: config=%p\n",
+ config);
*config = params->s3a_config;
ia_css_set_s3a_config(struct ia_css_isp_parameters *params,
const struct ia_css_3a_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_s3a_config() enter:\n");
ia_css_s3a_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->s3a_config = *config;
params->config_changed[IA_CSS_S3A_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_s3a_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_s3a_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_output_config(const struct ia_css_isp_parameters *params,
struct ia_css_output_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_output_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_output_config() enter: config=%p\n",
+ config);
*config = params->output_config;
ia_css_set_output_config(struct ia_css_isp_parameters *params,
const struct ia_css_output_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_output_config() enter:\n");
ia_css_output_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->output_config = *config;
params->config_changed[IA_CSS_OUTPUT_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_output_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_output_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_global_access_function() */
ia_css_set_s3a_config(params, config->s3a_config);
ia_css_set_output_config(params, config->output_config);
}
-
struct ia_css_pipeline_stage; /* forward declaration */
-extern void (* ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
- unsigned pipe_id,
+extern void (*ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.aa.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.aa.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset;
if (size)
memset(&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], 0, size);
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.cnr.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset;
if (size) {
ia_css_init_cnr_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset;
if (size) {
ia_css_init_cnr2_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.dp.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.dp.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset;
if (size) {
ia_css_init_dp_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.de.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.de.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.de.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.de.offset;
if (size) {
ia_css_init_de_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->dmem.tnr.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->dmem.tnr.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->dmem.tnr.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->dmem.tnr.offset;
if (size) {
ia_css_init_tnr_state((struct sh_css_isp_tnr_dmem_state *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->dmem.ref.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->dmem.ref.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->dmem.ref.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->dmem.ref.offset;
if (size) {
ia_css_init_ref_state((struct sh_css_isp_ref_dmem_state *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.ynr.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.ynr.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.ynr.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.ynr.offset;
if (size) {
ia_css_init_ynr_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() leave:\n");
}
ia_css_initialize_ref_state,
ia_css_initialize_ynr_state,
};
-
#define _hrt_get_bit(w, b) \
(((w) >> (b)) & 1)
#define _hrt_set_bit(w, b, v) \
- (((w) & (~(1 << (b)))) | (((v)&1) << (b)))
+ (((w) & (~(1 << (b)))) | (((v) & 1) << (b)))
#define _hrt_set_lower_half(w, v) \
_hrt_set_bits(w, 0, 16, v)
#define _hrt_set_upper_half(w, v) \
#define SP_ICACHE_BLOCK_ADDRESS_BITS 11 /* 2048 lines capacity*/
#define SP_ICACHE_ADDRESS_BITS \
- (SP_ICACHE_TAG_BITS+SP_ICACHE_BLOCK_ADDRESS_BITS)
+ (SP_ICACHE_TAG_BITS + SP_ICACHE_BLOCK_ADDRESS_BITS)
-#define SP_PMEM_DEPTH (1<<SP_ICACHE_ADDRESS_BITS)
+#define SP_PMEM_DEPTH BIT(SP_ICACHE_ADDRESS_BITS)
#define SP_FIFO_0_DEPTH 0
#define SP_FIFO_1_DEPTH 0
#define SP_FIFO_6_DEPTH 0
#define SP_FIFO_7_DEPTH 0
-
#define SP_SLV_BUS_MAXBURSTSIZE 1
#endif /* _cell_params_h */
-
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH 2
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH 3
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH (_HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH)
-#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */
+#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */
/* Definition of data format ID at the interface CSS_receiver capture/acquisition units */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8_CSPS 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10_CSPS 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
/* used reserved mipi positions for these */
-#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46
-#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47
-#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37
-#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38
+#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46
+#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47
+#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37
+#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_WIDTH 6
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB444 2 // 32
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB565 3 // 34
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB666 4 // 35
-#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42
+#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW10 6 // 43
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW6 7 // 40
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW7 8 // 41
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18 28 // ?
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_2 29 // ? Option 2 for depacketiser
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_3 30 // ? Option 3 for depacketiser
-#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding
+#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding
/* definition for state machine of data FIFO for decode different type of data */
-#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1
+#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV420_10_REPEAT_PTN 5
#define _HRT_CSS_RECEIVER_2400_YUV420_8L_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV422_8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV422_10_REPEAT_PTN 5
-#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2
+#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB555_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB565_REPEAT_PTN 2
-#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9
+#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9
#define _HRT_CSS_RECEIVER_2400_RGB888_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW6_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW7_REPEAT_PTN 7
#define _HRT_CSS_RECEIVER_2400_RAW8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_RAW10_REPEAT_PTN 5
-#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3
+#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW14_REPEAT_PTN 7
#define _HRT_CSS_RECEIVER_2400_MAX_REPEAT_PTN _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_7_12 5
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_8_12 6
-
/* packet bit definition */
#define _HRT_CSS_RECEIVER_2400_PKT_SOP_IDX 32
#define _HRT_CSS_RECEIVER_2400_PKT_SOP_BITS 1
#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_IDX 0
#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_BITS 32
-
/*************************************************************************************************/
/* Custom Decoding */
/* These Custom Defs are defined based on design-time config in "csi_be_pixel_formatter.chdl" !! */
/*************************************************************************************************/
#define BE_CUST_EN_IDX 0 /* 2bits */
-#define BE_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */
-#define BE_CUST_EN_WIDTH 8
+#define BE_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */
+#define BE_CUST_EN_WIDTH 8
#define BE_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */
#define BE_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */
/* Data State config = {get_bits(6bits), valid(1bit)} */
-#define BE_CUST_DATA_STATE_S0_IDX 0 /* 7bits */
-#define BE_CUST_DATA_STATE_S1_IDX 7 /* 7bits */
+#define BE_CUST_DATA_STATE_S0_IDX 0 /* 7bits */
+#define BE_CUST_DATA_STATE_S1_IDX 7 /* 7bits */
#define BE_CUST_DATA_STATE_S2_IDX 14 /* 7bits */
-#define BE_CUST_DATA_STATE_WIDTH 21
+#define BE_CUST_DATA_STATE_WIDTH 21
#define BE_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */
#define BE_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */
#define BE_CUST_PIX_EXT_PIX_ALIGN_IDX 5 /* 5bits */
#define BE_CUST_PIX_EXT_PIX_MASK_IDX 10 /* 18bits */
#define BE_CUST_PIX_EXT_PIX_EN_IDX 28 /* 1bits */
-#define BE_CUST_PIX_EXT_WIDTH 29
+#define BE_CUST_PIX_EXT_WIDTH 29
/* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */
#define BE_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */
-#define BE_CUST_PIX_VALID_EOP_WIDTH 16
+#define BE_CUST_PIX_VALID_EOP_WIDTH 16
#define BE_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */
#define BE_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */
#define BE_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */
#define BE_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */
#endif /* _mipi_backend_common_defs_h_ */
-#endif /* _css_receiver_2400_common_defs_h_ */
+#endif /* _css_receiver_2400_common_defs_h_ */
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_ECC_TWO_BIT_ERR_IDX 6
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_DATA_ID_ERR_IDX 7
-
/* Bits for CSI2_FUNC_PROG register */
#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX 0
#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS 19
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_IDX 3
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_BITS 2
-
/* BITS for backend RAW16 and RAW 18 registers */
#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_IDX 0
#define _HRT_CSS_RECEIVER_2400_RAW16_EN_BITS 1
/* These hsync and vsync values are for HSS simulation only */
-#define _HRT_CSS_RECEIVER_2400_HSYNC_VAL (1<<16)
-#define _HRT_CSS_RECEIVER_2400_VSYNC_VAL (1<<17)
+#define _HRT_CSS_RECEIVER_2400_HSYNC_VAL BIT(16)
+#define _HRT_CSS_RECEIVER_2400_VSYNC_VAL BIT(17)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_WIDTH 28
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB 0
#define _DMA_V2_SPEC_DEV_B_XB_IDX (_DMA_V2_SPEC_DEV_A_XB_IDX + _DMA_V2_SPEC_DEV_A_XB_BITS)
#define _DMA_V2_SPEC_DEV_B_XB_BITS 8
#define _DMA_V2_SPEC_YB_IDX (_DMA_V2_SPEC_DEV_B_XB_IDX + _DMA_V2_SPEC_DEV_B_XB_BITS)
-#define _DMA_V2_SPEC_YB_BITS (32-_DMA_V2_SPEC_DEV_B_XB_BITS-_DMA_V2_SPEC_DEV_A_XB_BITS-_DMA_V2_CMD_BITS-_DMA_V2_CHANNEL_BITS)
+#define _DMA_V2_SPEC_YB_BITS (32 - _DMA_V2_SPEC_DEV_B_XB_BITS - _DMA_V2_SPEC_DEV_A_XB_BITS - _DMA_V2_CMD_BITS - _DMA_V2_CHANNEL_BITS)
/* */
#define _DMA_V2_CMD_CTRL_IDX 4
#define _DMA_V2_STRIDE_BITS 32
/* Command IDs */
-#define _DMA_V2_MOVE_B2A_COMMAND 0
-#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1
-#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2
-#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3
-#define _DMA_V2_MOVE_A2B_COMMAND 4
-#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5
-#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6
-#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7
-#define _DMA_V2_INIT_A_COMMAND 8
-#define _DMA_V2_INIT_A_BLOCK_COMMAND 9
-#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10
-#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11
-#define _DMA_V2_INIT_B_COMMAND 12
-#define _DMA_V2_INIT_B_BLOCK_COMMAND 13
-#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14
-#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15
-#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32
-#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33
-#define _DMA_V2_SET_CRUN_COMMAND 62
+#define _DMA_V2_MOVE_B2A_COMMAND 0
+#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1
+#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2
+#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3
+#define _DMA_V2_MOVE_A2B_COMMAND 4
+#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5
+#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6
+#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7
+#define _DMA_V2_INIT_A_COMMAND 8
+#define _DMA_V2_INIT_A_BLOCK_COMMAND 9
+#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10
+#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11
+#define _DMA_V2_INIT_B_COMMAND 12
+#define _DMA_V2_INIT_B_BLOCK_COMMAND 13
+#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14
+#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15
+#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32
+#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33
+#define _DMA_V2_SET_CRUN_COMMAND 62
/* Channel Parameter IDs */
-#define _DMA_V2_PACKING_SETUP_PARAM 0
-#define _DMA_V2_STRIDE_A_PARAM 1
-#define _DMA_V2_ELEM_CROPPING_A_PARAM 2
-#define _DMA_V2_WIDTH_A_PARAM 3
-#define _DMA_V2_STRIDE_B_PARAM 4
-#define _DMA_V2_ELEM_CROPPING_B_PARAM 5
-#define _DMA_V2_WIDTH_B_PARAM 6
-#define _DMA_V2_HEIGHT_PARAM 7
-#define _DMA_V2_QUEUED_CMDS 8
+#define _DMA_V2_PACKING_SETUP_PARAM 0
+#define _DMA_V2_STRIDE_A_PARAM 1
+#define _DMA_V2_ELEM_CROPPING_A_PARAM 2
+#define _DMA_V2_WIDTH_A_PARAM 3
+#define _DMA_V2_STRIDE_B_PARAM 4
+#define _DMA_V2_ELEM_CROPPING_B_PARAM 5
+#define _DMA_V2_WIDTH_B_PARAM 6
+#define _DMA_V2_HEIGHT_PARAM 7
+#define _DMA_V2_QUEUED_CMDS 8
/* Parameter Constants */
#define _DMA_V2_ZERO_EXTEND 0
#define _DMA_V2_ADDR_SEL_COMP_BITS 4
#define _DMA_V2_ADDR_SEL_CH_REG_IDX 2
#define _DMA_V2_ADDR_SEL_CH_REG_BITS 6
-#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS+_DMA_V2_ADDR_SEL_CH_REG_IDX)
+#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS + _DMA_V2_ADDR_SEL_CH_REG_IDX)
#define _DMA_V2_ADDR_SEL_PARAM_BITS 4
#define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX 2
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX 2
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS 6
-#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX+_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS)
+#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX + _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS)
#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS 4
#define _DMA_V2_FSM_GROUP_CMD_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_PACK_IDX 5
#define _DMA_V2_FSM_GROUP_FSM_REQ_IDX 6
#define _DMA_V2_FSM_GROUP_FSM_WR_IDX 7
-
+
#define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX 2
#define HRT_GDC_FRAC_BITS 10 /* Number of fractional bits in the GDC block, driven by the size of the LUT */
#define HRT_GDC_BLI_FRAC_BITS 4 /* Number of fractional bits for the bi-linear interpolation type */
-#define HRT_GDC_BLI_COEF_ONE (1 << HRT_GDC_BLI_FRAC_BITS)
+#define HRT_GDC_BLI_COEF_ONE BIT(HRT_GDC_BLI_FRAC_BITS)
#define HRT_GDC_BCI_COEF_BITS 14 /* 14 bits per coefficient */
-#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS-2)) /* We represent signed 10 bit coefficients. */
- /* The supported range is [-256, .., +256] */
- /* in 14-bit signed notation, */
- /* We need all ten bits (MSB must be zero). */
- /* -s is inserted to solve this issue, and */
- /* therefore "1" is equal to +256. */
-#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1)
+#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS - 2)) /* We represent signed 10 bit coefficients. */
+ /* The supported range is [-256, .., +256] */
+ /* in 14-bit signed notation, */
+ /* We need all ten bits (MSB must be zero). */
+ /* -s is inserted to solve this issue, and */
+ /* therefore "1" is equal to +256. */
+#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1)
-#define HRT_GDC_LUT_BYTES (HRT_GDC_N*4*2) /* 1024 addresses, 4 coefficients per address, */
- /* 2 bytes per coefficient */
+#define HRT_GDC_LUT_BYTES (HRT_GDC_N * 4 * 2) /* 1024 addresses, 4 coefficients per address, */
+ /* 2 bytes per coefficient */
-#define _HRT_GDC_REG_ALIGN 4
+#define _HRT_GDC_REG_ALIGN 4
// 31 30 29 25 24 0
// |-----|---|--------|------------------------|
// | CMD | C | Reg_ID | Value |
-
// There are just two commands possible for the GDC block:
- // 1 - Configure reg
- // 0 - Data token
-
+ // 1 - Configure reg
+ // 0 - Data token
+
// C - Reserved bit
// Used in protocol to indicate whether it is C-run or other type of runs
// In case of C-run, this bit has a value of 1, for all the other runs, it is 0.
// Reg_ID - Address of the register to be configured
-
+
// Value - Value to store to the addressed register, maximum of 24 bits
- // Configure reg command is not followed by any other token.
- // The address of the register and the data to be filled in is contained in the same token
-
+ // Configure reg command is not followed by any other token.
+ // The address of the register and the data to be filled in is contained in the same token
+
// When the first data token is received, it must be:
// 1. FRX and FRY (device configured in one of the scaling modes) ***DEFAULT MODE***, or,
// 2. P0'X (device configured in one of the tetragon modes)
// After the first data token is received, pre-defined number of tokens with the following meaning follow:
// 1. two tokens: SRC address ; DST address
// 2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address
-
+
#define HRT_GDC_CONFIG_CMD 1
#define HRT_GDC_DATA_CMD 0
-
#define HRT_GDC_CMD_POS 31
#define HRT_GDC_CMD_BITS 1
#define HRT_GDC_CRUN_POS 30
#define HRT_GDC_FRYIPXFRX_BITS 26
#define HRT_GDC_P0X_BITS 23
-
-#define HRT_GDC_MAX_OXDIM (8192-64)
+#define HRT_GDC_MAX_OXDIM (8192 - 64)
#define HRT_GDC_MAX_OYDIM 4095
-#define HRT_GDC_MAX_IXDIM (8192-64)
+#define HRT_GDC_MAX_IXDIM (8192 - 64)
#define HRT_GDC_MAX_IYDIM 4095
#define HRT_GDC_MAX_DS_FAC 16
-#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC*HRT_GDC_N - 1)
+#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC * HRT_GDC_N - 1)
#define HRT_GDC_MAX_DY HRT_GDC_MAX_DX
-
/* GDC lookup tables entries are 10 bits values, but they're
stored 2 by 2 as 32 bit values, yielding 16 bits per entry.
A GDC lookup table contains 64 * 4 elements */
#define HRT_GDC_MODE_SCALING 0
#define HRT_GDC_MODE_TETRAGON 1
-#define HRT_GDC_LUT_COEFF_OFFSET 16
-#define HRT_GDC_FRY_BIT_OFFSET 16
-// FRYIPXFRX is the only register where we store two values in one field,
-// to save one token in the scaling protocol.
-// Like this, we have three tokens in the scaling protocol,
+#define HRT_GDC_LUT_COEFF_OFFSET 16
+#define HRT_GDC_FRY_BIT_OFFSET 16
+// FRYIPXFRX is the only register where we store two values in one field,
+// to save one token in the scaling protocol.
+// Like this, we have three tokens in the scaling protocol,
// Otherwise, we would have had four.
// The register bit-map is:
// 31 26 25 16 15 10 9 0
// |------|----------|------|----------|
// | XXXX | FRY | IPX | FRX |
-
#define HRT_GDC_CE_FSM0_POS 0
#define HRT_GDC_CE_FSM0_LEN 2
#define HRT_GDC_CE_OPY_POS 2
// 31 16 15 2 1 0
// |----------------|-----------|----|
// | OPX | OPY |FSM0|
-// However, for the time being at least,
+// However, for the time being at least,
// this implementation is meaningless in hss model,
// So, we just return 0
-
#define HRT_GDC_CHK_ENGINE_IDX 0
#define HRT_GDC_WOIX_IDX 1
#define HRT_GDC_WOIY_IDX 2
#define HRT_GDC_LUT_IDX 32
-
#endif /* HRT_GDC_v2_defs_h_ */
#define HIVE_GP_TIMER_RESET_REG_IDX 0
#define HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX 1
#define HIVE_GP_TIMER_ENABLE_REG_IDX(timer) (HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX + 1 + timer)
-#define HIVE_GP_TIMER_VALUE_REG_IDX(timer,timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer)
-#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer,timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer)
-#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer,timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer)
-#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq,timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq)
-#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq)
-#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq)
+#define HIVE_GP_TIMER_VALUE_REG_IDX(timer, timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer)
+#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer, timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer)
+#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer, timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer)
+#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq, timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq)
+#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq)
+#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq)
#define HIVE_GP_TIMER_COUNT_TYPE_HIGH 0
#define HIVE_GP_TIMER_COUNT_TYPE_LOW 1
#define HIVE_GP_TIMER_COUNT_TYPE_NEGEDGE 3
#define HIVE_GP_TIMER_COUNT_TYPES 4
-#endif /* _gp_timer_defs_h */
+#endif /* _gp_timer_defs_h */
#define _gpio_block_reg_di_debounce_cnt_3 14
#define _gpio_block_reg_di_active_level 15
-
/* read-only registers */
#define _gpio_block_reg_di 16
and in the DMA parameter list */
#define HIVE_ISP_DDR_DMA_SPECS {{32, 8}, {16, 16}, {18, 14}, {25, 10}, {21, 12}}
#define HIVE_ISP_DDR_WORD_BITS 256
-#define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS/8)
+#define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS / 8)
#define HIVE_ISP_DDR_BYTES (512 * 1024 * 1024) /* hss only */
#define HIVE_ISP_DDR_BYTES_RTL (127 * 1024 * 1024) /* RTL only */
#define HIVE_ISP_DDR_SMALL_BYTES (128 * 256 / 8)
#define HIVE_ISP_PAGE_SHIFT 12
-#define HIVE_ISP_PAGE_SIZE (1<<HIVE_ISP_PAGE_SHIFT)
+#define HIVE_ISP_PAGE_SIZE BIT(HIVE_ISP_PAGE_SHIFT)
#define CSS_DDR_WORD_BITS HIVE_ISP_DDR_WORD_BITS
#define CSS_DDR_WORD_BYTES HIVE_ISP_DDR_WORD_BYTES
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I4_I0 51
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I5_I0 52
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I6_I0 53
-#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I7_I0 54
+#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I7_I0 54
#define HIVE_GP_TIMER_MIPI_SOL_BIT_ID 55
#define HIVE_GP_TIMER_MIPI_EOL_BIT_ID 56
#define HIVE_GP_TIMER_MIPI_SOF_BIT_ID 57
/* port definititions SP streaming monitor, monitors the status of streaming ports at the SP side of the streaming FIFO's */
#define SP_STR_MON_PORT_SP2SIF 0
#define SP_STR_MON_PORT_SIF2SP 1
-#define SP_STR_MON_PORT_SP2MC 2
+#define SP_STR_MON_PORT_SP2MC 2
#define SP_STR_MON_PORT_MC2SP 3
-#define SP_STR_MON_PORT_SP2DMA 4
+#define SP_STR_MON_PORT_SP2DMA 4
#define SP_STR_MON_PORT_DMA2SP 5
-#define SP_STR_MON_PORT_SP2ISP 6
+#define SP_STR_MON_PORT_SP2ISP 6
#define SP_STR_MON_PORT_ISP2SP 7
#define SP_STR_MON_PORT_SP2GPD 8
#define SP_STR_MON_PORT_FA2SP 9
-#define SP_STR_MON_PORT_SP2ISYS 10
+#define SP_STR_MON_PORT_SP2ISYS 10
#define SP_STR_MON_PORT_ISYS2SP 11
#define SP_STR_MON_PORT_SP2PIFA 12
#define SP_STR_MON_PORT_PIFA2SP 13
/* port definititions ISP streaming monitor, monitors the status of streaming ports at the ISP side of the streaming FIFO's */
#define ISP_STR_MON_PORT_ISP2PIFA 0
#define ISP_STR_MON_PORT_PIFA2ISP 1
-#define ISP_STR_MON_PORT_ISP2PIFB 2
+#define ISP_STR_MON_PORT_ISP2PIFB 2
#define ISP_STR_MON_PORT_PIFB2ISP 3
-#define ISP_STR_MON_PORT_ISP2DMA 4
+#define ISP_STR_MON_PORT_ISP2DMA 4
#define ISP_STR_MON_PORT_DMA2ISP 5
-#define ISP_STR_MON_PORT_ISP2GDC1 6
+#define ISP_STR_MON_PORT_ISP2GDC1 6
#define ISP_STR_MON_PORT_GDC12ISP 7
-#define ISP_STR_MON_PORT_ISP2GDC2 8
+#define ISP_STR_MON_PORT_ISP2GDC2 8
#define ISP_STR_MON_PORT_GDC22ISP 9
-#define ISP_STR_MON_PORT_ISP2GPD 10
+#define ISP_STR_MON_PORT_ISP2GPD 10
#define ISP_STR_MON_PORT_FA2ISP 11
-#define ISP_STR_MON_PORT_ISP2SP 12
+#define ISP_STR_MON_PORT_ISP2SP 12
#define ISP_STR_MON_PORT_SP2ISP 13
/* previously used ISP streaming monitor port identifiers, kept for backward compatibility */
#define ISP_STR_MON_PORT_SND_PIF_A ISP_STR_MON_PORT_ISP2PIFA
#define ISP_STR_MON_PORT_RCV_PIF_A ISP_STR_MON_PORT_PIFA2ISP
-#define ISP_STR_MON_PORT_SND_PIF_B ISP_STR_MON_PORT_ISP2PIFB
+#define ISP_STR_MON_PORT_SND_PIF_B ISP_STR_MON_PORT_ISP2PIFB
#define ISP_STR_MON_PORT_RCV_PIF_B ISP_STR_MON_PORT_PIFB2ISP
-#define ISP_STR_MON_PORT_SND_DMA ISP_STR_MON_PORT_ISP2DMA
-#define ISP_STR_MON_PORT_RCV_DMA ISP_STR_MON_PORT_DMA2ISP
-#define ISP_STR_MON_PORT_SND_GDC ISP_STR_MON_PORT_ISP2GDC1
+#define ISP_STR_MON_PORT_SND_DMA ISP_STR_MON_PORT_ISP2DMA
+#define ISP_STR_MON_PORT_RCV_DMA ISP_STR_MON_PORT_DMA2ISP
+#define ISP_STR_MON_PORT_SND_GDC ISP_STR_MON_PORT_ISP2GDC1
#define ISP_STR_MON_PORT_RCV_GDC ISP_STR_MON_PORT_GDC12ISP
-#define ISP_STR_MON_PORT_SND_GPD ISP_STR_MON_PORT_ISP2GPD
+#define ISP_STR_MON_PORT_SND_GPD ISP_STR_MON_PORT_ISP2GPD
#define ISP_STR_MON_PORT_RCV_GPD ISP_STR_MON_PORT_FA2ISP
#define ISP_STR_MON_PORT_SND_SP ISP_STR_MON_PORT_ISP2SP
#define ISP_STR_MON_PORT_RCV_SP ISP_STR_MON_PORT_SP2ISP
-
+
/* port definititions MOD streaming monitor, monitors the status of streaming ports at the module side of the streaming FIFO's */
#define MOD_STR_MON_PORT_PIFA2CELLS 0
#define MOD_STR_MON_PORT_SND_GDC 12
#define MOD_STR_MON_PORT_RCV_GDC 13
-
/* testbench signals: */
/* testbench GP adapter register ids */
#define HIVE_TESTBENCH_IDLE_REG_IDX 4
#define HIVE_TESTBENCH_GPIO_DATA_IN_REG_IDX 5
#define HIVE_TESTBENCH_MIPI_BFM_EN_REG_IDX 6
-#define HIVE_TESTBENCH_CSI_CONFIG_REG_IDX 7
+#define HIVE_TESTBENCH_CSI_CONFIG_REG_IDX 7
#define HIVE_TESTBENCH_DDR_STALL_EN_REG_IDX 8
#define HIVE_TESTBENCH_ISP_PMEM_ERROR_IRQ_REG_IDX 9
#define ISP testbench_isp_isp
#define SP testbench_isp_scp
-#define IF_PRIM testbench_isp_ifmt_ift_prim
+#define IF_PRIM testbench_isp_ifmt_ift_prim
#define IF_PRIM_B testbench_isp_ifmt_ift_prim_b
#define IF_SEC testbench_isp_ifmt_ift_sec
#define IF_SEC_MASTER testbench_isp_ifmt_ift_sec_mt_out
* The definitions are taken from <system>_defs.h
*/
typedef enum hrt_isp_css_irq {
- hrt_isp_css_irq_gpio_pin_0 = HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_1 = HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_2 = HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_3 = HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_4 = HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_5 = HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_6 = HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_7 = HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_8 = HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_9 = HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_10 = HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_11 = HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID ,
- hrt_isp_css_irq_sp = HIVE_GP_DEV_IRQ_SP_BIT_ID ,
- hrt_isp_css_irq_isp = HIVE_GP_DEV_IRQ_ISP_BIT_ID ,
- hrt_isp_css_irq_isys = HIVE_GP_DEV_IRQ_ISYS_BIT_ID ,
- hrt_isp_css_irq_isel = HIVE_GP_DEV_IRQ_ISEL_BIT_ID ,
- hrt_isp_css_irq_ifmt = HIVE_GP_DEV_IRQ_IFMT_BIT_ID ,
- hrt_isp_css_irq_sp_stream_mon = HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID ,
- hrt_isp_css_irq_isp_stream_mon = HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID ,
- hrt_isp_css_irq_mod_stream_mon = HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID ,
+ hrt_isp_css_irq_gpio_pin_0 = HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_1 = HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_2 = HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_3 = HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_4 = HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_5 = HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_6 = HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_7 = HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_8 = HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_9 = HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_10 = HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_11 = HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID,
+ hrt_isp_css_irq_sp = HIVE_GP_DEV_IRQ_SP_BIT_ID,
+ hrt_isp_css_irq_isp = HIVE_GP_DEV_IRQ_ISP_BIT_ID,
+ hrt_isp_css_irq_isys = HIVE_GP_DEV_IRQ_ISYS_BIT_ID,
+ hrt_isp_css_irq_isel = HIVE_GP_DEV_IRQ_ISEL_BIT_ID,
+ hrt_isp_css_irq_ifmt = HIVE_GP_DEV_IRQ_IFMT_BIT_ID,
+ hrt_isp_css_irq_sp_stream_mon = HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID,
+ hrt_isp_css_irq_isp_stream_mon = HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID,
+ hrt_isp_css_irq_mod_stream_mon = HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID,
#ifdef _HIVE_ISP_CSS_2401_SYSTEM
- hrt_isp_css_irq_is2401 = HIVE_GP_DEV_IRQ_IS2401_BIT_ID ,
+ hrt_isp_css_irq_is2401 = HIVE_GP_DEV_IRQ_IS2401_BIT_ID,
#else
- hrt_isp_css_irq_isp_pmem_error = HIVE_GP_DEV_IRQ_ISP_PMEM_ERROR_BIT_ID ,
+ hrt_isp_css_irq_isp_pmem_error = HIVE_GP_DEV_IRQ_ISP_PMEM_ERROR_BIT_ID,
#endif
- hrt_isp_css_irq_isp_bamem_error = HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID ,
- hrt_isp_css_irq_isp_dmem_error = HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID ,
- hrt_isp_css_irq_sp_icache_mem_error = HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID ,
- hrt_isp_css_irq_sp_dmem_error = HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID ,
- hrt_isp_css_irq_mmu_cache_mem_error = HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID ,
- hrt_isp_css_irq_gp_timer_0 = HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID ,
- hrt_isp_css_irq_gp_timer_1 = HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID ,
- hrt_isp_css_irq_sw_pin_0 = HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID ,
- hrt_isp_css_irq_sw_pin_1 = HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID ,
- hrt_isp_css_irq_dma = HIVE_GP_DEV_IRQ_DMA_BIT_ID ,
- hrt_isp_css_irq_sp_stream_mon_b = HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID ,
+ hrt_isp_css_irq_isp_bamem_error = HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID,
+ hrt_isp_css_irq_isp_dmem_error = HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID,
+ hrt_isp_css_irq_sp_icache_mem_error = HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID,
+ hrt_isp_css_irq_sp_dmem_error = HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID,
+ hrt_isp_css_irq_mmu_cache_mem_error = HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID,
+ hrt_isp_css_irq_gp_timer_0 = HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID,
+ hrt_isp_css_irq_gp_timer_1 = HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID,
+ hrt_isp_css_irq_sw_pin_0 = HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID,
+ hrt_isp_css_irq_sw_pin_1 = HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID,
+ hrt_isp_css_irq_dma = HIVE_GP_DEV_IRQ_DMA_BIT_ID,
+ hrt_isp_css_irq_sp_stream_mon_b = HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID,
/* this must (obviously) be the last on in the enum */
hrt_isp_css_irq_num_irqs
} hrt_isp_css_irq_t;
#include <streaming_to_mipi_defs.h>
-#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS)-1)
-#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS)-1)
+#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS) - 1)
+#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS) - 1)
#define _HIVE_STR_TO_MIPI_FMT_TYPE_LSB (HIVE_STR_TO_MIPI_CH_ID_LSB + HIVE_ISP_CH_ID_BITS)
#define _HIVE_STR_TO_MIPI_DATA_B_LSB (HIVE_STR_TO_MIPI_DATA_A_LSB + HIVE_IF_PIXEL_WIDTH)
-
+
#endif /* _hive_isp_css_streaming_to_mipi_types_hrt_h_ */
* more details.
*/
-#ifndef _HRT_HIVE_TYPES_H
-#define _HRT_HIVE_TYPES_H
+#ifndef _HRT_HIVE_TYPES_H
+#define _HRT_HIVE_TYPES_H
#include "version.h"
#include "defs.h"
#ifndef HRTCAT3
-#define _HRTCAT3(m,n,o) m##n##o
-#define HRTCAT3(m,n,o) _HRTCAT3(m,n,o)
+#define _HRTCAT3(m, n, o) m##n##o
+#define HRTCAT3(m, n, o) _HRTCAT3(m, n, o)
#endif
#ifndef HRTCAT4
-#define _HRTCAT4(m,n,o,p) m##n##o##p
-#define HRTCAT4(m,n,o,p) _HRTCAT4(m,n,o,p)
+#define _HRTCAT4(m, n, o, p) m##n##o##p
+#define HRTCAT4(m, n, o, p) _HRTCAT4(m, n, o, p)
#endif
#ifndef HRTMIN
-#define HRTMIN(a,b) (((a)<(b))?(a):(b))
+#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
-
+
#ifndef HRTMAX
-#define HRTMAX(a,b) (((a)>(b))?(a):(b))
+#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
/* boolean data type */
#define HRT_ADDRESS_WIDTH 32
#endif
-#define HRT_DATA_BYTES (HRT_DATA_WIDTH/8)
-#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH/8)
+#define HRT_DATA_BYTES (HRT_DATA_WIDTH / 8)
+#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH / 8)
#if HRT_DATA_WIDTH == 64
typedef hive_uint64 hrt_data;
#endif
#if HRT_ADDRESS_WIDTH == 64
-typedef hive_uint64 hrt_address;
+typedef hive_uint64 hrt_address;
#elif HRT_ADDRESS_WIDTH == 32
typedef hive_uint32 hrt_address;
#else
typedef hive_uint hive_mmio_id;
typedef hive_mmio_id hive_slave_id;
typedef hive_mmio_id hive_port_id;
-typedef hive_mmio_id hive_master_id;
+typedef hive_mmio_id hive_master_id;
typedef hive_mmio_id hive_mem_id;
typedef hive_mmio_id hive_dev_id;
typedef hive_mmio_id hive_fifo_id;
typedef hive_uint hive_msink_id;
/* HRT specific */
-typedef char* hive_program;
-typedef char* hive_function;
+typedef char *hive_program;
+typedef char *hive_function;
#endif /* _HRT_HIVE_TYPES_H */
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_4 4
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_5 5
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_6 6
-#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7
+#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_FSYNC_LUT_REG 8
#define HIVE_IFMT_GP_REGS_SRST_IDX 9
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IDX 10
#define HIVE_ISEL_GP_REGS_SYNCGEN_ENABLE_IDX 0
#define HIVE_ISEL_GP_REGS_SYNCGEN_FREE_RUNNING_IDX 1
#define HIVE_ISEL_GP_REGS_SYNCGEN_PAUSE_IDX 2
-#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_FRAMES_IDX 3
-#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_PIX_IDX 4
-#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_LINES_IDX 5
-#define HIVE_ISEL_GP_REGS_SYNCGEN_HBLANK_CYCLES_IDX 6
-#define HIVE_ISEL_GP_REGS_SYNCGEN_VBLANK_CYCLES_IDX 7
+#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_FRAMES_IDX 3
+#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_PIX_IDX 4
+#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_LINES_IDX 5
+#define HIVE_ISEL_GP_REGS_SYNCGEN_HBLANK_CYCLES_IDX 6
+#define HIVE_ISEL_GP_REGS_SYNCGEN_VBLANK_CYCLES_IDX 7
-#define HIVE_ISEL_GP_REGS_SOF_IDX 8
-#define HIVE_ISEL_GP_REGS_EOF_IDX 9
-#define HIVE_ISEL_GP_REGS_SOL_IDX 10
-#define HIVE_ISEL_GP_REGS_EOL_IDX 11
+#define HIVE_ISEL_GP_REGS_SOF_IDX 8
+#define HIVE_ISEL_GP_REGS_EOF_IDX 9
+#define HIVE_ISEL_GP_REGS_SOL_IDX 10
+#define HIVE_ISEL_GP_REGS_EOL_IDX 11
-#define HIVE_ISEL_GP_REGS_PRBS_ENABLE 12
-#define HIVE_ISEL_GP_REGS_PRBS_ENABLE_PORT_B 13
-#define HIVE_ISEL_GP_REGS_PRBS_LFSR_RESET_VALUE 14
+#define HIVE_ISEL_GP_REGS_PRBS_ENABLE 12
+#define HIVE_ISEL_GP_REGS_PRBS_ENABLE_PORT_B 13
+#define HIVE_ISEL_GP_REGS_PRBS_LFSR_RESET_VALUE 14
-#define HIVE_ISEL_GP_REGS_TPG_ENABLE 15
-#define HIVE_ISEL_GP_REGS_TPG_ENABLE_PORT_B 16
-#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_MASK_IDX 17
-#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_MASK_IDX 18
-#define HIVE_ISEL_GP_REGS_TPG_XY_CNT_MASK_IDX 19
-#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_DELTA_IDX 20
-#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_DELTA_IDX 21
-#define HIVE_ISEL_GP_REGS_TPG_MODE_IDX 22
-#define HIVE_ISEL_GP_REGS_TPG_R1_IDX 23
+#define HIVE_ISEL_GP_REGS_TPG_ENABLE 15
+#define HIVE_ISEL_GP_REGS_TPG_ENABLE_PORT_B 16
+#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_MASK_IDX 17
+#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_MASK_IDX 18
+#define HIVE_ISEL_GP_REGS_TPG_XY_CNT_MASK_IDX 19
+#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_DELTA_IDX 20
+#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_DELTA_IDX 21
+#define HIVE_ISEL_GP_REGS_TPG_MODE_IDX 22
+#define HIVE_ISEL_GP_REGS_TPG_R1_IDX 23
#define HIVE_ISEL_GP_REGS_TPG_G1_IDX 24
#define HIVE_ISEL_GP_REGS_TPG_B1_IDX 25
#define HIVE_ISEL_GP_REGS_TPG_R2_IDX 26
#define HIVE_ISEL_GP_REGS_TPG_G2_IDX 27
#define HIVE_ISEL_GP_REGS_TPG_B2_IDX 28
-
#define HIVE_ISEL_GP_REGS_CH_ID_IDX 29
#define HIVE_ISEL_GP_REGS_FMT_TYPE_IDX 30
#define HIVE_ISEL_GP_REGS_DATA_SEL_IDX 31
#ifndef _input_switch_2400_defs_h
#define _input_switch_2400_defs_h
-#define _HIVE_INPUT_SWITCH_GET_LUT_REG_ID(ch_id, fmt_type) (((ch_id)*2) + ((fmt_type)>=16))
-#define _HIVE_INPUT_SWITCH_GET_LUT_REG_LSB(fmt_type) (((fmt_type)%16) * 2)
+#define _HIVE_INPUT_SWITCH_GET_LUT_REG_ID(ch_id, fmt_type) (((ch_id) * 2) + ((fmt_type) >= 16))
+#define _HIVE_INPUT_SWITCH_GET_LUT_REG_LSB(fmt_type) (((fmt_type) % 16) * 2)
#define HIVE_INPUT_SWITCH_SELECT_NO_OUTPUT 0
#define HIVE_INPUT_SWITCH_SELECT_IF_PRIM 1
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID 20
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID 21
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID 22
-
/* register reset value */
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL 128
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL 128
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL 128
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL 3
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL 3
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL 3
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL 3
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL 3
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL 3
#define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL 0
-#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL 128
-#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3
+#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL 128
+#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3
#define ISYS_CTRL_INIT_REG_RSTVAL 0
-#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
+#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL 0
-#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL 0
+#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL 0
/* register width value */
-#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH 9
-#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH 9
-#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH 9
-#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
-#define ISYS_CTRL_INIT_REG_WIDTH 3
+#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH 9
+#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH 9
+#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH 9
+#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
+#define ISYS_CTRL_INIT_REG_WIDTH 3
#define ISYS_CTRL_LAST_COMMAND_REG_WIDTH 32 /* slave data width */
#define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH 32
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH 32
/*
InpSysCaptFramesAcq 1/0 [3:0] - 'b0000
[7:4] - CaptPortId,
- CaptA-'b0000
- CaptB-'b0001
- CaptC-'b0010
+ CaptA-'b0000
+ CaptB-'b0001
+ CaptC-'b0010
[31:16] - NOF_frames
InpSysCaptFrameExt 2/0 [3:0] - 'b0001'
[7:4] - CaptPortId,
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
2/1 [31:0] - external capture address
-InpSysAcqFrame 2/0 [3:0] - 'b0010,
+InpSysAcqFrame 2/0 [3:0] - 'b0010,
[31:4] - NOF_ext_mem_words
2/1 [31:0] - external memory read start address
-InpSysOverruleON 1/0 [3:0] - 'b0011,
+InpSysOverruleON 1/0 [3:0] - 'b0011,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
-
-InpSysOverruleOFF 1/0 [3:0] - 'b0100,
+InpSysOverruleOFF 1/0 [3:0] - 'b0100,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
-
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
-InpSysOverruleCmd 2/0 [3:0] - 'b0101,
+InpSysOverruleCmd 2/0 [3:0] - 'b0101,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
-
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
2/1 [31:0] - command token value for port opid
-
acknowledge tokens:
InpSysAckCFA 1/0 [3:0] - 'b0000
[7:4] - CaptPortId,
- CaptA-'b0000
- CaptB- 'b0001
- CaptC-'b0010
+ CaptA-'b0000
+ CaptB- 'b0001
+ CaptC-'b0010
[31:16] - NOF_frames
InpSysAckCFE 1/0 [3:0] - 'b0001'
[7:4] - CaptPortId,
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
InpSysAckAF 1/0 [3:0] - 'b0010
-InpSysAckOverruleON 1/0 [3:0] - 'b0011,
+InpSysAckOverruleON 1/0 [3:0] - 'b0011,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
-
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
-InpSysAckOverruleOFF 1/0 [3:0] - 'b0100,
+InpSysAckOverruleOFF 1/0 [3:0] - 'b0100,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
-
-InpSysAckOverrule 2/0 [3:0] - 'b0101,
+InpSysAckOverrule 2/0 [3:0] - 'b0101,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
-
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
2/1 [31:0] - acknowledge token value from port opid
-
-
*/
-
/* Command and acknowledge tokens IDs */
#define ISYS_CTRL_CAPT_FRAMES_ACQ_TOKEN_ID 0 /* 0000b */
#define ISYS_CTRL_CAPT_FRAME_EXT_TOKEN_ID 1 /* 0001b */
#define ISYS_CTRL_TOKEN_ID_IDX 0
#define ISYS_CTRL_TOKEN_ID_BITS (ISYS_CTRL_TOKEN_ID_MSB - ISYS_CTRL_TOKEN_ID_LSB + 1)
#define ISYS_CTRL_PORT_ID_IDX (ISYS_CTRL_TOKEN_ID_IDX + ISYS_CTRL_TOKEN_ID_BITS)
-#define ISYS_CTRL_PORT_ID_BITS (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB +1)
-#define ISYS_CTRL_NOF_CAPT_IDX ISYS_CTRL_NOF_CAPT_TOKEN_LSB
+#define ISYS_CTRL_PORT_ID_BITS (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB + 1)
+#define ISYS_CTRL_NOF_CAPT_IDX ISYS_CTRL_NOF_CAPT_TOKEN_LSB
#define ISYS_CTRL_NOF_CAPT_BITS (ISYS_CTRL_NOF_CAPT_TOKEN_MSB - ISYS_CTRL_NOF_CAPT_TOKEN_LSB + 1)
-#define ISYS_CTRL_NOF_EXT_IDX ISYS_CTRL_NOF_EXT_TOKEN_LSB
+#define ISYS_CTRL_NOF_EXT_IDX ISYS_CTRL_NOF_EXT_TOKEN_LSB
#define ISYS_CTRL_NOF_EXT_BITS (ISYS_CTRL_NOF_EXT_TOKEN_MSB - ISYS_CTRL_NOF_EXT_TOKEN_LSB + 1)
#define ISYS_CTRL_PORT_ID_CAPT_A 0 /* device ID for capture unit A */
#define ISYS_CTRL_PORT_ID_DMA_ACQ 7 /* device ID for dma unit */
#define ISYS_CTRL_NO_ACQ_ACK 16 /* no ack from acquisition unit */
-#define ISYS_CTRL_NO_DMA_ACK 0
+#define ISYS_CTRL_NO_DMA_ACK 0
#define ISYS_CTRL_NO_CAPT_ACK 16
-#endif /* _input_system_ctrl_defs_h */
+#endif /* _input_system_ctrl_defs_h */
#define _HRT_IRQ_CONTROLLER_REG_ALIGN 4
-#endif /* _irq_controller_defs_h */
+#endif /* _irq_controller_defs_h */
#define ISP_SRU_GUARDING 1
#define ISP_VLSU_GUARDING 1
-#define ISP_VRF_RAM 1
-#define ISP_SRF_RAM 1
+#define ISP_VRF_RAM 1
+#define ISP_SRF_RAM 1
#define ISP_SPLIT_VMUL_VADD_IS 0
#define ISP_RFSPLIT_FPGA 0
#define ISP_NWAY ISP_VEC_NELEMS
#define NBITS ISP_VEC_ELEMBITS
-#define _isp_ceil_div(a,b) (((a)+(b)-1)/(b))
+#define _isp_ceil_div(a, b) (((a) + (b) - 1) / (b))
#define ISP_VEC_ALIGN ISP_VMEM_ALIGN
#define _isp_acquisition_defs_h
#define _ISP_ACQUISITION_REG_ALIGN 4 /* assuming 32 bit control bus width */
-#define _ISP_ACQUISITION_BYTES_PER_ELEM 4
+#define _ISP_ACQUISITION_BYTES_PER_ELEM 4
/* --------------------------------------------------*/
/* REGISTER INFO */
/* --------------------------------------------------*/
-#define NOF_ACQ_REGS 12
+#define NOF_ACQ_REGS 12
// Register id's of MMIO slave accesible registers
-#define ACQ_START_ADDR_REG_ID 0
+#define ACQ_START_ADDR_REG_ID 0
#define ACQ_MEM_REGION_SIZE_REG_ID 1
#define ACQ_NUM_MEM_REGIONS_REG_ID 2
-#define ACQ_INIT_REG_ID 3
+#define ACQ_INIT_REG_ID 3
#define ACQ_RECEIVED_SHORT_PACKETS_REG_ID 4
#define ACQ_RECEIVED_LONG_PACKETS_REG_ID 5
#define ACQ_LAST_COMMAND_REG_ID 6
#define ACQ_NEXT_ACKNOWLEDGE_REG_ID 9
#define ACQ_FSM_STATE_INFO_REG_ID 10
#define ACQ_INT_CNTR_INFO_REG_ID 11
-
+
// Register width
-#define ACQ_START_ADDR_REG_WIDTH 9
-#define ACQ_MEM_REGION_SIZE_REG_WIDTH 9
-#define ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
-#define ACQ_INIT_REG_WIDTH 3
-#define ACQ_RECEIVED_SHORT_PACKETS_REG_WIDTH 32
-#define ACQ_RECEIVED_LONG_PACKETS_REG_WIDTH 32
-#define ACQ_LAST_COMMAND_REG_WIDTH 32
-#define ACQ_NEXT_COMMAND_REG_WIDTH 32
-#define ACQ_LAST_ACKNOWLEDGE_REG_WIDTH 32
-#define ACQ_NEXT_ACKNOWLEDGE_REG_WIDTH 32
-#define ACQ_FSM_STATE_INFO_REG_WIDTH ((MEM2STREAM_FSM_STATE_BITS * 3) + (ACQ_SYNCHRONIZER_FSM_STATE_BITS *3))
+#define ACQ_START_ADDR_REG_WIDTH 9
+#define ACQ_MEM_REGION_SIZE_REG_WIDTH 9
+#define ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
+#define ACQ_INIT_REG_WIDTH 3
+#define ACQ_RECEIVED_SHORT_PACKETS_REG_WIDTH 32
+#define ACQ_RECEIVED_LONG_PACKETS_REG_WIDTH 32
+#define ACQ_LAST_COMMAND_REG_WIDTH 32
+#define ACQ_NEXT_COMMAND_REG_WIDTH 32
+#define ACQ_LAST_ACKNOWLEDGE_REG_WIDTH 32
+#define ACQ_NEXT_ACKNOWLEDGE_REG_WIDTH 32
+#define ACQ_FSM_STATE_INFO_REG_WIDTH ((MEM2STREAM_FSM_STATE_BITS * 3) + (ACQ_SYNCHRONIZER_FSM_STATE_BITS * 3))
#define ACQ_INT_CNTR_INFO_REG_WIDTH 32
/* register reset value */
-#define ACQ_START_ADDR_REG_RSTVAL 0
+#define ACQ_START_ADDR_REG_RSTVAL 0
#define ACQ_MEM_REGION_SIZE_REG_RSTVAL 128
#define ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3
-#define ACQ_INIT_REG_RSTVAL 0
+#define ACQ_INIT_REG_RSTVAL 0
#define ACQ_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0
#define ACQ_RECEIVED_LONG_PACKETS_REG_RSTVAL 0
#define ACQ_LAST_COMMAND_REG_RSTVAL 0
#define ACQ_NEXT_COMMAND_REG_RSTVAL 0
#define ACQ_LAST_ACKNOWLEDGE_REG_RSTVAL 0
-#define ACQ_NEXT_ACKNOWLEDGE_REG_RSTVAL 0
+#define ACQ_NEXT_ACKNOWLEDGE_REG_RSTVAL 0
#define ACQ_FSM_STATE_INFO_REG_RSTVAL 0
-#define ACQ_INT_CNTR_INFO_REG_RSTVAL 0
+#define ACQ_INT_CNTR_INFO_REG_RSTVAL 0
/* bit definitions */
#define ACQ_INIT_RST_REG_BIT 0
/* TOKEN INFO */
/* --------------------------------------------------*/
#define ACQ_TOKEN_ID_LSB 0
-#define ACQ_TOKEN_ID_MSB 3
+#define ACQ_TOKEN_ID_MSB 3
#define ACQ_TOKEN_WIDTH (ACQ_TOKEN_ID_MSB - ACQ_TOKEN_ID_LSB + 1) // 4
#define ACQ_TOKEN_ID_IDX 0
#define ACQ_TOKEN_ID_BITS ACQ_TOKEN_WIDTH
#define ACQ_CMD_START_ADDR_IDX 4
#define ACQ_CMD_START_ADDR_BITS 9
#define ACQ_CMD_NOFWORDS_IDX 13
-#define ACQ_CMD_NOFWORDS_BITS 9
+#define ACQ_CMD_NOFWORDS_BITS 9
#define ACQ_MEM_REGION_ID_IDX 22
-#define ACQ_MEM_REGION_ID_BITS 9
+#define ACQ_MEM_REGION_ID_BITS 9
#define ACQ_PACKET_LENGTH_TOKEN_MSB 21
#define ACQ_PACKET_LENGTH_TOKEN_LSB 13
#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_MSB 9
#define ACQ_PACKET_MEM_REGION_ID_TOKEN_MSB 12 /* only for capt_end_of_packet_written */
#define ACQ_PACKET_MEM_REGION_ID_TOKEN_LSB 4 /* only for capt_end_of_packet_written */
-
/* Command tokens IDs */
#define ACQ_READ_REGION_AUTO_INCR_TOKEN_ID 0 //0000b
#define ACQ_READ_REGION_TOKEN_ID 1 //0001b
-#define ACQ_READ_REGION_SOP_TOKEN_ID 2 //0010b
+#define ACQ_READ_REGION_SOP_TOKEN_ID 2 //0010b
#define ACQ_INIT_TOKEN_ID 8 //1000b
/* Acknowledge token IDs */
#define ACQ_TOKEN_NOFWORDS_MSB 21
#define ACQ_TOKEN_NOFWORDS_LSB 13
#define ACQ_TOKEN_STARTADDR_MSB 12
-#define ACQ_TOKEN_STARTADDR_LSB 4
-
+#define ACQ_TOKEN_STARTADDR_LSB 4
/* --------------------------------------------------*/
/* MIPI */
/* --------------------------------------------------*/
#define WORD_COUNT_WIDTH 16
-#define PKT_CODE_WIDTH 6
-#define CHN_NO_WIDTH 2
+#define PKT_CODE_WIDTH 6
+#define CHN_NO_WIDTH 2
#define ERROR_INFO_WIDTH 8
-
+
#define LONG_PKTCODE_MAX 63
#define LONG_PKTCODE_MIN 16
#define SHORT_PKTCODE_MAX 15
#define ACQ_LINE_PAYLOAD 4
#define ACQ_GEN_SH_PKT 5
-
/* bit definition */
#define ACQ_PKT_TYPE_IDX 16
#define ACQ_PKT_TYPE_BITS 6
#define ACQ_ACK_PKT_LEN_IDX 4
#define ACQ_ACK_PKT_LEN_BITS 16
-
/* --------------------------------------------------*/
/* Packet Data Type */
/* --------------------------------------------------*/
-
#define ACQ_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */
#define ACQ_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */
#define ACQ_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */
#define ACQ_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */
#define ACQ_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */
#define ACQ_RGB444_DATA 32 /* 10 0000 RGB444 */
-#define ACQ_RGB555_DATA 33 /* 10 0001 RGB555 */
-#define ACQ_RGB565_DATA 34 /* 10 0010 RGB565 */
-#define ACQ_RGB666_DATA 35 /* 10 0011 RGB666 */
-#define ACQ_RGB888_DATA 36 /* 10 0100 RGB888 */
-#define ACQ_RAW6_DATA 40 /* 10 1000 RAW6 */
-#define ACQ_RAW7_DATA 41 /* 10 1001 RAW7 */
-#define ACQ_RAW8_DATA 42 /* 10 1010 RAW8 */
-#define ACQ_RAW10_DATA 43 /* 10 1011 RAW10 */
-#define ACQ_RAW12_DATA 44 /* 10 1100 RAW12 */
-#define ACQ_RAW14_DATA 45 /* 10 1101 RAW14 */
-#define ACQ_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
-#define ACQ_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
-#define ACQ_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
-#define ACQ_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
-#define ACQ_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
-#define ACQ_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
-#define ACQ_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
-#define ACQ_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
-#define ACQ_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
-#define ACQ_SOF_DATA 0 /* 00 0000 frame start */
-#define ACQ_EOF_DATA 1 /* 00 0001 frame end */
-#define ACQ_SOL_DATA 2 /* 00 0010 line start */
-#define ACQ_EOL_DATA 3 /* 00 0011 line end */
-#define ACQ_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
-#define ACQ_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
-#define ACQ_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
-#define ACQ_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
-#define ACQ_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
-#define ACQ_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
-#define ACQ_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
-#define ACQ_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
-#define ACQ_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
-#define ACQ_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
+#define ACQ_RGB555_DATA 33 /* 10 0001 RGB555 */
+#define ACQ_RGB565_DATA 34 /* 10 0010 RGB565 */
+#define ACQ_RGB666_DATA 35 /* 10 0011 RGB666 */
+#define ACQ_RGB888_DATA 36 /* 10 0100 RGB888 */
+#define ACQ_RAW6_DATA 40 /* 10 1000 RAW6 */
+#define ACQ_RAW7_DATA 41 /* 10 1001 RAW7 */
+#define ACQ_RAW8_DATA 42 /* 10 1010 RAW8 */
+#define ACQ_RAW10_DATA 43 /* 10 1011 RAW10 */
+#define ACQ_RAW12_DATA 44 /* 10 1100 RAW12 */
+#define ACQ_RAW14_DATA 45 /* 10 1101 RAW14 */
+#define ACQ_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
+#define ACQ_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
+#define ACQ_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
+#define ACQ_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
+#define ACQ_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
+#define ACQ_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
+#define ACQ_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
+#define ACQ_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
+#define ACQ_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
+#define ACQ_SOF_DATA 0 /* 00 0000 frame start */
+#define ACQ_EOF_DATA 1 /* 00 0001 frame end */
+#define ACQ_SOL_DATA 2 /* 00 0010 line start */
+#define ACQ_EOL_DATA 3 /* 00 0011 line end */
+#define ACQ_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
+#define ACQ_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
+#define ACQ_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
+#define ACQ_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
+#define ACQ_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
+#define ACQ_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
+#define ACQ_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
+#define ACQ_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
+#define ACQ_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
+#define ACQ_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
#define ACQ_RESERVED_DATA_TYPE_MIN 56
#define ACQ_RESERVED_DATA_TYPE_MAX 63
#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MIN 19
/* --------------------------------------------------*/
-#endif /* _isp_acquisition_defs_h */
+#endif /* _isp_acquisition_defs_h */
#define _isp_capture_defs_h
#define _ISP_CAPTURE_REG_ALIGN 4 /* assuming 32 bit control bus width */
-#define _ISP_CAPTURE_BITS_PER_ELEM 32 /* only for data, not SOP */
-#define _ISP_CAPTURE_BYTES_PER_ELEM (_ISP_CAPTURE_BITS_PER_ELEM/8 )
-#define _ISP_CAPTURE_BYTES_PER_WORD 32 /* 256/8 */
-#define _ISP_CAPTURE_ELEM_PER_WORD _ISP_CAPTURE_BYTES_PER_WORD / _ISP_CAPTURE_BYTES_PER_ELEM
+#define _ISP_CAPTURE_BITS_PER_ELEM 32 /* only for data, not SOP */
+#define _ISP_CAPTURE_BYTES_PER_ELEM (_ISP_CAPTURE_BITS_PER_ELEM / 8)
+#define _ISP_CAPTURE_BYTES_PER_WORD 32 /* 256/8 */
+#define _ISP_CAPTURE_ELEM_PER_WORD _ISP_CAPTURE_BYTES_PER_WORD / _ISP_CAPTURE_BYTES_PER_ELEM
//#define CAPT_RCV_ACK 1
-//#define CAPT_WRT_ACK 2
-//#define CAPT_IRQ_ACK 3
+//#define CAPT_WRT_ACK 2
+//#define CAPT_IRQ_ACK 3
/* --------------------------------------------------*/
// Register id's of MMIO slave accesible registers
#define CAPT_START_MODE_REG_ID 0
-#define CAPT_START_ADDR_REG_ID 1
-#define CAPT_MEM_REGION_SIZE_REG_ID 2
-#define CAPT_NUM_MEM_REGIONS_REG_ID 3
-#define CAPT_INIT_REG_ID 4
+#define CAPT_START_ADDR_REG_ID 1
+#define CAPT_MEM_REGION_SIZE_REG_ID 2
+#define CAPT_NUM_MEM_REGIONS_REG_ID 3
+#define CAPT_INIT_REG_ID 4
#define CAPT_START_REG_ID 5
-#define CAPT_STOP_REG_ID 6
+#define CAPT_STOP_REG_ID 6
#define CAPT_PACKET_LENGTH_REG_ID 7
-#define CAPT_RECEIVED_LENGTH_REG_ID 8
-#define CAPT_RECEIVED_SHORT_PACKETS_REG_ID 9
-#define CAPT_RECEIVED_LONG_PACKETS_REG_ID 10
-#define CAPT_LAST_COMMAND_REG_ID 11
+#define CAPT_RECEIVED_LENGTH_REG_ID 8
+#define CAPT_RECEIVED_SHORT_PACKETS_REG_ID 9
+#define CAPT_RECEIVED_LONG_PACKETS_REG_ID 10
+#define CAPT_LAST_COMMAND_REG_ID 11
#define CAPT_NEXT_COMMAND_REG_ID 12
#define CAPT_LAST_ACKNOWLEDGE_REG_ID 13
#define CAPT_NEXT_ACKNOWLEDGE_REG_ID 14
#define CAPT_FSM_STATE_INFO_REG_ID 15
// Register width
-#define CAPT_START_MODE_REG_WIDTH 1
+#define CAPT_START_MODE_REG_WIDTH 1
#define CAPT_START_ADDR_REG_WIDTH 9
#define CAPT_MEM_REGION_SIZE_REG_WIDTH 9
#define CAPT_NUM_MEM_REGIONS_REG_WIDTH 9
#define CAPT_WRITE2MEM_FSM_STATE_BITS 2
#define CAPT_SYNCHRONIZER_FSM_STATE_BITS 3
-
#define CAPT_PACKET_LENGTH_REG_WIDTH 17
-#define CAPT_RECEIVED_LENGTH_REG_WIDTH 17
+#define CAPT_RECEIVED_LENGTH_REG_WIDTH 17
#define CAPT_RECEIVED_SHORT_PACKETS_REG_WIDTH 32
#define CAPT_RECEIVED_LONG_PACKETS_REG_WIDTH 32
#define CAPT_LAST_COMMAND_REG_WIDTH 32
-/* #define CAPT_NEXT_COMMAND_REG_WIDTH 32 */
+/* #define CAPT_NEXT_COMMAND_REG_WIDTH 32 */
#define CAPT_LAST_ACKNOWLEDGE_REG_WIDTH 32
#define CAPT_NEXT_ACKNOWLEDGE_REG_WIDTH 32
#define CAPT_FSM_STATE_INFO_REG_WIDTH ((CAPT_WRITE2MEM_FSM_STATE_BITS * 3) + (CAPT_SYNCHRONIZER_FSM_STATE_BITS * 3))
-#define CAPT_INIT_RESTART_MEM_ADDR_WIDTH 9
-#define CAPT_INIT_RESTART_MEM_REGION_WIDTH 9
+#define CAPT_INIT_RESTART_MEM_ADDR_WIDTH 9
+#define CAPT_INIT_RESTART_MEM_REGION_WIDTH 9
/* register reset value */
-#define CAPT_START_MODE_REG_RSTVAL 0
+#define CAPT_START_MODE_REG_RSTVAL 0
#define CAPT_START_ADDR_REG_RSTVAL 0
#define CAPT_MEM_REGION_SIZE_REG_RSTVAL 128
-#define CAPT_NUM_MEM_REGIONS_REG_RSTVAL 3
+#define CAPT_NUM_MEM_REGIONS_REG_RSTVAL 3
#define CAPT_INIT_REG_RSTVAL 0
#define CAPT_START_REG_RSTVAL 0
#define CAPT_INIT_RESTART_MEM_REGION_LSB 13
#define CAPT_INIT_RESTART_MEM_REGION_MSB 21
-
#define CAPT_INIT_RST_REG_IDX CAPT_INIT_RST_REG_BIT
#define CAPT_INIT_RST_REG_BITS 1
#define CAPT_INIT_FLUSH_IDX CAPT_INIT_FLUSH_BIT
#define CAPT_INIT_RESYNC_IDX CAPT_INIT_RESYNC_BIT
#define CAPT_INIT_RESYNC_BITS 1
#define CAPT_INIT_RESTART_IDX CAPT_INIT_RESTART_BIT
-#define CAPT_INIT_RESTART_BITS 1
+#define CAPT_INIT_RESTART_BITS 1
#define CAPT_INIT_RESTART_MEM_ADDR_IDX CAPT_INIT_RESTART_MEM_ADDR_LSB
#define CAPT_INIT_RESTART_MEM_ADDR_BITS (CAPT_INIT_RESTART_MEM_ADDR_MSB - CAPT_INIT_RESTART_MEM_ADDR_LSB + 1)
#define CAPT_INIT_RESTART_MEM_REGION_IDX CAPT_INIT_RESTART_MEM_REGION_LSB
#define CAPT_INIT_RESTART_MEM_REGION_BITS (CAPT_INIT_RESTART_MEM_REGION_MSB - CAPT_INIT_RESTART_MEM_REGION_LSB + 1)
-
-
/* --------------------------------------------------*/
/* TOKEN INFO */
/* --------------------------------------------------*/
#define CAPT_TOKEN_ID_LSB 0
-#define CAPT_TOKEN_ID_MSB 3
+#define CAPT_TOKEN_ID_MSB 3
#define CAPT_TOKEN_WIDTH (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1) /* 4 */
/* Command tokens IDs */
#define CAPT_START_TOKEN_ID 0 /* 0000b */
#define CAPT_STOP_TOKEN_ID 1 /* 0001b */
-#define CAPT_FREEZE_TOKEN_ID 2 /* 0010b */
+#define CAPT_FREEZE_TOKEN_ID 2 /* 0010b */
#define CAPT_RESUME_TOKEN_ID 3 /* 0011b */
#define CAPT_INIT_TOKEN_ID 8 /* 1000b */
-#define CAPT_START_TOKEN_BIT 0
+#define CAPT_START_TOKEN_BIT 0
#define CAPT_STOP_TOKEN_BIT 0
#define CAPT_FREEZE_TOKEN_BIT 0
#define CAPT_RESUME_TOKEN_BIT 0
#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB 20
#define CAPT_PACKET_CH_ID_TOKEN_MSB 27
#define CAPT_PACKET_CH_ID_TOKEN_LSB 26
-#define CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB 29
-#define CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB 21
+#define CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB 29
+#define CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB 21
/* bit definition */
#define CAPT_CMD_IDX CAPT_TOKEN_ID_LSB
#define CAPT_INIT_TOKEN_INIT_IDX 4
#define CAPT_INIT_TOKEN_INIT_BITS 22
-
/* --------------------------------------------------*/
/* MIPI */
/* --------------------------------------------------*/
-#define CAPT_WORD_COUNT_WIDTH 16
-#define CAPT_PKT_CODE_WIDTH 6
-#define CAPT_CHN_NO_WIDTH 2
-#define CAPT_ERROR_INFO_WIDTH 8
+#define CAPT_WORD_COUNT_WIDTH 16
+#define CAPT_PKT_CODE_WIDTH 6
+#define CAPT_CHN_NO_WIDTH 2
+#define CAPT_ERROR_INFO_WIDTH 8
#define LONG_PKTCODE_MAX 63
#define LONG_PKTCODE_MIN 16
#define SHORT_PKTCODE_MAX 15
-
/* --------------------------------------------------*/
/* Packet Info */
/* --------------------------------------------------*/
#define CAPT_LINE_PAYLOAD 4
#define CAPT_GEN_SH_PKT 5
-
/* --------------------------------------------------*/
/* Packet Data Type */
/* --------------------------------------------------*/
#define CAPT_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */
#define CAPT_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */
#define CAPT_RGB444_DATA 32 /* 10 0000 RGB444 */
-#define CAPT_RGB555_DATA 33 /* 10 0001 RGB555 */
-#define CAPT_RGB565_DATA 34 /* 10 0010 RGB565 */
-#define CAPT_RGB666_DATA 35 /* 10 0011 RGB666 */
-#define CAPT_RGB888_DATA 36 /* 10 0100 RGB888 */
-#define CAPT_RAW6_DATA 40 /* 10 1000 RAW6 */
-#define CAPT_RAW7_DATA 41 /* 10 1001 RAW7 */
-#define CAPT_RAW8_DATA 42 /* 10 1010 RAW8 */
-#define CAPT_RAW10_DATA 43 /* 10 1011 RAW10 */
-#define CAPT_RAW12_DATA 44 /* 10 1100 RAW12 */
-#define CAPT_RAW14_DATA 45 /* 10 1101 RAW14 */
-#define CAPT_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
-#define CAPT_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
-#define CAPT_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
-#define CAPT_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
-#define CAPT_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
-#define CAPT_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
-#define CAPT_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
-#define CAPT_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
-#define CAPT_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
-#define CAPT_SOF_DATA 0 /* 00 0000 frame start */
-#define CAPT_EOF_DATA 1 /* 00 0001 frame end */
-#define CAPT_SOL_DATA 2 /* 00 0010 line start */
-#define CAPT_EOL_DATA 3 /* 00 0011 line end */
-#define CAPT_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
-#define CAPT_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
-#define CAPT_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
-#define CAPT_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
-#define CAPT_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
-#define CAPT_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
-#define CAPT_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
-#define CAPT_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
-#define CAPT_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
-#define CAPT_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
+#define CAPT_RGB555_DATA 33 /* 10 0001 RGB555 */
+#define CAPT_RGB565_DATA 34 /* 10 0010 RGB565 */
+#define CAPT_RGB666_DATA 35 /* 10 0011 RGB666 */
+#define CAPT_RGB888_DATA 36 /* 10 0100 RGB888 */
+#define CAPT_RAW6_DATA 40 /* 10 1000 RAW6 */
+#define CAPT_RAW7_DATA 41 /* 10 1001 RAW7 */
+#define CAPT_RAW8_DATA 42 /* 10 1010 RAW8 */
+#define CAPT_RAW10_DATA 43 /* 10 1011 RAW10 */
+#define CAPT_RAW12_DATA 44 /* 10 1100 RAW12 */
+#define CAPT_RAW14_DATA 45 /* 10 1101 RAW14 */
+#define CAPT_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
+#define CAPT_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
+#define CAPT_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
+#define CAPT_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
+#define CAPT_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
+#define CAPT_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
+#define CAPT_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
+#define CAPT_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
+#define CAPT_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
+#define CAPT_SOF_DATA 0 /* 00 0000 frame start */
+#define CAPT_EOF_DATA 1 /* 00 0001 frame end */
+#define CAPT_SOL_DATA 2 /* 00 0010 line start */
+#define CAPT_EOL_DATA 3 /* 00 0011 line end */
+#define CAPT_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
+#define CAPT_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
+#define CAPT_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
+#define CAPT_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
+#define CAPT_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
+#define CAPT_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
+#define CAPT_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
+#define CAPT_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
+#define CAPT_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
+#define CAPT_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
#define CAPT_RESERVED_DATA_TYPE_MIN 56
#define CAPT_RESERVED_DATA_TYPE_MAX 63
#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MIN 19
#define CAPT_RAW_RESERVED_DATA_TYPE_MIN 46
#define CAPT_RAW_RESERVED_DATA_TYPE_MAX 47
-
/* --------------------------------------------------*/
/* Capture Unit State */
/* --------------------------------------------------*/
#define CAPT_FREEZE 5
#define CAPT_RUN 6
-
/* --------------------------------------------------*/
-#endif /* _isp_capture_defs_h */
-
-
-
-
-
+#endif /* _isp_capture_defs_h */
#define _HRT_TIMED_CONTROLLER_REG_ALIGN 4
-#endif /* _timed_controller_defs_h */
+#endif /* _timed_controller_defs_h */
#define hrt_host_type_of_ulong unsigned long
#define hrt_host_type_of_ptr void*
-#define HRT_TYPE_BYTES(cell, type) (HRT_TYPE_BITS(cell, type)/8)
+#define HRT_TYPE_BYTES(cell, type) (HRT_TYPE_BITS(cell, type) / 8)
#define HRT_HOST_TYPE(cell_type) HRTCAT(hrt_host_type_of_, cell_type)
#define HRT_INT_TYPE(type) HRTCAT(hrt_int_type_of_, type)
#define hrt_scalar_store(cell, type, var, data) \
- HRTCAT(hrt_mem_store_,HRT_TYPE_BITS(cell, type))(\
+ HRTCAT(hrt_mem_store_, HRT_TYPE_BITS(cell, type))(\
cell, \
- HRTCAT(HIVE_MEM_,var), \
- HRTCAT(HIVE_ADDR_,var), \
+ HRTCAT(HIVE_MEM_, var), \
+ HRTCAT(HIVE_ADDR_, var), \
(HRT_INT_TYPE(type))(data))
#define hrt_scalar_load(cell, type, var) \
- (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_,HRT_PROC_TYPE(cell),_,type) ( \
+ (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_, HRT_PROC_TYPE(cell), _, type) ( \
cell, \
- HRTCAT(HIVE_MEM_,var), \
- HRTCAT(HIVE_ADDR_,var)))
+ HRTCAT(HIVE_MEM_, var), \
+ HRTCAT(HIVE_ADDR_, var)))
#define hrt_indexed_store(cell, type, array, index, data) \
- HRTCAT(hrt_mem_store_,HRT_TYPE_BITS(cell, type))(\
+ HRTCAT(hrt_mem_store_, HRT_TYPE_BITS(cell, type))(\
cell, \
- HRTCAT(HIVE_MEM_,array), \
- (HRTCAT(HIVE_ADDR_,array))+((index)*HRT_TYPE_BYTES(cell, type)), \
+ HRTCAT(HIVE_MEM_, array), \
+ (HRTCAT(HIVE_ADDR_, array)) + ((index) * HRT_TYPE_BYTES(cell, type)), \
(HRT_INT_TYPE(type))(data))
#define hrt_indexed_load(cell, type, array, index) \
- (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_,HRT_PROC_TYPE(cell),_,type) ( \
- cell, \
- HRTCAT(HIVE_MEM_,array), \
- (HRTCAT(HIVE_ADDR_,array))+((index)*HRT_TYPE_BYTES(cell, type))))
+ (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_, HRT_PROC_TYPE(cell), _, type) ( \
+ cell, \
+ HRTCAT(HIVE_MEM_, array), \
+ (HRTCAT(HIVE_ADDR_, array)) + ((index) * HRT_TYPE_BYTES(cell, type))))
#endif /* _HRT_VAR_H */
#endif
#ifndef _sp_map_h_
#define _sp_map_h_
-
#ifndef _hrt_dummy_use_blob_sp
#define _hrt_dummy_use_blob_sp()
#endif
typedef struct csi_rx_backend_lut_entry_s csi_rx_backend_lut_entry_t;
struct csi_rx_backend_lut_entry_s {
- uint32_t long_packet_entry;
- uint32_t short_packet_entry;
+ u32 long_packet_entry;
+ u32 short_packet_entry;
};
typedef struct csi_rx_backend_cfg_s csi_rx_backend_cfg_t;
struct {
bool comp_enable;
- uint32_t virtual_channel;
- uint32_t data_type;
- uint32_t comp_scheme;
- uint32_t comp_predictor;
- uint32_t comp_bit_idx;
+ u32 virtual_channel;
+ u32 data_type;
+ u32 comp_scheme;
+ u32 comp_predictor;
+ u32 comp_bit_idx;
} csi_mipi_cfg;
};
typedef struct csi_rx_frontend_cfg_s csi_rx_frontend_cfg_t;
struct csi_rx_frontend_cfg_s {
- uint32_t active_lanes;
+ u32 active_lanes;
};
-extern const uint32_t N_SHORT_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID];
-extern const uint32_t N_LONG_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID];
-extern const uint32_t N_CSI_RX_FE_CTRL_DLANES[N_CSI_RX_FRONTEND_ID];
+extern const u32 N_SHORT_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID];
+extern const u32 N_LONG_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID];
+extern const u32 N_CSI_RX_FE_CTRL_DLANES[N_CSI_RX_FRONTEND_ID];
/* sid_width for CSI_RX_BACKEND<N>_ID */
-extern const uint32_t N_CSI_RX_BE_SID_WIDTH[N_CSI_RX_BACKEND_ID];
+extern const u32 N_CSI_RX_BE_SID_WIDTH[N_CSI_RX_BACKEND_ID];
#endif /* __CSI_RX_GLOBAL_H_INCLUDED__ */
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_iterator() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.iterator.size;
offset = binary->info->mem_offsets.offsets.config->dmem.iterator.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_copy_output() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.copy_output.size;
offset = binary->info->mem_offsets.offsets.config->dmem.copy_output.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_crop() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.crop.size;
offset = binary->info->mem_offsets.offsets.config->dmem.crop.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_fpn() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.fpn.size;
offset = binary->info->mem_offsets.offsets.config->dmem.fpn.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_dvs() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.dvs.size;
offset = binary->info->mem_offsets.offsets.config->dmem.dvs.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_qplane() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.qplane.size;
offset = binary->info->mem_offsets.offsets.config->dmem.qplane.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output0() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output0.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output0.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output1() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output1.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output1.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_sc() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.sc.size;
offset = binary->info->mem_offsets.offsets.config->dmem.sc.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_raw() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.raw.size;
offset = binary->info->mem_offsets.offsets.config->dmem.raw.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_tnr() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.tnr.size;
offset = binary->info->mem_offsets.offsets.config->dmem.tnr.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_ref() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.ref.size;
offset = binary->info->mem_offsets.offsets.config->dmem.ref.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.vf.size;
offset = binary->info->mem_offsets.offsets.config->dmem.vf.offset;
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() leave:\n");
}
-
static void
ia_css_process_aa(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.aa.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.aa.size;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset;
if (size) {
struct sh_css_isp_aa_params *t = (struct sh_css_isp_aa_params *)
static void
ia_css_process_anr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.anr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.anr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr() leave:\n");
}
-
}
}
static void
ia_css_process_anr2(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr2() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr2() leave:\n");
}
-
}
}
static void
ia_css_process_bh(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bh.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.bh.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bh.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.bh.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() leave:\n");
}
-
}
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->hmem0.bh.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->hmem0.bh.size;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() leave:\n");
}
-
}
}
static void
ia_css_process_cnr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_cnr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_cnr() leave:\n");
}
-
}
}
static void
ia_css_process_crop(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.crop.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.crop.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.crop.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.crop.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_crop() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_crop() leave:\n");
}
-
}
}
static void
ia_css_process_csc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.csc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.csc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.csc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.csc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_csc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_csc() leave:\n");
}
-
}
}
static void
ia_css_process_dp(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.dp.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.dp.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.dp.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.dp.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_dp() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_dp() leave:\n");
}
-
}
}
static void
ia_css_process_bnr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bnr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bnr() leave:\n");
}
-
}
}
static void
ia_css_process_de(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.de.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.de.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.de.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.de.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_de() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_de() leave:\n");
}
-
}
}
static void
ia_css_process_ecd(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ecd() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ecd() leave:\n");
}
-
}
}
static void
ia_css_process_formats(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.formats.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.formats.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.formats.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.formats.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_formats() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_formats() leave:\n");
}
-
}
}
static void
ia_css_process_fpn(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fpn() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fpn() leave:\n");
}
-
}
}
static void
ia_css_process_gc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.gc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.gc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.gc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.gc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() leave:\n");
}
-
}
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() leave:\n");
}
-
}
}
static void
ia_css_process_ce(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ce.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.ce.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ce.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.ce.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ce() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ce() leave:\n");
}
-
}
}
static void
ia_css_process_yuv2rgb(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yuv2rgb() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yuv2rgb() leave:\n");
}
-
}
}
static void
ia_css_process_rgb2yuv(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_rgb2yuv() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_rgb2yuv() leave:\n");
}
-
}
}
static void
ia_css_process_r_gamma(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_r_gamma() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_r_gamma() leave:\n");
}
-
}
}
static void
ia_css_process_g_gamma(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_g_gamma() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_g_gamma() leave:\n");
}
-
}
}
static void
ia_css_process_b_gamma(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_b_gamma() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_b_gamma() leave:\n");
}
-
}
}
static void
ia_css_process_uds(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.uds.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.uds.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.uds.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.uds.offset;
if (size) {
struct sh_css_sp_uds_params *p;
+
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_uds() enter:\n");
p = (struct sh_css_sp_uds_params *)
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_uds() leave:\n");
}
-
}
}
static void
ia_css_process_raa(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.raa.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.raa.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.raa.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.raa.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_raa() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_raa() leave:\n");
}
-
}
}
static void
ia_css_process_s3a(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_s3a() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_s3a() leave:\n");
}
-
}
}
static void
ia_css_process_ob(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ob.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.ob.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ob.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.ob.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() leave:\n");
}
-
}
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.ob.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.ob.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.ob.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.ob.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() leave:\n");
}
-
}
}
static void
ia_css_process_output(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.output.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.output.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.output.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.output.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_output() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_output() leave:\n");
}
-
}
}
static void
ia_css_process_sc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.sc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.sc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sc() leave:\n");
}
-
}
}
static void
ia_css_process_bds(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bds.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.bds.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bds.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.bds.offset;
if (size) {
struct sh_css_isp_bds_params *p;
+
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bds() enter:\n");
p = (struct sh_css_isp_bds_params *)
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bds() leave:\n");
}
-
}
}
static void
ia_css_process_tnr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_tnr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_tnr() leave:\n");
}
-
}
}
static void
ia_css_process_macc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.macc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.macc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.macc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.macc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_macc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_macc() leave:\n");
}
-
}
}
static void
ia_css_process_sdis_horicoef(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horicoef() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horicoef() leave:\n");
}
-
}
}
static void
ia_css_process_sdis_vertcoef(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertcoef() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertcoef() leave:\n");
}
-
}
}
static void
ia_css_process_sdis_horiproj(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horiproj() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horiproj() leave:\n");
}
-
}
}
static void
ia_css_process_sdis_vertproj(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertproj() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertproj() leave:\n");
}
-
}
}
static void
ia_css_process_sdis2_horicoef(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horicoef() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horicoef() leave:\n");
}
-
}
}
static void
ia_css_process_sdis2_vertcoef(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertcoef() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertcoef() leave:\n");
}
-
}
}
static void
ia_css_process_sdis2_horiproj(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horiproj() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horiproj() leave:\n");
}
-
}
}
static void
ia_css_process_sdis2_vertproj(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertproj() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertproj() leave:\n");
}
-
}
}
static void
ia_css_process_wb(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.wb.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.wb.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.wb.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.wb.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_wb() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_wb() leave:\n");
}
-
}
}
static void
ia_css_process_nr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.nr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.nr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.nr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.nr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_nr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_nr() leave:\n");
}
-
}
}
static void
ia_css_process_yee(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.yee.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.yee.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.yee.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.yee.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yee() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yee() leave:\n");
}
-
}
}
static void
ia_css_process_ynr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ynr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ynr() leave:\n");
}
-
}
}
static void
ia_css_process_fc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.fc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.fc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.fc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.fc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fc() leave:\n");
}
-
}
}
static void
ia_css_process_ctc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() leave:\n");
}
-
}
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() leave:\n");
}
-
}
}
static void
ia_css_process_xnr_table(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr_table() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr_table() leave:\n");
}
-
}
}
static void
ia_css_process_xnr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr() leave:\n");
}
-
}
}
static void
ia_css_process_xnr3(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() leave:\n");
}
-
}
#ifdef ISP2401
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() leave:\n");
}
-
}
#endif
}
/* Code generated by genparam/gencode.c:gen_param_process_table() */
-void (* ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
- unsigned pipe_id,
+void (*ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params) = {
ia_css_process_aa,
static void
ia_css_get_dp_config(const struct ia_css_isp_parameters *params,
struct ia_css_dp_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_dp_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_dp_config() enter: config=%p\n",
+ config);
*config = params->dp_config;
ia_css_set_dp_config(struct ia_css_isp_parameters *params,
const struct ia_css_dp_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_dp_config() enter:\n");
ia_css_dp_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dp_config = *config;
params->config_changed[IA_CSS_DP_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_dp_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_dp_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_wb_config(const struct ia_css_isp_parameters *params,
struct ia_css_wb_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_wb_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_wb_config() enter: config=%p\n",
+ config);
*config = params->wb_config;
ia_css_set_wb_config(struct ia_css_isp_parameters *params,
const struct ia_css_wb_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_wb_config() enter:\n");
ia_css_wb_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->wb_config = *config;
params->config_changed[IA_CSS_WB_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_wb_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_wb_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_tnr_config(const struct ia_css_isp_parameters *params,
struct ia_css_tnr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_tnr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_tnr_config() enter: config=%p\n",
+ config);
*config = params->tnr_config;
ia_css_set_tnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_tnr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_tnr_config() enter:\n");
ia_css_tnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->tnr_config = *config;
params->config_changed[IA_CSS_TNR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_tnr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_tnr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_ob_config(const struct ia_css_isp_parameters *params,
struct ia_css_ob_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ob_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ob_config() enter: config=%p\n",
+ config);
*config = params->ob_config;
ia_css_set_ob_config(struct ia_css_isp_parameters *params,
const struct ia_css_ob_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ob_config() enter:\n");
ia_css_ob_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->ob_config = *config;
params->config_changed[IA_CSS_OB_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ob_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ob_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_de_config(const struct ia_css_isp_parameters *params,
struct ia_css_de_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_de_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_de_config() enter: config=%p\n",
+ config);
*config = params->de_config;
ia_css_set_de_config(struct ia_css_isp_parameters *params,
const struct ia_css_de_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_de_config() enter:\n");
ia_css_de_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->de_config = *config;
params->config_changed[IA_CSS_DE_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_de_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_de_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_anr_config(const struct ia_css_isp_parameters *params,
struct ia_css_anr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr_config() enter: config=%p\n",
+ config);
*config = params->anr_config;
ia_css_set_anr_config(struct ia_css_isp_parameters *params,
const struct ia_css_anr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_anr_config() enter:\n");
ia_css_anr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->anr_config = *config;
params->config_changed[IA_CSS_ANR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_anr2_config(const struct ia_css_isp_parameters *params,
struct ia_css_anr_thres *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr2_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr2_config() enter: config=%p\n",
+ config);
*config = params->anr_thres;
ia_css_set_anr2_config(struct ia_css_isp_parameters *params,
const struct ia_css_anr_thres *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_anr2_config() enter:\n");
ia_css_anr2_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->anr_thres = *config;
params->config_changed[IA_CSS_ANR2_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr2_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr2_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_ce_config(const struct ia_css_isp_parameters *params,
struct ia_css_ce_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ce_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ce_config() enter: config=%p\n",
+ config);
*config = params->ce_config;
ia_css_set_ce_config(struct ia_css_isp_parameters *params,
const struct ia_css_ce_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ce_config() enter:\n");
ia_css_ce_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->ce_config = *config;
params->config_changed[IA_CSS_CE_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ce_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ce_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_ecd_config(const struct ia_css_isp_parameters *params,
struct ia_css_ecd_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ecd_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ecd_config() enter: config=%p\n",
+ config);
*config = params->ecd_config;
ia_css_set_ecd_config(struct ia_css_isp_parameters *params,
const struct ia_css_ecd_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ecd_config() enter:\n");
ia_css_ecd_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->ecd_config = *config;
params->config_changed[IA_CSS_ECD_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ecd_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ecd_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_ynr_config(const struct ia_css_isp_parameters *params,
struct ia_css_ynr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ynr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ynr_config() enter: config=%p\n",
+ config);
*config = params->ynr_config;
ia_css_set_ynr_config(struct ia_css_isp_parameters *params,
const struct ia_css_ynr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ynr_config() enter:\n");
ia_css_ynr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->ynr_config = *config;
params->config_changed[IA_CSS_YNR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ynr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ynr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_fc_config(const struct ia_css_isp_parameters *params,
struct ia_css_fc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_fc_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_fc_config() enter: config=%p\n",
+ config);
*config = params->fc_config;
ia_css_set_fc_config(struct ia_css_isp_parameters *params,
const struct ia_css_fc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_fc_config() enter:\n");
ia_css_fc_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->fc_config = *config;
params->config_changed[IA_CSS_FC_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_fc_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_fc_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_cnr_config(const struct ia_css_isp_parameters *params,
struct ia_css_cnr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_cnr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_cnr_config() enter: config=%p\n",
+ config);
*config = params->cnr_config;
ia_css_set_cnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_cnr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_cnr_config() enter:\n");
ia_css_cnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->cnr_config = *config;
params->config_changed[IA_CSS_CNR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_cnr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_cnr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_macc_config(const struct ia_css_isp_parameters *params,
struct ia_css_macc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_macc_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_macc_config() enter: config=%p\n",
+ config);
*config = params->macc_config;
ia_css_set_macc_config(struct ia_css_isp_parameters *params,
const struct ia_css_macc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_macc_config() enter:\n");
ia_css_macc_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->macc_config = *config;
params->config_changed[IA_CSS_MACC_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_macc_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_macc_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_ctc_config(const struct ia_css_isp_parameters *params,
struct ia_css_ctc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ctc_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ctc_config() enter: config=%p\n",
+ config);
*config = params->ctc_config;
ia_css_set_ctc_config(struct ia_css_isp_parameters *params,
const struct ia_css_ctc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ctc_config() enter:\n");
ia_css_ctc_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->ctc_config = *config;
params->config_changed[IA_CSS_CTC_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ctc_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ctc_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_aa_config(const struct ia_css_isp_parameters *params,
struct ia_css_aa_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_aa_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_aa_config() enter: config=%p\n",
+ config);
*config = params->aa_config;
ia_css_set_aa_config(struct ia_css_isp_parameters *params,
const struct ia_css_aa_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_aa_config() enter:\n");
params->aa_config = *config;
params->config_changed[IA_CSS_AA_ID] = true;
params->config_changed[IA_CSS_AA_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_aa_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_aa_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_yuv2rgb_config(const struct ia_css_isp_parameters *params,
struct ia_css_cc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_yuv2rgb_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_yuv2rgb_config() enter: config=%p\n",
+ config);
*config = params->yuv2rgb_cc_config;
ia_css_set_yuv2rgb_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_yuv2rgb_config() enter:\n");
ia_css_yuv2rgb_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->yuv2rgb_cc_config = *config;
params->config_changed[IA_CSS_YUV2RGB_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_yuv2rgb_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_yuv2rgb_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_rgb2yuv_config(const struct ia_css_isp_parameters *params,
struct ia_css_cc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_rgb2yuv_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_rgb2yuv_config() enter: config=%p\n",
+ config);
*config = params->rgb2yuv_cc_config;
ia_css_set_rgb2yuv_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_rgb2yuv_config() enter:\n");
ia_css_rgb2yuv_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->rgb2yuv_cc_config = *config;
params->config_changed[IA_CSS_RGB2YUV_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_rgb2yuv_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_rgb2yuv_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_csc_config(const struct ia_css_isp_parameters *params,
struct ia_css_cc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_csc_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_csc_config() enter: config=%p\n",
+ config);
*config = params->cc_config;
ia_css_set_csc_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_csc_config() enter:\n");
ia_css_csc_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->cc_config = *config;
params->config_changed[IA_CSS_CSC_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_csc_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_csc_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_nr_config(const struct ia_css_isp_parameters *params,
struct ia_css_nr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_nr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_nr_config() enter: config=%p\n",
+ config);
*config = params->nr_config;
ia_css_set_nr_config(struct ia_css_isp_parameters *params,
const struct ia_css_nr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_nr_config() enter:\n");
ia_css_nr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->nr_config = *config;
params->config_changed[IA_CSS_NR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_nr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_nr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_gc_config(const struct ia_css_isp_parameters *params,
struct ia_css_gc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_gc_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_gc_config() enter: config=%p\n",
+ config);
*config = params->gc_config;
ia_css_set_gc_config(struct ia_css_isp_parameters *params,
const struct ia_css_gc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_gc_config() enter:\n");
ia_css_gc_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->gc_config = *config;
params->config_changed[IA_CSS_GC_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_gc_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_gc_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis_horicoef_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horicoef_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horicoef_config() enter: config=%p\n",
+ config);
*config = params->dvs_coefs;
ia_css_set_sdis_horicoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_horicoef_config() enter:\n");
ia_css_sdis_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs_coefs = *config;
params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horicoef_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horicoef_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis_vertcoef_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertcoef_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertcoef_config() enter: config=%p\n",
+ config);
*config = params->dvs_coefs;
ia_css_set_sdis_vertcoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_vertcoef_config() enter:\n");
ia_css_sdis_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs_coefs = *config;
params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertcoef_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertcoef_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis_horiproj_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horiproj_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horiproj_config() enter: config=%p\n",
+ config);
*config = params->dvs_coefs;
ia_css_set_sdis_horiproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_horiproj_config() enter:\n");
ia_css_sdis_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs_coefs = *config;
params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horiproj_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horiproj_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis_vertproj_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertproj_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertproj_config() enter: config=%p\n",
+ config);
*config = params->dvs_coefs;
ia_css_set_sdis_vertproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_vertproj_config() enter:\n");
ia_css_sdis_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs_coefs = *config;
params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertproj_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertproj_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis2_horicoef_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs2_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horicoef_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horicoef_config() enter: config=%p\n",
+ config);
*config = params->dvs2_coefs;
ia_css_set_sdis2_horicoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_horicoef_config() enter:\n");
ia_css_sdis2_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs2_coefs = *config;
params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horicoef_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horicoef_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis2_vertcoef_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs2_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertcoef_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertcoef_config() enter: config=%p\n",
+ config);
*config = params->dvs2_coefs;
ia_css_set_sdis2_vertcoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_vertcoef_config() enter:\n");
ia_css_sdis2_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs2_coefs = *config;
params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertcoef_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertcoef_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis2_horiproj_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs2_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horiproj_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horiproj_config() enter: config=%p\n",
+ config);
*config = params->dvs2_coefs;
ia_css_set_sdis2_horiproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_horiproj_config() enter:\n");
ia_css_sdis2_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs2_coefs = *config;
params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horiproj_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horiproj_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis2_vertproj_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs2_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertproj_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertproj_config() enter: config=%p\n",
+ config);
*config = params->dvs2_coefs;
ia_css_set_sdis2_vertproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_vertproj_config() enter:\n");
ia_css_sdis2_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs2_coefs = *config;
params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertproj_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertproj_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_r_gamma_config(const struct ia_css_isp_parameters *params,
struct ia_css_rgb_gamma_table *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_r_gamma_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_r_gamma_config() enter: config=%p\n",
+ config);
*config = params->r_gamma_table;
ia_css_set_r_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_r_gamma_config() enter:\n");
ia_css_r_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->r_gamma_table = *config;
params->config_changed[IA_CSS_R_GAMMA_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_r_gamma_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_r_gamma_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_g_gamma_config(const struct ia_css_isp_parameters *params,
struct ia_css_rgb_gamma_table *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_g_gamma_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_g_gamma_config() enter: config=%p\n",
+ config);
*config = params->g_gamma_table;
ia_css_set_g_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_g_gamma_config() enter:\n");
ia_css_g_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->g_gamma_table = *config;
params->config_changed[IA_CSS_G_GAMMA_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_g_gamma_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_g_gamma_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_b_gamma_config(const struct ia_css_isp_parameters *params,
struct ia_css_rgb_gamma_table *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_b_gamma_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_b_gamma_config() enter: config=%p\n",
+ config);
*config = params->b_gamma_table;
ia_css_set_b_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_b_gamma_config() enter:\n");
ia_css_b_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->b_gamma_table = *config;
params->config_changed[IA_CSS_B_GAMMA_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_b_gamma_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_b_gamma_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_xnr_table_config(const struct ia_css_isp_parameters *params,
struct ia_css_xnr_table *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_table_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_table_config() enter: config=%p\n",
+ config);
*config = params->xnr_table;
ia_css_set_xnr_table_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr_table *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr_table_config() enter:\n");
ia_css_xnr_table_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->xnr_table = *config;
params->config_changed[IA_CSS_XNR_TABLE_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_table_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_table_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_formats_config(const struct ia_css_isp_parameters *params,
struct ia_css_formats_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_formats_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_formats_config() enter: config=%p\n",
+ config);
*config = params->formats_config;
ia_css_set_formats_config(struct ia_css_isp_parameters *params,
const struct ia_css_formats_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_formats_config() enter:\n");
ia_css_formats_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->formats_config = *config;
params->config_changed[IA_CSS_FORMATS_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_formats_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_formats_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_xnr_config(const struct ia_css_isp_parameters *params,
struct ia_css_xnr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_config() enter: config=%p\n",
+ config);
*config = params->xnr_config;
ia_css_set_xnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr_config() enter:\n");
ia_css_xnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->xnr_config = *config;
params->config_changed[IA_CSS_XNR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_xnr3_config(const struct ia_css_isp_parameters *params,
struct ia_css_xnr3_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr3_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr3_config() enter: config=%p\n",
+ config);
*config = params->xnr3_config;
ia_css_set_xnr3_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr3_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr3_config() enter:\n");
ia_css_xnr3_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->xnr3_config = *config;
params->config_changed[IA_CSS_XNR3_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr3_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr3_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_s3a_config(const struct ia_css_isp_parameters *params,
struct ia_css_3a_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_s3a_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_s3a_config() enter: config=%p\n",
+ config);
*config = params->s3a_config;
ia_css_set_s3a_config(struct ia_css_isp_parameters *params,
const struct ia_css_3a_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_s3a_config() enter:\n");
ia_css_s3a_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->s3a_config = *config;
params->config_changed[IA_CSS_S3A_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_s3a_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_s3a_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_output_config(const struct ia_css_isp_parameters *params,
struct ia_css_output_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_output_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_output_config() enter: config=%p\n",
+ config);
*config = params->output_config;
ia_css_set_output_config(struct ia_css_isp_parameters *params,
const struct ia_css_output_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_output_config() enter:\n");
ia_css_output_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->output_config = *config;
params->config_changed[IA_CSS_OUTPUT_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_output_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_output_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_global_access_function() */
ia_css_set_s3a_config(params, config->s3a_config);
ia_css_set_output_config(params, config->output_config);
}
-
struct ia_css_pipeline_stage; /* forward declaration */
-extern void (* ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
- unsigned pipe_id,
+extern void (*ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.aa.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.aa.size;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset;
if (size)
memset(&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], 0, size);
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.cnr.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset;
if (size) {
ia_css_init_cnr_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset;
if (size) {
ia_css_init_cnr2_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.dp.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.dp.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset;
if (size) {
ia_css_init_dp_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.de.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.de.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.de.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.de.offset;
if (size) {
ia_css_init_de_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->dmem.tnr.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->dmem.tnr.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->dmem.tnr.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->dmem.tnr.offset;
if (size) {
ia_css_init_tnr_state((struct sh_css_isp_tnr_dmem_state *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->dmem.ref.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->dmem.ref.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->dmem.ref.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->dmem.ref.offset;
if (size) {
ia_css_init_ref_state((struct sh_css_isp_ref_dmem_state *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.ynr.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.ynr.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.ynr.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.ynr.offset;
if (size) {
ia_css_init_ynr_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() leave:\n");
}
ia_css_initialize_ref_state,
ia_css_initialize_ynr_state,
};
-
* more details.
*/
-
#include "system_global.h"
-const uint32_t N_SHORT_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID] = {
+const u32 N_SHORT_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID] = {
4, /* 4 entries at CSI_RX_BACKEND0_ID*/
4, /* 4 entries at CSI_RX_BACKEND1_ID*/
4 /* 4 entries at CSI_RX_BACKEND2_ID*/
};
-const uint32_t N_LONG_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID] = {
+const u32 N_LONG_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID] = {
8, /* 8 entries at CSI_RX_BACKEND0_ID*/
4, /* 4 entries at CSI_RX_BACKEND1_ID*/
4 /* 4 entries at CSI_RX_BACKEND2_ID*/
};
-const uint32_t N_CSI_RX_FE_CTRL_DLANES[N_CSI_RX_FRONTEND_ID] = {
+const u32 N_CSI_RX_FE_CTRL_DLANES[N_CSI_RX_FRONTEND_ID] = {
N_CSI_RX_DLANE_ID, /* 4 dlanes for CSI_RX_FR0NTEND0_ID */
N_CSI_RX_DLANE_ID, /* 4 dlanes for CSI_RX_FR0NTEND1_ID */
N_CSI_RX_DLANE_ID /* 4 dlanes for CSI_RX_FR0NTEND2_ID */
};
/* sid_width for CSI_RX_BACKEND<N>_ID */
-const uint32_t N_CSI_RX_BE_SID_WIDTH[N_CSI_RX_BACKEND_ID] = {
+const u32 N_CSI_RX_BE_SID_WIDTH[N_CSI_RX_BACKEND_ID] = {
3,
2,
2
#define __CSI_RX_LOCAL_H_INCLUDED__
#include "csi_rx_global.h"
-#define N_CSI_RX_BE_MIPI_COMP_FMT_REG 4
+#define N_CSI_RX_BE_MIPI_COMP_FMT_REG 4
#define N_CSI_RX_BE_MIPI_CUSTOM_PEC 12
#define N_CSI_RX_BE_SHORT_PKT_LUT 4
#define N_CSI_RX_BE_LONG_PKT_LUT 8
/*mipi_backend_custom_mode_pixel_extraction_config*/
typedef struct csi_rx_be_ctrl_pec_s csi_rx_be_ctrl_pec_t;
-
struct csi_rx_fe_ctrl_lane_s {
hrt_data termen;
hrt_data settle;
};
+
struct csi_rx_fe_ctrl_state_s {
- hrt_data enable;
- hrt_data nof_enable_lanes;
- hrt_data error_handling;
- hrt_data status;
- hrt_data status_dlane_hs;
- hrt_data status_dlane_lp;
- csi_rx_fe_ctrl_lane_t clane;
- csi_rx_fe_ctrl_lane_t dlane[N_CSI_RX_DLANE_ID];
+ hrt_data enable;
+ hrt_data nof_enable_lanes;
+ hrt_data error_handling;
+ hrt_data status;
+ hrt_data status_dlane_hs;
+ hrt_data status_dlane_lp;
+ csi_rx_fe_ctrl_lane_t clane;
+ csi_rx_fe_ctrl_lane_t dlane[N_CSI_RX_DLANE_ID];
};
+
struct csi_rx_be_ctrl_state_s {
- hrt_data enable;
- hrt_data status;
- hrt_data comp_format_reg[N_CSI_RX_BE_MIPI_COMP_FMT_REG];
- hrt_data raw16;
- hrt_data raw18;
- hrt_data force_raw8;
- hrt_data irq_status;
- hrt_data custom_mode_enable;
- hrt_data custom_mode_data_state;
- hrt_data pec[N_CSI_RX_BE_MIPI_CUSTOM_PEC];
- hrt_data custom_mode_valid_eop_config;
- hrt_data global_lut_disregard_reg;
- hrt_data packet_status_stall;
- hrt_data short_packet_lut_entry[N_CSI_RX_BE_SHORT_PKT_LUT];
- hrt_data long_packet_lut_entry[N_CSI_RX_BE_LONG_PKT_LUT];
+ hrt_data enable;
+ hrt_data status;
+ hrt_data comp_format_reg[N_CSI_RX_BE_MIPI_COMP_FMT_REG];
+ hrt_data raw16;
+ hrt_data raw18;
+ hrt_data force_raw8;
+ hrt_data irq_status;
+ hrt_data custom_mode_enable;
+ hrt_data custom_mode_data_state;
+ hrt_data pec[N_CSI_RX_BE_MIPI_CUSTOM_PEC];
+ hrt_data custom_mode_valid_eop_config;
+ hrt_data global_lut_disregard_reg;
+ hrt_data packet_status_stall;
+ hrt_data short_packet_lut_entry[N_CSI_RX_BE_SHORT_PKT_LUT];
+ hrt_data long_packet_lut_entry[N_CSI_RX_BE_LONG_PKT_LUT];
};
#endif /* __CSI_RX_LOCAL_H_INCLUDED__ */
#include "assert_support.h" /* assert */
#include "print_support.h" /* print */
-
/*****************************************************
*
* Native command interface (NCI).
const csi_rx_frontend_ID_t ID,
csi_rx_fe_ctrl_state_t *state)
{
- uint32_t i;
+ u32 i;
state->enable =
csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ENABLE_REG_IDX);
csi_rx_fe_ctrl_get_dlane_state(
ID,
i,
- &(state->dlane[i]));
+ &state->dlane[i]);
}
}
*/
static inline void csi_rx_fe_ctrl_get_dlane_state(
const csi_rx_frontend_ID_t ID,
- const uint32_t lane,
+ const u32 lane,
csi_rx_fe_ctrl_lane_t *dlane_state)
{
-
dlane_state->termen =
csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane));
dlane_state->settle =
csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane));
-
}
+
/**
* @brief dump the csi rx fe state.
* Refer to "csi_rx_public.h" for details.
const csi_rx_frontend_ID_t ID,
csi_rx_fe_ctrl_state_t *state)
{
- uint32_t i;
+ u32 i;
- ia_css_print("CSI RX FE STATE Controller %d Enable state 0x%x \n", ID, state->enable);
- ia_css_print("CSI RX FE STATE Controller %d No Of enable lanes 0x%x \n", ID, state->nof_enable_lanes);
- ia_css_print("CSI RX FE STATE Controller %d Error handling 0x%x \n", ID, state->error_handling);
- ia_css_print("CSI RX FE STATE Controller %d Status 0x%x \n", ID, state->status);
- ia_css_print("CSI RX FE STATE Controller %d Status Dlane HS 0x%x \n", ID, state->status_dlane_hs);
- ia_css_print("CSI RX FE STATE Controller %d Status Dlane LP 0x%x \n", ID, state->status_dlane_lp);
- ia_css_print("CSI RX FE STATE Controller %d Status term enable LP 0x%x \n", ID, state->clane.termen);
- ia_css_print("CSI RX FE STATE Controller %d Status term settle LP 0x%x \n", ID, state->clane.settle);
+ ia_css_print("CSI RX FE STATE Controller %d Enable state 0x%x\n", ID, state->enable);
+ ia_css_print("CSI RX FE STATE Controller %d No Of enable lanes 0x%x\n", ID, state->nof_enable_lanes);
+ ia_css_print("CSI RX FE STATE Controller %d Error handling 0x%x\n", ID, state->error_handling);
+ ia_css_print("CSI RX FE STATE Controller %d Status 0x%x\n", ID, state->status);
+ ia_css_print("CSI RX FE STATE Controller %d Status Dlane HS 0x%x\n", ID, state->status_dlane_hs);
+ ia_css_print("CSI RX FE STATE Controller %d Status Dlane LP 0x%x\n", ID, state->status_dlane_lp);
+ ia_css_print("CSI RX FE STATE Controller %d Status term enable LP 0x%x\n", ID, state->clane.termen);
+ ia_css_print("CSI RX FE STATE Controller %d Status term settle LP 0x%x\n", ID, state->clane.settle);
/*
* Get the values of the register-set per
* dlane.
*/
for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) {
- ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d termen 0x%x \n", ID, i, state->dlane[i].termen);
- ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d settle 0x%x \n", ID, i, state->dlane[i].settle);
+ ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d termen 0x%x\n", ID, i, state->dlane[i].termen);
+ ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d settle 0x%x\n", ID, i, state->dlane[i].settle);
}
}
const csi_rx_backend_ID_t ID,
csi_rx_be_ctrl_state_t *state)
{
- uint32_t i;
+ u32 i;
state->enable =
csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_ENABLE_REG_IDX);
state->status =
csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_STATUS_REG_IDX);
- for(i = 0; i <N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) {
+ for (i = 0; i < N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) {
state->comp_format_reg[i] =
- csi_rx_be_ctrl_reg_load(ID,
- _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX+i);
+ csi_rx_be_ctrl_reg_load(ID,
+ _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX + i);
}
state->raw16 =
state->custom_mode_data_state =
csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX);
- for(i = 0; i <N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) {
- state->pec[i] =
+ for (i = 0; i < N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) {
+ state->pec[i] =
csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX + i);
}
state->custom_mode_valid_eop_config =
const csi_rx_backend_ID_t ID,
csi_rx_be_ctrl_state_t *state)
{
- uint32_t i;
+ u32 i;
- ia_css_print("CSI RX BE STATE Controller %d Enable 0x%x \n", ID, state->enable);
- ia_css_print("CSI RX BE STATE Controller %d Status 0x%x \n", ID, state->status);
+ ia_css_print("CSI RX BE STATE Controller %d Enable 0x%x\n", ID, state->enable);
+ ia_css_print("CSI RX BE STATE Controller %d Status 0x%x\n", ID, state->status);
- for(i = 0; i <N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) {
- ia_css_print("CSI RX BE STATE Controller %d comp format reg vc%d value 0x%x \n", ID, i, state->status);
+ for (i = 0; i < N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) {
+ ia_css_print("CSI RX BE STATE Controller %d comp format reg vc%d value 0x%x\n", ID, i, state->status);
}
- ia_css_print("CSI RX BE STATE Controller %d RAW16 0x%x \n", ID, state->raw16);
- ia_css_print("CSI RX BE STATE Controller %d RAW18 0x%x \n", ID, state->raw18);
- ia_css_print("CSI RX BE STATE Controller %d Force RAW8 0x%x \n", ID, state->force_raw8);
- ia_css_print("CSI RX BE STATE Controller %d IRQ state 0x%x \n", ID, state->irq_status);
+ ia_css_print("CSI RX BE STATE Controller %d RAW16 0x%x\n", ID, state->raw16);
+ ia_css_print("CSI RX BE STATE Controller %d RAW18 0x%x\n", ID, state->raw18);
+ ia_css_print("CSI RX BE STATE Controller %d Force RAW8 0x%x\n", ID, state->force_raw8);
+ ia_css_print("CSI RX BE STATE Controller %d IRQ state 0x%x\n", ID, state->irq_status);
#if 0 /* ToDo:Getting device access error for this register */
- for(i = 0; i <N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) {
- ia_css_print("CSI RX BE STATE Controller %d PEC ID %d custom pec 0x%x \n", ID, i, state->pec[i]);
+ for (i = 0; i < N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) {
+ ia_css_print("CSI RX BE STATE Controller %d PEC ID %d custom pec 0x%x\n", ID, i, state->pec[i]);
}
#endif
- ia_css_print("CSI RX BE STATE Controller %d Global LUT disregard reg 0x%x \n", ID, state->global_lut_disregard_reg);
- ia_css_print("CSI RX BE STATE Controller %d packet stall reg 0x%x \n", ID, state->packet_status_stall);
+ ia_css_print("CSI RX BE STATE Controller %d Global LUT disregard reg 0x%x\n", ID, state->global_lut_disregard_reg);
+ ia_css_print("CSI RX BE STATE Controller %d packet stall reg 0x%x\n", ID, state->packet_status_stall);
/*
* Get the values of the register-set per
* lut.
*/
for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) {
- ia_css_print("CSI RX BE STATE Controller ID %d Short packat entry %d shart packet lut id 0x%x \n", ID, i, state->short_packet_lut_entry[i]);
+ ia_css_print("CSI RX BE STATE Controller ID %d Short packat entry %d shart packet lut id 0x%x\n", ID, i, state->short_packet_lut_entry[i]);
}
for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) {
- ia_css_print("CSI RX BE STATE Controller ID %d Long packat entry %d Long packet lut id 0x%x \n", ID, i, state->long_packet_lut_entry[i]);
+ ia_css_print("CSI RX BE STATE Controller ID %d Long packat entry %d Long packet lut id 0x%x\n", ID, i, state->long_packet_lut_entry[i]);
}
}
+
/* end of NCI */
/*****************************************************
*
{
assert(ID < N_CSI_RX_FRONTEND_ID);
assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1);
- return ia_css_device_load_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg*sizeof(hrt_data));
+ return ia_css_device_load_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof(hrt_data));
}
-
/**
* @brief Store a value to the register.
* Refer to "ibuf_ctrl_public.h" for details.
assert(ID < N_CSI_RX_FRONTEND_ID);
assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1);
- ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
+ ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
}
+
/**
* @brief Load the register value.
* Refer to "csi_rx_public.h" for details.
{
assert(ID < N_CSI_RX_BACKEND_ID);
assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1);
- return ia_css_device_load_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg*sizeof(hrt_data));
+ return ia_css_device_load_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg * sizeof(hrt_data));
}
-
/**
* @brief Store a value to the register.
* Refer to "ibuf_ctrl_public.h" for details.
assert(ID < N_CSI_RX_BACKEND_ID);
assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1);
- ia_css_device_store_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
+ ia_css_device_store_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
}
+
/* end of DLI */
#endif /* __CSI_RX_PRIVATE_H_INCLUDED__ */
#include <type_support.h>
#include "system_global.h"
-const uint32_t N_IBUF_CTRL_PROCS[N_IBUF_CTRL_ID] = {
+const u32 N_IBUF_CTRL_PROCS[N_IBUF_CTRL_ID] = {
8, /* IBUF_CTRL0_ID supports at most 8 processes */
4, /* IBUF_CTRL1_ID supports at most 4 processes */
4 /* IBUF_CTRL2_ID supports at most 4 processes */
#include "assert_support.h" /* assert */
#include "print_support.h" /* print */
-
/*****************************************************
*
* Native command interface (NCI).
const ibuf_ctrl_ID_t ID,
ibuf_ctrl_state_t *state)
{
- uint32_t i;
+ u32 i;
state->recalc_words =
ibuf_ctrl_reg_load(ID, _IBUF_CNTRL_RECALC_WORDS_STATUS);
ibuf_ctrl_get_proc_state(
ID,
i,
- &(state->proc_state[i]));
+ &state->proc_state[i]);
}
}
*/
STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_get_proc_state(
const ibuf_ctrl_ID_t ID,
- const uint32_t proc_id,
+ const u32 proc_id,
ibuf_ctrl_proc_state_t *state)
{
hrt_address reg_bank_offset;
state->isp_sync_state =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ISP_SYNC_STATE);
}
+
/**
* @brief Dump the ibuf-controller state.
* Refer to "ibuf_ctrl_public.h" for details.
const ibuf_ctrl_ID_t ID,
ibuf_ctrl_state_t *state)
{
- uint32_t i;
+ u32 i;
+
ia_css_print("IBUF controller ID %d recalculate words 0x%x\n", ID, state->recalc_words);
ia_css_print("IBUF controller ID %d arbiters 0x%x\n", ID, state->arbiters);
ia_css_print("IBUF controller ID %d Process ID %d isp_sync_state 0x%x\n", ID, i, state->proc_state[i].isp_sync_state);
}
}
+
/* end of NCI */
/*****************************************************
{
assert(ID < N_IBUF_CTRL_ID);
assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1);
- return ia_css_device_load_uint32(IBUF_CTRL_BASE[ID] + reg*sizeof(hrt_data));
+ return ia_css_device_load_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data));
}
-
/**
* @brief Store a value to the register.
* Refer to "ibuf_ctrl_public.h" for details.
assert(ID < N_IBUF_CTRL_ID);
assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1);
- ia_css_device_store_uint32(IBUF_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
+ ia_css_device_store_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
}
-/* end of DLI */
+/* end of DLI */
#endif /* __IBUF_CTRL_PRIVATE_H_INCLUDED__ */
const input_system_ID_t ID,
input_system_state_t *state)
{
- uint32_t i;
+ u32 i;
(void)(ID);
for (i = 0; i < N_CSI_RX_FRONTEND_ID; i++) {
csi_rx_fe_ctrl_get_state(
(csi_rx_frontend_ID_t)i,
- &(state->csi_rx_fe_ctrl_state[i]));
+ &state->csi_rx_fe_ctrl_state[i]);
}
/* get the states of all CIS RX backend devices */
for (i = 0; i < N_CSI_RX_BACKEND_ID; i++) {
csi_rx_be_ctrl_get_state(
(csi_rx_backend_ID_t)i,
- &(state->csi_rx_be_ctrl_state[i]));
+ &state->csi_rx_be_ctrl_state[i]);
}
/* get the states of all pixelgen devices */
for (i = 0; i < N_PIXELGEN_ID; i++) {
pixelgen_ctrl_get_state(
(pixelgen_ID_t)i,
- &(state->pixelgen_ctrl_state[i]));
+ &state->pixelgen_ctrl_state[i]);
}
/* get the states of all stream2mmio devices */
for (i = 0; i < N_STREAM2MMIO_ID; i++) {
stream2mmio_get_state(
(stream2mmio_ID_t)i,
- &(state->stream2mmio_state[i]));
+ &state->stream2mmio_state[i]);
}
/* get the states of all ibuf-controller devices */
for (i = 0; i < N_IBUF_CTRL_ID; i++) {
ibuf_ctrl_get_state(
(ibuf_ctrl_ID_t)i,
- &(state->ibuf_ctrl_state[i]));
+ &state->ibuf_ctrl_state[i]);
}
/* get the states of all isys irq controllers */
for (i = 0; i < N_ISYS_IRQ_ID; i++) {
- isys_irqc_state_get((isys_irq_ID_t)i, &(state->isys_irqc_state[i]));
+ isys_irqc_state_get((isys_irq_ID_t)i, &state->isys_irqc_state[i]);
}
/* TODO: get the states of all ISYS2401 DMA devices */
return INPUT_SYSTEM_ERR_NO_ERROR;
}
+
STORAGE_CLASS_INPUT_SYSTEM_C void input_system_dump_state(
const input_system_ID_t ID,
input_system_state_t *state)
{
- uint32_t i;
+ u32 i;
(void)(ID);
for (i = 0; i < N_CSI_RX_FRONTEND_ID; i++) {
csi_rx_fe_ctrl_dump_state(
(csi_rx_frontend_ID_t)i,
- &(state->csi_rx_fe_ctrl_state[i]));
+ &state->csi_rx_fe_ctrl_state[i]);
}
/* dump the states of all CIS RX backend devices */
for (i = 0; i < N_CSI_RX_BACKEND_ID; i++) {
csi_rx_be_ctrl_dump_state(
(csi_rx_backend_ID_t)i,
- &(state->csi_rx_be_ctrl_state[i]));
+ &state->csi_rx_be_ctrl_state[i]);
}
/* dump the states of all pixelgen devices */
for (i = 0; i < N_PIXELGEN_ID; i++) {
pixelgen_ctrl_dump_state(
(pixelgen_ID_t)i,
- &(state->pixelgen_ctrl_state[i]));
+ &state->pixelgen_ctrl_state[i]);
}
/* dump the states of all st2mmio devices */
for (i = 0; i < N_STREAM2MMIO_ID; i++) {
stream2mmio_dump_state(
(stream2mmio_ID_t)i,
- &(state->stream2mmio_state[i]));
+ &state->stream2mmio_state[i]);
}
/* dump the states of all ibuf-controller devices */
for (i = 0; i < N_IBUF_CTRL_ID; i++) {
ibuf_ctrl_dump_state(
(ibuf_ctrl_ID_t)i,
- &(state->ibuf_ctrl_state[i]));
+ &state->ibuf_ctrl_state[i]);
}
/* dump the states of all isys irq controllers */
for (i = 0; i < N_ISYS_IRQ_ID; i++) {
- isys_irqc_state_dump((isys_irq_ID_t)i, &(state->isys_irqc_state[i]));
+ isys_irqc_state_dump((isys_irq_ID_t)i, &state->isys_irqc_state[i]);
}
/* TODO: dump the states of all ISYS2401 DMA devices */
#include "dma_v2_defs.h"
#include "print_support.h"
-
STORAGE_CLASS_ISYS2401_DMA_C void isys2401_dma_reg_store(
const isys2401_dma_ID_t dma_id,
const unsigned int reg,
unsigned int reg_loc;
assert(dma_id < N_ISYS2401_DMA_ID);
- assert(ISYS2401_DMA_BASE[dma_id] != (hrt_address)-1);
+ assert(ISYS2401_DMA_BASE[dma_id] != (hrt_address) - 1);
reg_loc = ISYS2401_DMA_BASE[dma_id] + (reg * sizeof(hrt_data));
hrt_data value;
assert(dma_id < N_ISYS2401_DMA_ID);
- assert(ISYS2401_DMA_BASE[dma_id] != (hrt_address)-1);
+ assert(ISYS2401_DMA_BASE[dma_id] != (hrt_address) - 1);
reg_loc = ISYS2401_DMA_BASE[dma_id] + (reg * sizeof(hrt_data));
const isys_irqc_state_t *state)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
- "isys irq controller id %d"
- "\n\tstatus:0x%x\n\tedge:0x%x\n\tmask:0x%x"
- "\n\tenable:0x%x\n\tlevel_not_pulse:0x%x\n",
+ "isys irq controller id %d\n\tstatus:0x%x\n\tedge:0x%x\n\tmask:0x%x\n\tenable:0x%x\n\tlevel_not_pulse:0x%x\n",
isys_irqc_id,
state->status, state->edge, state->mask, state->enable, state->level_no);
}
};
struct stream2mmio_state_s {
- stream2mmio_sid_state_t sid_state[N_STREAM2MMIO_SID_ID];
+ stream2mmio_sid_state_t sid_state[N_STREAM2MMIO_SID_ID];
};
#endif /* __ISYS_STREAM2MMIO_LOCAL_H_INCLUDED__ */
* stream2mmio-controller sids.
*/
for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) {
- stream2mmio_get_sid_state(ID, i, &(state->sid_state[i]));
+ stream2mmio_get_sid_state(ID, i, &state->sid_state[i]);
}
}
const stream2mmio_sid_ID_t sid_id,
stream2mmio_sid_state_t *state)
{
-
state->rcv_ack =
stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_ACKNOWLEDGE_REG_ID);
state->block_when_no_cmd =
stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID);
-
}
/**
ia_css_print("\t \t Strides 0x%x\n", state->strides);
ia_css_print("\t \t Num Items 0x%x\n", state->num_items);
ia_css_print("\t \t block when no cmd 0x%x\n", state->block_when_no_cmd);
-
}
+
/**
* @brief Dump the ibuf-controller state.
* Refer to "stream2mmio_public.h" for details.
*/
for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) {
ia_css_print("StREAM2MMIO ID %d SID %d\n", ID, i);
- stream2mmio_print_sid_state(&(state->sid_state[i]));
+ stream2mmio_print_sid_state(&state->sid_state[i]);
}
}
+
/* end of NCI */
/*****************************************************
const stream2mmio_sid_ID_t sid_id,
const uint32_t reg_idx)
{
- uint32_t reg_bank_offset;
+ u32 reg_bank_offset;
assert(ID < N_STREAM2MMIO_ID);
(reg_bank_offset + reg_idx) * sizeof(hrt_data));
}
-
/**
* @brief Store a value to the register.
* Refer to "stream2mmio_public.h" for details.
ia_css_device_store_uint32(STREAM2MMIO_CTRL_BASE[ID] +
reg * sizeof(hrt_data), value);
}
+
/* end of DLI */
#endif /* __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__ */
#include "device_access.h" /* ia_css_device_load_uint32 */
#include "assert_support.h" /* assert */
-
/*****************************************************
*
* Native command interface (NCI).
const pixelgen_ID_t ID,
pixelgen_ctrl_state_t *state)
{
-
state->com_enable =
pixelgen_ctrl_reg_load(ID, _PXG_COM_ENABLE_REG_IDX);
state->prbs_rstval0 =
state->tpg_b2 =
pixelgen_ctrl_reg_load(ID, _PXG_TPG_B2_REG_IDX);
}
+
/**
* @brief Dump the pixelgen state.
* Refer to "pixelgen_public.h" for details.
const pixelgen_ID_t ID,
pixelgen_ctrl_state_t *state)
{
- ia_css_print("Pixel Generator ID %d Enable 0x%x \n", ID, state->com_enable);
- ia_css_print("Pixel Generator ID %d PRBS reset vlue 0 0x%x \n", ID, state->prbs_rstval0);
- ia_css_print("Pixel Generator ID %d PRBS reset vlue 1 0x%x \n", ID, state->prbs_rstval1);
- ia_css_print("Pixel Generator ID %d SYNC SID 0x%x \n", ID, state->syng_sid);
- ia_css_print("Pixel Generator ID %d syng free run 0x%x \n", ID, state->syng_free_run);
- ia_css_print("Pixel Generator ID %d syng pause 0x%x \n", ID, state->syng_pause);
- ia_css_print("Pixel Generator ID %d syng no of frames 0x%x \n", ID, state->syng_nof_frames);
- ia_css_print("Pixel Generator ID %d syng no of pixels 0x%x \n", ID, state->syng_nof_pixels);
- ia_css_print("Pixel Generator ID %d syng no of line 0x%x \n", ID, state->syng_nof_line);
- ia_css_print("Pixel Generator ID %d syng hblank cyc 0x%x \n", ID, state->syng_hblank_cyc);
- ia_css_print("Pixel Generator ID %d syng vblank cyc 0x%x \n", ID, state->syng_vblank_cyc);
- ia_css_print("Pixel Generator ID %d syng stat hcnt 0x%x \n", ID, state->syng_stat_hcnt);
- ia_css_print("Pixel Generator ID %d syng stat vcnt 0x%x \n", ID, state->syng_stat_vcnt);
- ia_css_print("Pixel Generator ID %d syng stat fcnt 0x%x \n", ID, state->syng_stat_fcnt);
- ia_css_print("Pixel Generator ID %d syng stat done 0x%x \n", ID, state->syng_stat_done);
- ia_css_print("Pixel Generator ID %d tpg modee 0x%x \n", ID, state->tpg_mode);
- ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x \n", ID, state->tpg_hcnt_mask);
- ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x \n", ID, state->tpg_hcnt_mask);
- ia_css_print("Pixel Generator ID %d tpg xycnt mask 0x%x \n", ID, state->tpg_xycnt_mask);
- ia_css_print("Pixel Generator ID %d tpg hcnt delta 0x%x \n", ID, state->tpg_hcnt_delta);
- ia_css_print("Pixel Generator ID %d tpg vcnt delta 0x%x \n", ID, state->tpg_vcnt_delta);
- ia_css_print("Pixel Generator ID %d tpg r1 0x%x \n", ID, state->tpg_r1);
- ia_css_print("Pixel Generator ID %d tpg g1 0x%x \n", ID, state->tpg_g1);
- ia_css_print("Pixel Generator ID %d tpg b1 0x%x \n", ID, state->tpg_b1);
- ia_css_print("Pixel Generator ID %d tpg r2 0x%x \n", ID, state->tpg_r2);
- ia_css_print("Pixel Generator ID %d tpg g2 0x%x \n", ID, state->tpg_g2);
- ia_css_print("Pixel Generator ID %d tpg b2 0x%x \n", ID, state->tpg_b2);
+ ia_css_print("Pixel Generator ID %d Enable 0x%x\n", ID, state->com_enable);
+ ia_css_print("Pixel Generator ID %d PRBS reset vlue 0 0x%x\n", ID, state->prbs_rstval0);
+ ia_css_print("Pixel Generator ID %d PRBS reset vlue 1 0x%x\n", ID, state->prbs_rstval1);
+ ia_css_print("Pixel Generator ID %d SYNC SID 0x%x\n", ID, state->syng_sid);
+ ia_css_print("Pixel Generator ID %d syng free run 0x%x\n", ID, state->syng_free_run);
+ ia_css_print("Pixel Generator ID %d syng pause 0x%x\n", ID, state->syng_pause);
+ ia_css_print("Pixel Generator ID %d syng no of frames 0x%x\n", ID, state->syng_nof_frames);
+ ia_css_print("Pixel Generator ID %d syng no of pixels 0x%x\n", ID, state->syng_nof_pixels);
+ ia_css_print("Pixel Generator ID %d syng no of line 0x%x\n", ID, state->syng_nof_line);
+ ia_css_print("Pixel Generator ID %d syng hblank cyc 0x%x\n", ID, state->syng_hblank_cyc);
+ ia_css_print("Pixel Generator ID %d syng vblank cyc 0x%x\n", ID, state->syng_vblank_cyc);
+ ia_css_print("Pixel Generator ID %d syng stat hcnt 0x%x\n", ID, state->syng_stat_hcnt);
+ ia_css_print("Pixel Generator ID %d syng stat vcnt 0x%x\n", ID, state->syng_stat_vcnt);
+ ia_css_print("Pixel Generator ID %d syng stat fcnt 0x%x\n", ID, state->syng_stat_fcnt);
+ ia_css_print("Pixel Generator ID %d syng stat done 0x%x\n", ID, state->syng_stat_done);
+ ia_css_print("Pixel Generator ID %d tpg modee 0x%x\n", ID, state->tpg_mode);
+ ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x\n", ID, state->tpg_hcnt_mask);
+ ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x\n", ID, state->tpg_hcnt_mask);
+ ia_css_print("Pixel Generator ID %d tpg xycnt mask 0x%x\n", ID, state->tpg_xycnt_mask);
+ ia_css_print("Pixel Generator ID %d tpg hcnt delta 0x%x\n", ID, state->tpg_hcnt_delta);
+ ia_css_print("Pixel Generator ID %d tpg vcnt delta 0x%x\n", ID, state->tpg_vcnt_delta);
+ ia_css_print("Pixel Generator ID %d tpg r1 0x%x\n", ID, state->tpg_r1);
+ ia_css_print("Pixel Generator ID %d tpg g1 0x%x\n", ID, state->tpg_g1);
+ ia_css_print("Pixel Generator ID %d tpg b1 0x%x\n", ID, state->tpg_b1);
+ ia_css_print("Pixel Generator ID %d tpg r2 0x%x\n", ID, state->tpg_r2);
+ ia_css_print("Pixel Generator ID %d tpg g2 0x%x\n", ID, state->tpg_g2);
+ ia_css_print("Pixel Generator ID %d tpg b2 0x%x\n", ID, state->tpg_b2);
}
+
/* end of NCI */
/*****************************************************
*
const hrt_address reg)
{
assert(ID < N_PIXELGEN_ID);
- assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1);
- return ia_css_device_load_uint32(PIXELGEN_CTRL_BASE[ID] + reg*sizeof(hrt_data));
+ assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address) - 1);
+ return ia_css_device_load_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof(hrt_data));
}
-
/**
* @brief Store a value to the register.
* Refer to "pixelgen_ctrl_public.h" for details.
assert(ID < N_PIXELGEN_ID);
assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1);
- ia_css_device_store_uint32(PIXELGEN_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
+ ia_css_device_store_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
}
+
/* end of DLI */
#endif /* __PIXELGEN_PRIVATE_H_INCLUDED__ */
static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
0x0000000000000100ULL};
-
/* INPUT_FORMATTER */
static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
0x0000000000030000ULL,
0x00000000000C2400ULL, /* csi fe controller B */
0x00000000000C4400ULL /* csi fe controller C */
};
+
/* CSI BE, part of the Input System 2401 */
static const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = {
0x00000000000C0800ULL, /* csi be controller A */
0x00000000000C2800ULL, /* csi be controller B */
0x00000000000C4800ULL /* csi be controller C */
};
+
/* PIXEL Generator, part of the Input System 2401 */
static const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = {
0x00000000000C1000ULL, /* pixel gen controller A */
0x00000000000C3000ULL, /* pixel gen controller B */
0x00000000000C5000ULL /* pixel gen controller C */
};
+
/* Stream2MMIO, part of the Input System 2401 */
static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = {
0x00000000000C0C00ULL, /* stream2mmio controller A */
static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
0x00000100UL};
-
/* INPUT_FORMATTER */
static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
0x00030000UL,
0x000C2400UL, /* csi fe controller B */
0x000C4400UL /* csi fe controller C */
};
+
/* CSI BE, part of the Input System 2401 */
static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = {
0x000C0800UL, /* csi be controller A */
0x000C2800UL, /* csi be controller B */
0x000C4800UL /* csi be controller C */
};
+
/* PIXEL Generator, part of the Input System 2401 */
static const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = {
0x000C1000UL, /* pixel gen controller A */
0x000C3000UL, /* pixel gen controller B */
0x000C5000UL /* pixel gen controller C */
};
+
/* Stream2MMIO, part of the Input System 2401 */
static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = {
0x000C0C00UL, /* stream2mmio controller A */
#define _PXG_INVALID_FLAG 0xDEADBEEF
#define _PXG_CAFE_FLAG 0xCAFEBABE
-
#endif /* _PixelGen_SysBlock_defs_h */
-
#define _hrt_get_bit(w, b) \
(((w) >> (b)) & 1)
#define _hrt_set_bit(w, b, v) \
- (((w) & (~(1 << (b)))) | (((v)&1) << (b)))
+ (((w) & (~(1 << (b)))) | (((v) & 1) << (b)))
#define _hrt_set_lower_half(w, v) \
_hrt_set_bits(w, 0, 16, v)
#define _hrt_set_upper_half(w, v) \
#define SP_ICACHE_BLOCK_ADDRESS_BITS 11 /* 2048 lines capacity*/
#define SP_ICACHE_ADDRESS_BITS \
- (SP_ICACHE_TAG_BITS+SP_ICACHE_BLOCK_ADDRESS_BITS)
+ (SP_ICACHE_TAG_BITS + SP_ICACHE_BLOCK_ADDRESS_BITS)
-#define SP_PMEM_DEPTH (1<<SP_ICACHE_ADDRESS_BITS)
+#define SP_PMEM_DEPTH BIT(SP_ICACHE_ADDRESS_BITS)
#define SP_FIFO_0_DEPTH 0
#define SP_FIFO_1_DEPTH 0
#define SP_FIFO_6_DEPTH 0
#define SP_FIFO_7_DEPTH 0
-
#define SP_SLV_BUS_MAXBURSTSIZE 1
#endif /* _cell_params_h */
-
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH 2
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH 3
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH (_HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH)
-#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */
+#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */
/* Definition of data format ID at the interface CSS_receiver capture/acquisition units */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8_CSPS 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10_CSPS 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
/* used reserved mipi positions for these */
-#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46
-#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47
-#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37
-#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38
+#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46
+#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47
+#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37
+#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_WIDTH 6
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB444 2 // 32
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB565 3 // 34
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB666 4 // 35
-#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42
+#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW10 6 // 43
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW6 7 // 40
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW7 8 // 41
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18 28 // ?
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_2 29 // ? Option 2 for depacketiser
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_3 30 // ? Option 3 for depacketiser
-#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding
+#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding
/* definition for state machine of data FIFO for decode different type of data */
-#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1
+#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV420_10_REPEAT_PTN 5
#define _HRT_CSS_RECEIVER_2400_YUV420_8L_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV422_8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV422_10_REPEAT_PTN 5
-#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2
+#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB555_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB565_REPEAT_PTN 2
-#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9
+#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9
#define _HRT_CSS_RECEIVER_2400_RGB888_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW6_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW7_REPEAT_PTN 7
#define _HRT_CSS_RECEIVER_2400_RAW8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_RAW10_REPEAT_PTN 5
-#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3
+#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW14_REPEAT_PTN 7
#define _HRT_CSS_RECEIVER_2400_MAX_REPEAT_PTN _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_7_12 5
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_8_12 6
-
/* packet bit definition */
#define _HRT_CSS_RECEIVER_2400_PKT_SOP_IDX 32
#define _HRT_CSS_RECEIVER_2400_PKT_SOP_BITS 1
#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_IDX 0
#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_BITS 32
-
/*************************************************************************************************/
/* Custom Decoding */
/* These Custom Defs are defined based on design-time config in "csi_be_pixel_formatter.chdl" !! */
/*************************************************************************************************/
#define BE_CUST_EN_IDX 0 /* 2bits */
-#define BE_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */
-#define BE_CUST_EN_WIDTH 8
+#define BE_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */
+#define BE_CUST_EN_WIDTH 8
#define BE_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */
#define BE_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */
/* Data State config = {get_bits(6bits), valid(1bit)} */
-#define BE_CUST_DATA_STATE_S0_IDX 0 /* 7bits */
-#define BE_CUST_DATA_STATE_S1_IDX 7 /* 7bits */
+#define BE_CUST_DATA_STATE_S0_IDX 0 /* 7bits */
+#define BE_CUST_DATA_STATE_S1_IDX 7 /* 7bits */
#define BE_CUST_DATA_STATE_S2_IDX 14 /* 7bits */
-#define BE_CUST_DATA_STATE_WIDTH 21
+#define BE_CUST_DATA_STATE_WIDTH 21
#define BE_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */
#define BE_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */
#define BE_CUST_PIX_EXT_PIX_ALIGN_IDX 5 /* 5bits */
#define BE_CUST_PIX_EXT_PIX_MASK_IDX 10 /* 18bits */
#define BE_CUST_PIX_EXT_PIX_EN_IDX 28 /* 1bits */
-#define BE_CUST_PIX_EXT_WIDTH 29
+#define BE_CUST_PIX_EXT_WIDTH 29
/* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */
#define BE_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */
-#define BE_CUST_PIX_VALID_EOP_WIDTH 16
+#define BE_CUST_PIX_VALID_EOP_WIDTH 16
#define BE_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */
#define BE_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */
#define BE_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */
#define BE_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */
#endif /* _mipi_backend_common_defs_h_ */
-#endif /* _css_receiver_2400_common_defs_h_ */
+#endif /* _css_receiver_2400_common_defs_h_ */
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_ECC_TWO_BIT_ERR_IDX 6
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_DATA_ID_ERR_IDX 7
-
/* Bits for CSI2_FUNC_PROG register */
#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX 0
#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS 19
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_IDX 3
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_BITS 2
-
/* BITS for backend RAW16 and RAW 18 registers */
#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_IDX 0
#define _HRT_CSS_RECEIVER_2400_RAW16_EN_BITS 1
/* These hsync and vsync values are for HSS simulation only */
-#define _HRT_CSS_RECEIVER_2400_HSYNC_VAL (1<<16)
-#define _HRT_CSS_RECEIVER_2400_VSYNC_VAL (1<<17)
+#define _HRT_CSS_RECEIVER_2400_HSYNC_VAL BIT(16)
+#define _HRT_CSS_RECEIVER_2400_VSYNC_VAL BIT(17)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_WIDTH 28
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB 0
#define _DMA_V2_SPEC_DEV_B_XB_IDX (_DMA_V2_SPEC_DEV_A_XB_IDX + _DMA_V2_SPEC_DEV_A_XB_BITS)
#define _DMA_V2_SPEC_DEV_B_XB_BITS 8
#define _DMA_V2_SPEC_YB_IDX (_DMA_V2_SPEC_DEV_B_XB_IDX + _DMA_V2_SPEC_DEV_B_XB_BITS)
-#define _DMA_V2_SPEC_YB_BITS (32-_DMA_V2_SPEC_DEV_B_XB_BITS-_DMA_V2_SPEC_DEV_A_XB_BITS-_DMA_V2_CMD_BITS-_DMA_V2_CHANNEL_BITS)
+#define _DMA_V2_SPEC_YB_BITS (32 - _DMA_V2_SPEC_DEV_B_XB_BITS - _DMA_V2_SPEC_DEV_A_XB_BITS - _DMA_V2_CMD_BITS - _DMA_V2_CHANNEL_BITS)
/* */
#define _DMA_V2_CMD_CTRL_IDX 4
#define _DMA_V2_STRIDE_BITS 32
/* Command IDs */
-#define _DMA_V2_MOVE_B2A_COMMAND 0
-#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1
-#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2
-#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3
-#define _DMA_V2_MOVE_A2B_COMMAND 4
-#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5
-#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6
-#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7
-#define _DMA_V2_INIT_A_COMMAND 8
-#define _DMA_V2_INIT_A_BLOCK_COMMAND 9
-#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10
-#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11
-#define _DMA_V2_INIT_B_COMMAND 12
-#define _DMA_V2_INIT_B_BLOCK_COMMAND 13
-#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14
-#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15
-#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32
-#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33
-#define _DMA_V2_SET_CRUN_COMMAND 62
+#define _DMA_V2_MOVE_B2A_COMMAND 0
+#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1
+#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2
+#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3
+#define _DMA_V2_MOVE_A2B_COMMAND 4
+#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5
+#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6
+#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7
+#define _DMA_V2_INIT_A_COMMAND 8
+#define _DMA_V2_INIT_A_BLOCK_COMMAND 9
+#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10
+#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11
+#define _DMA_V2_INIT_B_COMMAND 12
+#define _DMA_V2_INIT_B_BLOCK_COMMAND 13
+#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14
+#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15
+#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32
+#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33
+#define _DMA_V2_SET_CRUN_COMMAND 62
/* Channel Parameter IDs */
-#define _DMA_V2_PACKING_SETUP_PARAM 0
-#define _DMA_V2_STRIDE_A_PARAM 1
-#define _DMA_V2_ELEM_CROPPING_A_PARAM 2
-#define _DMA_V2_WIDTH_A_PARAM 3
-#define _DMA_V2_STRIDE_B_PARAM 4
-#define _DMA_V2_ELEM_CROPPING_B_PARAM 5
-#define _DMA_V2_WIDTH_B_PARAM 6
-#define _DMA_V2_HEIGHT_PARAM 7
-#define _DMA_V2_QUEUED_CMDS 8
+#define _DMA_V2_PACKING_SETUP_PARAM 0
+#define _DMA_V2_STRIDE_A_PARAM 1
+#define _DMA_V2_ELEM_CROPPING_A_PARAM 2
+#define _DMA_V2_WIDTH_A_PARAM 3
+#define _DMA_V2_STRIDE_B_PARAM 4
+#define _DMA_V2_ELEM_CROPPING_B_PARAM 5
+#define _DMA_V2_WIDTH_B_PARAM 6
+#define _DMA_V2_HEIGHT_PARAM 7
+#define _DMA_V2_QUEUED_CMDS 8
/* Parameter Constants */
#define _DMA_V2_ZERO_EXTEND 0
#define _DMA_V2_ADDR_SEL_COMP_BITS 4
#define _DMA_V2_ADDR_SEL_CH_REG_IDX 2
#define _DMA_V2_ADDR_SEL_CH_REG_BITS 6
-#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS+_DMA_V2_ADDR_SEL_CH_REG_IDX)
+#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS + _DMA_V2_ADDR_SEL_CH_REG_IDX)
#define _DMA_V2_ADDR_SEL_PARAM_BITS 4
#define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX 2
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX 2
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS 6
-#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX+_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS)
+#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX + _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS)
#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS 4
#define _DMA_V2_FSM_GROUP_CMD_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_PACK_IDX 5
#define _DMA_V2_FSM_GROUP_FSM_REQ_IDX 6
#define _DMA_V2_FSM_GROUP_FSM_WR_IDX 7
-
+
#define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX 2
#define HRT_GDC_FRAC_BITS 10 /* Number of fractional bits in the GDC block, driven by the size of the LUT */
#define HRT_GDC_BLI_FRAC_BITS 4 /* Number of fractional bits for the bi-linear interpolation type */
-#define HRT_GDC_BLI_COEF_ONE (1 << HRT_GDC_BLI_FRAC_BITS)
+#define HRT_GDC_BLI_COEF_ONE BIT(HRT_GDC_BLI_FRAC_BITS)
#define HRT_GDC_BCI_COEF_BITS 14 /* 14 bits per coefficient */
-#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS-2)) /* We represent signed 10 bit coefficients. */
- /* The supported range is [-256, .., +256] */
- /* in 14-bit signed notation, */
- /* We need all ten bits (MSB must be zero). */
- /* -s is inserted to solve this issue, and */
- /* therefore "1" is equal to +256. */
-#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1)
+#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS - 2)) /* We represent signed 10 bit coefficients. */
+ /* The supported range is [-256, .., +256] */
+ /* in 14-bit signed notation, */
+ /* We need all ten bits (MSB must be zero). */
+ /* -s is inserted to solve this issue, and */
+ /* therefore "1" is equal to +256. */
+#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1)
-#define HRT_GDC_LUT_BYTES (HRT_GDC_N*4*2) /* 1024 addresses, 4 coefficients per address, */
- /* 2 bytes per coefficient */
+#define HRT_GDC_LUT_BYTES (HRT_GDC_N * 4 * 2) /* 1024 addresses, 4 coefficients per address, */
+ /* 2 bytes per coefficient */
-#define _HRT_GDC_REG_ALIGN 4
+#define _HRT_GDC_REG_ALIGN 4
// 31 30 29 25 24 0
// |-----|---|--------|------------------------|
// | CMD | C | Reg_ID | Value |
-
// There are just two commands possible for the GDC block:
- // 1 - Configure reg
- // 0 - Data token
-
+ // 1 - Configure reg
+ // 0 - Data token
+
// C - Reserved bit
// Used in protocol to indicate whether it is C-run or other type of runs
// In case of C-run, this bit has a value of 1, for all the other runs, it is 0.
// Reg_ID - Address of the register to be configured
-
+
// Value - Value to store to the addressed register, maximum of 24 bits
- // Configure reg command is not followed by any other token.
- // The address of the register and the data to be filled in is contained in the same token
-
+ // Configure reg command is not followed by any other token.
+ // The address of the register and the data to be filled in is contained in the same token
+
// When the first data token is received, it must be:
// 1. FRX and FRY (device configured in one of the scaling modes) ***DEFAULT MODE***, or,
// 2. P0'X (device configured in one of the tetragon modes)
// After the first data token is received, pre-defined number of tokens with the following meaning follow:
// 1. two tokens: SRC address ; DST address
// 2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address
-
+
#define HRT_GDC_CONFIG_CMD 1
#define HRT_GDC_DATA_CMD 0
-
#define HRT_GDC_CMD_POS 31
#define HRT_GDC_CMD_BITS 1
#define HRT_GDC_CRUN_POS 30
#define HRT_GDC_FRYIPXFRX_BITS 26
#define HRT_GDC_P0X_BITS 23
-
-#define HRT_GDC_MAX_OXDIM (8192-64)
+#define HRT_GDC_MAX_OXDIM (8192 - 64)
#define HRT_GDC_MAX_OYDIM 4095
-#define HRT_GDC_MAX_IXDIM (8192-64)
+#define HRT_GDC_MAX_IXDIM (8192 - 64)
#define HRT_GDC_MAX_IYDIM 4095
#define HRT_GDC_MAX_DS_FAC 16
-#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC*HRT_GDC_N - 1)
+#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC * HRT_GDC_N - 1)
#define HRT_GDC_MAX_DY HRT_GDC_MAX_DX
-
/* GDC lookup tables entries are 10 bits values, but they're
stored 2 by 2 as 32 bit values, yielding 16 bits per entry.
A GDC lookup table contains 64 * 4 elements */
#define HRT_GDC_MODE_SCALING 0
#define HRT_GDC_MODE_TETRAGON 1
-#define HRT_GDC_LUT_COEFF_OFFSET 16
-#define HRT_GDC_FRY_BIT_OFFSET 16
-// FRYIPXFRX is the only register where we store two values in one field,
-// to save one token in the scaling protocol.
-// Like this, we have three tokens in the scaling protocol,
+#define HRT_GDC_LUT_COEFF_OFFSET 16
+#define HRT_GDC_FRY_BIT_OFFSET 16
+// FRYIPXFRX is the only register where we store two values in one field,
+// to save one token in the scaling protocol.
+// Like this, we have three tokens in the scaling protocol,
// Otherwise, we would have had four.
// The register bit-map is:
// 31 26 25 16 15 10 9 0
// |------|----------|------|----------|
// | XXXX | FRY | IPX | FRX |
-
#define HRT_GDC_CE_FSM0_POS 0
#define HRT_GDC_CE_FSM0_LEN 2
#define HRT_GDC_CE_OPY_POS 2
// 31 16 15 2 1 0
// |----------------|-----------|----|
// | OPX | OPY |FSM0|
-// However, for the time being at least,
+// However, for the time being at least,
// this implementation is meaningless in hss model,
// So, we just return 0
-
#define HRT_GDC_CHK_ENGINE_IDX 0
#define HRT_GDC_WOIX_IDX 1
#define HRT_GDC_WOIY_IDX 2
#define HRT_GDC_LUT_IDX 32
-
#endif /* HRT_GDC_v2_defs_h_ */
#define HIVE_GP_TIMER_RESET_REG_IDX 0
#define HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX 1
#define HIVE_GP_TIMER_ENABLE_REG_IDX(timer) (HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX + 1 + timer)
-#define HIVE_GP_TIMER_VALUE_REG_IDX(timer,timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer)
-#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer,timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer)
-#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer,timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer)
-#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq,timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq)
-#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq)
-#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq)
+#define HIVE_GP_TIMER_VALUE_REG_IDX(timer, timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer)
+#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer, timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer)
+#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer, timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer)
+#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq, timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq)
+#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq)
+#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq)
#define HIVE_GP_TIMER_COUNT_TYPE_HIGH 0
#define HIVE_GP_TIMER_COUNT_TYPE_LOW 1
#define HIVE_GP_TIMER_COUNT_TYPE_NEGEDGE 3
#define HIVE_GP_TIMER_COUNT_TYPES 4
-#endif /* _gp_timer_defs_h */
+#endif /* _gp_timer_defs_h */
#define _gpio_block_reg_di_debounce_cnt_3 14
#define _gpio_block_reg_di_active_level 15
-
/* read-only registers */
#define _gpio_block_reg_di 16
* The definitions are taken from <system>_defs.h
*/
typedef enum hrt_isp_css_irq {
- hrt_isp_css_irq_gpio_pin_0 = HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_1 = HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_2 = HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_3 = HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_4 = HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_5 = HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_6 = HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_7 = HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_8 = HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_9 = HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_10 = HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_11 = HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID ,
- hrt_isp_css_irq_sp = HIVE_GP_DEV_IRQ_SP_BIT_ID ,
- hrt_isp_css_irq_isp = HIVE_GP_DEV_IRQ_ISP_BIT_ID ,
- hrt_isp_css_irq_isys = HIVE_GP_DEV_IRQ_ISYS_BIT_ID ,
- hrt_isp_css_irq_isel = HIVE_GP_DEV_IRQ_ISEL_BIT_ID ,
- hrt_isp_css_irq_ifmt = HIVE_GP_DEV_IRQ_IFMT_BIT_ID ,
- hrt_isp_css_irq_sp_stream_mon = HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID ,
- hrt_isp_css_irq_isp_stream_mon = HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID ,
- hrt_isp_css_irq_mod_stream_mon = HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID ,
- hrt_isp_css_irq_is2401 = HIVE_GP_DEV_IRQ_IS2401_BIT_ID ,
- hrt_isp_css_irq_isp_bamem_error = HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID ,
- hrt_isp_css_irq_isp_dmem_error = HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID ,
- hrt_isp_css_irq_sp_icache_mem_error = HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID ,
- hrt_isp_css_irq_sp_dmem_error = HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID ,
- hrt_isp_css_irq_mmu_cache_mem_error = HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID ,
- hrt_isp_css_irq_gp_timer_0 = HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID ,
- hrt_isp_css_irq_gp_timer_1 = HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID ,
- hrt_isp_css_irq_sw_pin_0 = HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID ,
- hrt_isp_css_irq_sw_pin_1 = HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID ,
- hrt_isp_css_irq_dma = HIVE_GP_DEV_IRQ_DMA_BIT_ID ,
- hrt_isp_css_irq_sp_stream_mon_b = HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID ,
+ hrt_isp_css_irq_gpio_pin_0 = HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_1 = HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_2 = HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_3 = HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_4 = HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_5 = HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_6 = HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_7 = HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_8 = HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_9 = HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_10 = HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_11 = HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID,
+ hrt_isp_css_irq_sp = HIVE_GP_DEV_IRQ_SP_BIT_ID,
+ hrt_isp_css_irq_isp = HIVE_GP_DEV_IRQ_ISP_BIT_ID,
+ hrt_isp_css_irq_isys = HIVE_GP_DEV_IRQ_ISYS_BIT_ID,
+ hrt_isp_css_irq_isel = HIVE_GP_DEV_IRQ_ISEL_BIT_ID,
+ hrt_isp_css_irq_ifmt = HIVE_GP_DEV_IRQ_IFMT_BIT_ID,
+ hrt_isp_css_irq_sp_stream_mon = HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID,
+ hrt_isp_css_irq_isp_stream_mon = HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID,
+ hrt_isp_css_irq_mod_stream_mon = HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID,
+ hrt_isp_css_irq_is2401 = HIVE_GP_DEV_IRQ_IS2401_BIT_ID,
+ hrt_isp_css_irq_isp_bamem_error = HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID,
+ hrt_isp_css_irq_isp_dmem_error = HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID,
+ hrt_isp_css_irq_sp_icache_mem_error = HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID,
+ hrt_isp_css_irq_sp_dmem_error = HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID,
+ hrt_isp_css_irq_mmu_cache_mem_error = HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID,
+ hrt_isp_css_irq_gp_timer_0 = HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID,
+ hrt_isp_css_irq_gp_timer_1 = HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID,
+ hrt_isp_css_irq_sw_pin_0 = HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID,
+ hrt_isp_css_irq_sw_pin_1 = HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID,
+ hrt_isp_css_irq_dma = HIVE_GP_DEV_IRQ_DMA_BIT_ID,
+ hrt_isp_css_irq_sp_stream_mon_b = HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID,
/* this must (obviously) be the last on in the enum */
hrt_isp_css_irq_num_irqs
} hrt_isp_css_irq_t;
and in the DMA parameter list */
#define HIVE_ISP_DDR_DMA_SPECS {{32, 8}, {16, 16}, {18, 14}, {25, 10}, {21, 12}}
#define HIVE_ISP_DDR_WORD_BITS 256
-#define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS/8)
+#define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS / 8)
#define HIVE_ISP_DDR_BYTES (512 * 1024 * 1024)
#define HIVE_ISP_DDR_BYTES_RTL (127 * 1024 * 1024)
#define HIVE_ISP_DDR_SMALL_BYTES (128 * 256 / 8)
#define HIVE_ISP_PAGE_SHIFT 12
-#define HIVE_ISP_PAGE_SIZE (1<<HIVE_ISP_PAGE_SHIFT)
+#define HIVE_ISP_PAGE_SIZE BIT(HIVE_ISP_PAGE_SHIFT)
#define CSS_DDR_WORD_BITS HIVE_ISP_DDR_WORD_BITS
#define CSS_DDR_WORD_BYTES HIVE_ISP_DDR_WORD_BYTES
#define HIVE_VMEM_VECTOR_ELEMENTS 64
#define HIVE_VMEM_ELEMENT_BITS 14
#define HIVE_XMEM_ELEMENT_BITS 16
-#define HIVE_VMEM_VECTOR_BYTES (HIVE_VMEM_VECTOR_ELEMENTS*HIVE_XMEM_ELEMENT_BITS/8) /* used for # addr bytes for one vector */
-#define HIVE_XMEM_PACKED_WORD_VMEM_ELEMENTS (HIVE_XMEM_WIDTH/HIVE_VMEM_ELEMENT_BITS)
-#define HIVE_XMEM_WORD_VMEM_ELEMENTS (HIVE_XMEM_WIDTH/HIVE_XMEM_ELEMENT_BITS)
+#define HIVE_VMEM_VECTOR_BYTES (HIVE_VMEM_VECTOR_ELEMENTS * HIVE_XMEM_ELEMENT_BITS / 8) /* used for # addr bytes for one vector */
+#define HIVE_XMEM_PACKED_WORD_VMEM_ELEMENTS (HIVE_XMEM_WIDTH / HIVE_VMEM_ELEMENT_BITS)
+#define HIVE_XMEM_WORD_VMEM_ELEMENTS (HIVE_XMEM_WIDTH / HIVE_XMEM_ELEMENT_BITS)
#define XMEM_INT_SIZE 4
-
-
-#define HIVE_ISYS_INP_BUFFER_BYTES (64*1024) /* 64 kByte = 2k words (of 256 bits) */
+#define HIVE_ISYS_INP_BUFFER_BYTES (64 * 1024) /* 64 kByte = 2k words (of 256 bits) */
/* If HIVE_ISP_DDR_BASE_OFFSET is set to a non-zero value, the wide bus just before the DDRAM gets an extra dummy port where */
/* address range 0 .. HIVE_ISP_DDR_BASE_OFFSET-1 maps onto. This effectively creates an offset for the DDRAM from system perspective */
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I4_I0 51
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I5_I0 52
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I6_I0 53
-#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I7_I0 54
+#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I7_I0 54
#define HIVE_GP_TIMER_MIPI_SOL_BIT_ID 55
#define HIVE_GP_TIMER_MIPI_EOL_BIT_ID 56
#define HIVE_GP_TIMER_MIPI_SOF_BIT_ID 57
/* port definititions SP streaming monitor, monitors the status of streaming ports at the SP side of the streaming FIFO's */
#define SP_STR_MON_PORT_SP2SIF 0
#define SP_STR_MON_PORT_SIF2SP 1
-#define SP_STR_MON_PORT_SP2MC 2
+#define SP_STR_MON_PORT_SP2MC 2
#define SP_STR_MON_PORT_MC2SP 3
-#define SP_STR_MON_PORT_SP2DMA 4
+#define SP_STR_MON_PORT_SP2DMA 4
#define SP_STR_MON_PORT_DMA2SP 5
-#define SP_STR_MON_PORT_SP2ISP 6
+#define SP_STR_MON_PORT_SP2ISP 6
#define SP_STR_MON_PORT_ISP2SP 7
#define SP_STR_MON_PORT_SP2GPD 8
#define SP_STR_MON_PORT_FA2SP 9
-#define SP_STR_MON_PORT_SP2ISYS 10
+#define SP_STR_MON_PORT_SP2ISYS 10
#define SP_STR_MON_PORT_ISYS2SP 11
#define SP_STR_MON_PORT_SP2PIFA 12
#define SP_STR_MON_PORT_PIFA2SP 13
/* port definititions ISP streaming monitor, monitors the status of streaming ports at the ISP side of the streaming FIFO's */
#define ISP_STR_MON_PORT_ISP2PIFA 0
#define ISP_STR_MON_PORT_PIFA2ISP 1
-#define ISP_STR_MON_PORT_ISP2PIFB 2
+#define ISP_STR_MON_PORT_ISP2PIFB 2
#define ISP_STR_MON_PORT_PIFB2ISP 3
-#define ISP_STR_MON_PORT_ISP2DMA 4
+#define ISP_STR_MON_PORT_ISP2DMA 4
#define ISP_STR_MON_PORT_DMA2ISP 5
-#define ISP_STR_MON_PORT_ISP2GDC1 6
+#define ISP_STR_MON_PORT_ISP2GDC1 6
#define ISP_STR_MON_PORT_GDC12ISP 7
-#define ISP_STR_MON_PORT_ISP2GDC2 8
+#define ISP_STR_MON_PORT_ISP2GDC2 8
#define ISP_STR_MON_PORT_GDC22ISP 9
-#define ISP_STR_MON_PORT_ISP2GPD 10
+#define ISP_STR_MON_PORT_ISP2GPD 10
#define ISP_STR_MON_PORT_FA2ISP 11
-#define ISP_STR_MON_PORT_ISP2SP 12
+#define ISP_STR_MON_PORT_ISP2SP 12
#define ISP_STR_MON_PORT_SP2ISP 13
/* previously used ISP streaming monitor port identifiers, kept for backward compatibility */
#define ISP_STR_MON_PORT_SND_PIF_A ISP_STR_MON_PORT_ISP2PIFA
#define ISP_STR_MON_PORT_RCV_PIF_A ISP_STR_MON_PORT_PIFA2ISP
-#define ISP_STR_MON_PORT_SND_PIF_B ISP_STR_MON_PORT_ISP2PIFB
+#define ISP_STR_MON_PORT_SND_PIF_B ISP_STR_MON_PORT_ISP2PIFB
#define ISP_STR_MON_PORT_RCV_PIF_B ISP_STR_MON_PORT_PIFB2ISP
-#define ISP_STR_MON_PORT_SND_DMA ISP_STR_MON_PORT_ISP2DMA
-#define ISP_STR_MON_PORT_RCV_DMA ISP_STR_MON_PORT_DMA2ISP
-#define ISP_STR_MON_PORT_SND_GDC ISP_STR_MON_PORT_ISP2GDC1
+#define ISP_STR_MON_PORT_SND_DMA ISP_STR_MON_PORT_ISP2DMA
+#define ISP_STR_MON_PORT_RCV_DMA ISP_STR_MON_PORT_DMA2ISP
+#define ISP_STR_MON_PORT_SND_GDC ISP_STR_MON_PORT_ISP2GDC1
#define ISP_STR_MON_PORT_RCV_GDC ISP_STR_MON_PORT_GDC12ISP
-#define ISP_STR_MON_PORT_SND_GPD ISP_STR_MON_PORT_ISP2GPD
+#define ISP_STR_MON_PORT_SND_GPD ISP_STR_MON_PORT_ISP2GPD
#define ISP_STR_MON_PORT_RCV_GPD ISP_STR_MON_PORT_FA2ISP
#define ISP_STR_MON_PORT_SND_SP ISP_STR_MON_PORT_ISP2SP
#define ISP_STR_MON_PORT_RCV_SP ISP_STR_MON_PORT_SP2ISP
-
+
/* port definititions MOD streaming monitor, monitors the status of streaming ports at the module side of the streaming FIFO's */
#define MOD_STR_MON_PORT_PIFA2CELLS 0
#define MOD_STR_MON_PORT_SND_GDC 12
#define MOD_STR_MON_PORT_RCV_GDC 13
-
/* testbench signals: */
/* testbench GP adapter register ids */
#define ISP testbench_isp_isp_css_sec_part_isp
#define SP testbench_isp_isp_css_sec_part_scp
-#define IF_PRIM testbench_isp_isp_css_part_is_2400_ifmt_ift_prim
+#define IF_PRIM testbench_isp_isp_css_part_is_2400_ifmt_ift_prim
#define IF_PRIM_B testbench_isp_isp_css_part_is_2400_ifmt_ift_prim_b
#define IF_SEC testbench_isp_isp_css_part_is_2400_ifmt_ift_sec
#define IF_SEC_MASTER testbench_isp_isp_css_part_is_2400_ifmt_ift_sec_mt_out
#define ISYS2401_IBUF_CNTRL_C testbench_isp_isp_css_part_is_2401_is_pipe_c_ibuf_ctrl
#define ISYS2401_IRQ_CTRL_C testbench_isp_isp_css_part_is_2401_is_pipe_c_irq_ctrl_pipe
-
/* Testbench identifiers */
#define DDR testbench_ddram
#define DDR_SMALL testbench_ddram_small
#include <streaming_to_mipi_defs.h>
-#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS)-1)
-#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS)-1)
+#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS) - 1)
+#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS) - 1)
#define _HIVE_STR_TO_MIPI_FMT_TYPE_LSB (HIVE_STR_TO_MIPI_CH_ID_LSB + HIVE_ISP_CH_ID_BITS)
#define _HIVE_STR_TO_MIPI_DATA_B_LSB (HIVE_STR_TO_MIPI_DATA_A_LSB + HIVE_IF_PIXEL_WIDTH)
-
+
#endif /* _hive_isp_css_streaming_to_mipi_types_hrt_h_ */
* more details.
*/
-#ifndef _HRT_HIVE_TYPES_H
-#define _HRT_HIVE_TYPES_H
+#ifndef _HRT_HIVE_TYPES_H
+#define _HRT_HIVE_TYPES_H
#include "version.h"
#include "defs.h"
#ifndef HRTCAT3
-#define _HRTCAT3(m,n,o) m##n##o
-#define HRTCAT3(m,n,o) _HRTCAT3(m,n,o)
+#define _HRTCAT3(m, n, o) m##n##o
+#define HRTCAT3(m, n, o) _HRTCAT3(m, n, o)
#endif
#ifndef HRTCAT4
-#define _HRTCAT4(m,n,o,p) m##n##o##p
-#define HRTCAT4(m,n,o,p) _HRTCAT4(m,n,o,p)
+#define _HRTCAT4(m, n, o, p) m##n##o##p
+#define HRTCAT4(m, n, o, p) _HRTCAT4(m, n, o, p)
#endif
#ifndef HRTMIN
-#define HRTMIN(a,b) (((a)<(b))?(a):(b))
+#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
-
+
#ifndef HRTMAX
-#define HRTMAX(a,b) (((a)>(b))?(a):(b))
+#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
/* boolean data type */
#define HRT_ADDRESS_WIDTH 32
#endif
-#define HRT_DATA_BYTES (HRT_DATA_WIDTH/8)
-#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH/8)
+#define HRT_DATA_BYTES (HRT_DATA_WIDTH / 8)
+#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH / 8)
#if HRT_DATA_WIDTH == 64
typedef hive_uint64 hrt_data;
#endif
#if HRT_ADDRESS_WIDTH == 64
-typedef hive_uint64 hrt_address;
+typedef hive_uint64 hrt_address;
#elif HRT_ADDRESS_WIDTH == 32
typedef hive_uint32 hrt_address;
#else
typedef hive_uint hive_mmio_id;
typedef hive_mmio_id hive_slave_id;
typedef hive_mmio_id hive_port_id;
-typedef hive_mmio_id hive_master_id;
+typedef hive_mmio_id hive_master_id;
typedef hive_mmio_id hive_mem_id;
typedef hive_mmio_id hive_dev_id;
typedef hive_mmio_id hive_fifo_id;
typedef hive_uint hive_msink_id;
/* HRT specific */
-typedef char* hive_program;
-typedef char* hive_function;
+typedef char *hive_program;
+typedef char *hive_function;
#endif /* _HRT_HIVE_TYPES_H */
#define _IBUF_CNTRL_ACK_TOKEN_ITEMS_BITS _STREAM2MMIO_PACK_NUM_ITEMS_BITS
#define _IBUF_CNTRL_ACK_TOKEN_LSB _IBUF_CNTRL_ACK_TOKEN_STORES_IDX
#define _IBUF_CNTRL_ACK_TOKEN_MSB (_IBUF_CNTRL_ACK_TOKEN_ITEMS_BITS + _IBUF_CNTRL_ACK_TOKEN_ITEMS_IDX - 1)
- /* bit 31 indicates a valid ack: */
+ /* bit 31 indicates a valid ack: */
#define _IBUF_CNTRL_ACK_TOKEN_VALID_BIT (_IBUF_CNTRL_ACK_TOKEN_ITEMS_BITS + _IBUF_CNTRL_ACK_TOKEN_ITEMS_IDX)
-
/*shared registers:*/
#define _IBUF_CNTRL_RECALC_WORDS_STATUS 0
#define _IBUF_CNTRL_ARBITERS_STATUS 1
#define _IBUF_CNTRL_SET_CRUN 2 /* NO PHYSICAL REGISTER!! Only used in HSS model */
-
/*register addresses for each proc: */
#define _IBUF_CNTRL_CMD 0
#define _IBUF_CNTRL_ACK 1
- /* number of items (packets or words) per frame: */
+ /* number of items (packets or words) per frame: */
#define _IBUF_CNTRL_NUM_ITEMS_PER_STORE 2
- /* number of stores (packets or words) per store/buffer: */
+ /* number of stores (packets or words) per store/buffer: */
#define _IBUF_CNTRL_NUM_STORES_PER_FRAME 3
- /* the channel and command in the DMA */
+ /* the channel and command in the DMA */
#define _IBUF_CNTRL_DMA_CHANNEL 4
#define _IBUF_CNTRL_DMA_CMD 5
- /* the start address and stride of the buffers */
+ /* the start address and stride of the buffers */
#define _IBUF_CNTRL_BUFFER_START_ADDRESS 6
#define _IBUF_CNTRL_BUFFER_STRIDE 7
#define _IBUF_CNTRL_BUFFER_END_ADDRESS 8
- /* destination start address, stride and end address; should be the same as in the DMA */
+ /* destination start address, stride and end address; should be the same as in the DMA */
#define _IBUF_CNTRL_DEST_START_ADDRESS 9
#define _IBUF_CNTRL_DEST_STRIDE 10
#define _IBUF_CNTRL_DEST_END_ADDRESS 11
- /* send a frame sync or not, default 1 */
+ /* send a frame sync or not, default 1 */
#define _IBUF_CNTRL_SYNC_FRAME 12
- /* str2mmio cmds */
+ /* str2mmio cmds */
#define _IBUF_CNTRL_STR2MMIO_SYNC_CMD 13
#define _IBUF_CNTRL_STR2MMIO_STORE_CMD 14
- /* num elems p word*/
+ /* num elems p word*/
#define _IBUF_CNTRL_SHIFT_ITEMS 15
#define _IBUF_CNTRL_ELEMS_P_WORD_IBUF 16
#define _IBUF_CNTRL_ELEMS_P_WORD_DEST 17
-
/* STATUS */
- /* current frame and stores in buffer */
+ /* current frame and stores in buffer */
#define _IBUF_CNTRL_CUR_STORES 18
#define _IBUF_CNTRL_CUR_ACKS 19
- /* current buffer and destination address for DMA cmd's */
+ /* current buffer and destination address for DMA cmd's */
#define _IBUF_CNTRL_CUR_S2M_IBUF_ADDR 20
#define _IBUF_CNTRL_CUR_DMA_IBUF_ADDR 21
#define _IBUF_CNTRL_CUR_DMA_DEST_ADDR 22
#define _IBUF_CNTRL_DMA_SYNC_STATE 26
#define _IBUF_CNTRL_ISP_SYNC_STATE 27
-
/*Commands: */
#define _IBUF_CNTRL_CMD_STORE_FRAME_IDX 0
#define _IBUF_CNTRL_CMD_ONLINE_IDX 1
#define _IBUF_CNTRL_CMD_INITIALIZE 0
/* store an online frame (sync with ISP, use end cfg start, stride and end address: */
-#define _IBUF_CNTRL_CMD_STORE_ONLINE_FRAME ((1<<_IBUF_CNTRL_CMD_STORE_FRAME_IDX) | (1<<_IBUF_CNTRL_CMD_ONLINE_IDX))
+#define _IBUF_CNTRL_CMD_STORE_ONLINE_FRAME ((1 << _IBUF_CNTRL_CMD_STORE_FRAME_IDX) | (1 << _IBUF_CNTRL_CMD_ONLINE_IDX))
/* store an offline frame (don't sync with ISP, requires start address as 2nd token, no end address: */
-#define _IBUF_CNTRL_CMD_STORE_OFFLINE_FRAME (1<<_IBUF_CNTRL_CMD_STORE_FRAME_IDX)
+#define _IBUF_CNTRL_CMD_STORE_OFFLINE_FRAME BIT(_IBUF_CNTRL_CMD_STORE_FRAME_IDX)
/* false command token, should be different then commands. Use online bit, not store frame: */
#define _IBUF_CNTRL_FALSE_ACK 2
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_4 4
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_5 5
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_6 6
-#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7
+#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_FSYNC_LUT_REG 8
#define HIVE_IFMT_GP_REGS_SRST_IDX 9
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IDX 10
#define HIVE_ISEL_GP_REGS_SYNCGEN_ENABLE_IDX 0
#define HIVE_ISEL_GP_REGS_SYNCGEN_FREE_RUNNING_IDX 1
#define HIVE_ISEL_GP_REGS_SYNCGEN_PAUSE_IDX 2
-#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_FRAMES_IDX 3
-#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_PIX_IDX 4
-#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_LINES_IDX 5
-#define HIVE_ISEL_GP_REGS_SYNCGEN_HBLANK_CYCLES_IDX 6
-#define HIVE_ISEL_GP_REGS_SYNCGEN_VBLANK_CYCLES_IDX 7
+#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_FRAMES_IDX 3
+#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_PIX_IDX 4
+#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_LINES_IDX 5
+#define HIVE_ISEL_GP_REGS_SYNCGEN_HBLANK_CYCLES_IDX 6
+#define HIVE_ISEL_GP_REGS_SYNCGEN_VBLANK_CYCLES_IDX 7
-#define HIVE_ISEL_GP_REGS_SOF_IDX 8
-#define HIVE_ISEL_GP_REGS_EOF_IDX 9
-#define HIVE_ISEL_GP_REGS_SOL_IDX 10
-#define HIVE_ISEL_GP_REGS_EOL_IDX 11
+#define HIVE_ISEL_GP_REGS_SOF_IDX 8
+#define HIVE_ISEL_GP_REGS_EOF_IDX 9
+#define HIVE_ISEL_GP_REGS_SOL_IDX 10
+#define HIVE_ISEL_GP_REGS_EOL_IDX 11
-#define HIVE_ISEL_GP_REGS_PRBS_ENABLE 12
-#define HIVE_ISEL_GP_REGS_PRBS_ENABLE_PORT_B 13
-#define HIVE_ISEL_GP_REGS_PRBS_LFSR_RESET_VALUE 14
+#define HIVE_ISEL_GP_REGS_PRBS_ENABLE 12
+#define HIVE_ISEL_GP_REGS_PRBS_ENABLE_PORT_B 13
+#define HIVE_ISEL_GP_REGS_PRBS_LFSR_RESET_VALUE 14
-#define HIVE_ISEL_GP_REGS_TPG_ENABLE 15
-#define HIVE_ISEL_GP_REGS_TPG_ENABLE_PORT_B 16
-#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_MASK_IDX 17
-#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_MASK_IDX 18
-#define HIVE_ISEL_GP_REGS_TPG_XY_CNT_MASK_IDX 19
-#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_DELTA_IDX 20
-#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_DELTA_IDX 21
-#define HIVE_ISEL_GP_REGS_TPG_MODE_IDX 22
-#define HIVE_ISEL_GP_REGS_TPG_R1_IDX 23
+#define HIVE_ISEL_GP_REGS_TPG_ENABLE 15
+#define HIVE_ISEL_GP_REGS_TPG_ENABLE_PORT_B 16
+#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_MASK_IDX 17
+#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_MASK_IDX 18
+#define HIVE_ISEL_GP_REGS_TPG_XY_CNT_MASK_IDX 19
+#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_DELTA_IDX 20
+#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_DELTA_IDX 21
+#define HIVE_ISEL_GP_REGS_TPG_MODE_IDX 22
+#define HIVE_ISEL_GP_REGS_TPG_R1_IDX 23
#define HIVE_ISEL_GP_REGS_TPG_G1_IDX 24
#define HIVE_ISEL_GP_REGS_TPG_B1_IDX 25
#define HIVE_ISEL_GP_REGS_TPG_R2_IDX 26
#define HIVE_ISEL_GP_REGS_TPG_G2_IDX 27
#define HIVE_ISEL_GP_REGS_TPG_B2_IDX 28
-
#define HIVE_ISEL_GP_REGS_CH_ID_IDX 29
#define HIVE_ISEL_GP_REGS_FMT_TYPE_IDX 30
#define HIVE_ISEL_GP_REGS_DATA_SEL_IDX 31
#ifndef _input_switch_2400_defs_h
#define _input_switch_2400_defs_h
-#define _HIVE_INPUT_SWITCH_GET_LUT_REG_ID(ch_id, fmt_type) (((ch_id)*2) + ((fmt_type)>=16))
-#define _HIVE_INPUT_SWITCH_GET_LUT_REG_LSB(fmt_type) (((fmt_type)%16) * 2)
+#define _HIVE_INPUT_SWITCH_GET_LUT_REG_ID(ch_id, fmt_type) (((ch_id) * 2) + ((fmt_type) >= 16))
+#define _HIVE_INPUT_SWITCH_GET_LUT_REG_LSB(fmt_type) (((fmt_type) % 16) * 2)
#define HIVE_INPUT_SWITCH_SELECT_NO_OUTPUT 0
#define HIVE_INPUT_SWITCH_SELECT_IF_PRIM 1
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID 20
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID 21
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID 22
-
/* register reset value */
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL 128
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL 128
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL 128
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL 3
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL 3
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL 3
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL 3
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL 3
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL 3
#define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL 0
-#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL 128
-#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3
+#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL 128
+#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3
#define ISYS_CTRL_INIT_REG_RSTVAL 0
-#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
+#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL 0
-#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL 0
+#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL 0
/* register width value */
-#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH 9
-#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH 9
-#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH 9
-#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
-#define ISYS_CTRL_INIT_REG_WIDTH 3
+#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH 9
+#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH 9
+#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH 9
+#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
+#define ISYS_CTRL_INIT_REG_WIDTH 3
#define ISYS_CTRL_LAST_COMMAND_REG_WIDTH 32 /* slave data width */
#define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH 32
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH 32
/*
InpSysCaptFramesAcq 1/0 [3:0] - 'b0000
[7:4] - CaptPortId,
- CaptA-'b0000
- CaptB-'b0001
- CaptC-'b0010
+ CaptA-'b0000
+ CaptB-'b0001
+ CaptC-'b0010
[31:16] - NOF_frames
InpSysCaptFrameExt 2/0 [3:0] - 'b0001'
[7:4] - CaptPortId,
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
2/1 [31:0] - external capture address
-InpSysAcqFrame 2/0 [3:0] - 'b0010,
+InpSysAcqFrame 2/0 [3:0] - 'b0010,
[31:4] - NOF_ext_mem_words
2/1 [31:0] - external memory read start address
-InpSysOverruleON 1/0 [3:0] - 'b0011,
+InpSysOverruleON 1/0 [3:0] - 'b0011,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
-
-InpSysOverruleOFF 1/0 [3:0] - 'b0100,
+InpSysOverruleOFF 1/0 [3:0] - 'b0100,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
-
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
-InpSysOverruleCmd 2/0 [3:0] - 'b0101,
+InpSysOverruleCmd 2/0 [3:0] - 'b0101,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
-
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
2/1 [31:0] - command token value for port opid
-
acknowledge tokens:
InpSysAckCFA 1/0 [3:0] - 'b0000
[7:4] - CaptPortId,
- CaptA-'b0000
- CaptB- 'b0001
- CaptC-'b0010
+ CaptA-'b0000
+ CaptB- 'b0001
+ CaptC-'b0010
[31:16] - NOF_frames
InpSysAckCFE 1/0 [3:0] - 'b0001'
[7:4] - CaptPortId,
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
InpSysAckAF 1/0 [3:0] - 'b0010
-InpSysAckOverruleON 1/0 [3:0] - 'b0011,
+InpSysAckOverruleON 1/0 [3:0] - 'b0011,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
-
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
-InpSysAckOverruleOFF 1/0 [3:0] - 'b0100,
+InpSysAckOverruleOFF 1/0 [3:0] - 'b0100,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
-
-InpSysAckOverrule 2/0 [3:0] - 'b0101,
+InpSysAckOverrule 2/0 [3:0] - 'b0101,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
-
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
2/1 [31:0] - acknowledge token value from port opid
-
-
*/
-
/* Command and acknowledge tokens IDs */
#define ISYS_CTRL_CAPT_FRAMES_ACQ_TOKEN_ID 0 /* 0000b */
#define ISYS_CTRL_CAPT_FRAME_EXT_TOKEN_ID 1 /* 0001b */
#define ISYS_CTRL_TOKEN_ID_IDX 0
#define ISYS_CTRL_TOKEN_ID_BITS (ISYS_CTRL_TOKEN_ID_MSB - ISYS_CTRL_TOKEN_ID_LSB + 1)
#define ISYS_CTRL_PORT_ID_IDX (ISYS_CTRL_TOKEN_ID_IDX + ISYS_CTRL_TOKEN_ID_BITS)
-#define ISYS_CTRL_PORT_ID_BITS (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB +1)
-#define ISYS_CTRL_NOF_CAPT_IDX ISYS_CTRL_NOF_CAPT_TOKEN_LSB
+#define ISYS_CTRL_PORT_ID_BITS (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB + 1)
+#define ISYS_CTRL_NOF_CAPT_IDX ISYS_CTRL_NOF_CAPT_TOKEN_LSB
#define ISYS_CTRL_NOF_CAPT_BITS (ISYS_CTRL_NOF_CAPT_TOKEN_MSB - ISYS_CTRL_NOF_CAPT_TOKEN_LSB + 1)
-#define ISYS_CTRL_NOF_EXT_IDX ISYS_CTRL_NOF_EXT_TOKEN_LSB
+#define ISYS_CTRL_NOF_EXT_IDX ISYS_CTRL_NOF_EXT_TOKEN_LSB
#define ISYS_CTRL_NOF_EXT_BITS (ISYS_CTRL_NOF_EXT_TOKEN_MSB - ISYS_CTRL_NOF_EXT_TOKEN_LSB + 1)
#define ISYS_CTRL_PORT_ID_CAPT_A 0 /* device ID for capture unit A */
#define ISYS_CTRL_PORT_ID_DMA_ACQ 7 /* device ID for dma unit */
#define ISYS_CTRL_NO_ACQ_ACK 16 /* no ack from acquisition unit */
-#define ISYS_CTRL_NO_DMA_ACK 0
+#define ISYS_CTRL_NO_DMA_ACK 0
#define ISYS_CTRL_NO_CAPT_ACK 16
-#endif /* _input_system_ctrl_defs_h */
+#endif /* _input_system_ctrl_defs_h */
#define _HRT_IRQ_CONTROLLER_REG_ALIGN 4
-#endif /* _irq_controller_defs_h */
+#endif /* _irq_controller_defs_h */
#define ISP_SRU_GUARDING 1
#define ISP_VLSU_GUARDING 1
-#define ISP_VRF_RAM 1
-#define ISP_SRF_RAM 1
+#define ISP_VRF_RAM 1
+#define ISP_SRF_RAM 1
#define ISP_SPLIT_VMUL_VADD_IS 0
#define ISP_RFSPLIT_FPGA 0
#define ISP_NWAY ISP_VEC_NELEMS
#define NBITS ISP_VEC_ELEMBITS
-#define _isp_ceil_div(a,b) (((a)+(b)-1)/(b))
+#define _isp_ceil_div(a, b) (((a) + (b) - 1) / (b))
#ifdef C_RUN
-#define ISP_VEC_ALIGN (_isp_ceil_div(ISP_VEC_WIDTH, 64)*8)
+#define ISP_VEC_ALIGN (_isp_ceil_div(ISP_VEC_WIDTH, 64) * 8)
#else
#define ISP_VEC_ALIGN ISP_VMEM_ALIGN
#endif
#define _isp_acquisition_defs_h
#define _ISP_ACQUISITION_REG_ALIGN 4 /* assuming 32 bit control bus width */
-#define _ISP_ACQUISITION_BYTES_PER_ELEM 4
+#define _ISP_ACQUISITION_BYTES_PER_ELEM 4
/* --------------------------------------------------*/
/* REGISTER INFO */
/* --------------------------------------------------*/
-#define NOF_ACQ_REGS 12
+#define NOF_ACQ_REGS 12
// Register id's of MMIO slave accesible registers
-#define ACQ_START_ADDR_REG_ID 0
+#define ACQ_START_ADDR_REG_ID 0
#define ACQ_MEM_REGION_SIZE_REG_ID 1
#define ACQ_NUM_MEM_REGIONS_REG_ID 2
-#define ACQ_INIT_REG_ID 3
+#define ACQ_INIT_REG_ID 3
#define ACQ_RECEIVED_SHORT_PACKETS_REG_ID 4
#define ACQ_RECEIVED_LONG_PACKETS_REG_ID 5
#define ACQ_LAST_COMMAND_REG_ID 6
#define ACQ_NEXT_ACKNOWLEDGE_REG_ID 9
#define ACQ_FSM_STATE_INFO_REG_ID 10
#define ACQ_INT_CNTR_INFO_REG_ID 11
-
+
// Register width
-#define ACQ_START_ADDR_REG_WIDTH 9
-#define ACQ_MEM_REGION_SIZE_REG_WIDTH 9
-#define ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
-#define ACQ_INIT_REG_WIDTH 3
-#define ACQ_RECEIVED_SHORT_PACKETS_REG_WIDTH 32
-#define ACQ_RECEIVED_LONG_PACKETS_REG_WIDTH 32
-#define ACQ_LAST_COMMAND_REG_WIDTH 32
-#define ACQ_NEXT_COMMAND_REG_WIDTH 32
-#define ACQ_LAST_ACKNOWLEDGE_REG_WIDTH 32
-#define ACQ_NEXT_ACKNOWLEDGE_REG_WIDTH 32
-#define ACQ_FSM_STATE_INFO_REG_WIDTH ((MEM2STREAM_FSM_STATE_BITS * 3) + (ACQ_SYNCHRONIZER_FSM_STATE_BITS *3))
+#define ACQ_START_ADDR_REG_WIDTH 9
+#define ACQ_MEM_REGION_SIZE_REG_WIDTH 9
+#define ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
+#define ACQ_INIT_REG_WIDTH 3
+#define ACQ_RECEIVED_SHORT_PACKETS_REG_WIDTH 32
+#define ACQ_RECEIVED_LONG_PACKETS_REG_WIDTH 32
+#define ACQ_LAST_COMMAND_REG_WIDTH 32
+#define ACQ_NEXT_COMMAND_REG_WIDTH 32
+#define ACQ_LAST_ACKNOWLEDGE_REG_WIDTH 32
+#define ACQ_NEXT_ACKNOWLEDGE_REG_WIDTH 32
+#define ACQ_FSM_STATE_INFO_REG_WIDTH ((MEM2STREAM_FSM_STATE_BITS * 3) + (ACQ_SYNCHRONIZER_FSM_STATE_BITS * 3))
#define ACQ_INT_CNTR_INFO_REG_WIDTH 32
/* register reset value */
-#define ACQ_START_ADDR_REG_RSTVAL 0
+#define ACQ_START_ADDR_REG_RSTVAL 0
#define ACQ_MEM_REGION_SIZE_REG_RSTVAL 128
#define ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3
-#define ACQ_INIT_REG_RSTVAL 0
+#define ACQ_INIT_REG_RSTVAL 0
#define ACQ_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0
#define ACQ_RECEIVED_LONG_PACKETS_REG_RSTVAL 0
#define ACQ_LAST_COMMAND_REG_RSTVAL 0
#define ACQ_NEXT_COMMAND_REG_RSTVAL 0
#define ACQ_LAST_ACKNOWLEDGE_REG_RSTVAL 0
-#define ACQ_NEXT_ACKNOWLEDGE_REG_RSTVAL 0
+#define ACQ_NEXT_ACKNOWLEDGE_REG_RSTVAL 0
#define ACQ_FSM_STATE_INFO_REG_RSTVAL 0
-#define ACQ_INT_CNTR_INFO_REG_RSTVAL 0
+#define ACQ_INT_CNTR_INFO_REG_RSTVAL 0
/* bit definitions */
#define ACQ_INIT_RST_REG_BIT 0
/* TOKEN INFO */
/* --------------------------------------------------*/
#define ACQ_TOKEN_ID_LSB 0
-#define ACQ_TOKEN_ID_MSB 3
+#define ACQ_TOKEN_ID_MSB 3
#define ACQ_TOKEN_WIDTH (ACQ_TOKEN_ID_MSB - ACQ_TOKEN_ID_LSB + 1) // 4
#define ACQ_TOKEN_ID_IDX 0
#define ACQ_TOKEN_ID_BITS ACQ_TOKEN_WIDTH
#define ACQ_CMD_START_ADDR_IDX 4
#define ACQ_CMD_START_ADDR_BITS 9
#define ACQ_CMD_NOFWORDS_IDX 13
-#define ACQ_CMD_NOFWORDS_BITS 9
+#define ACQ_CMD_NOFWORDS_BITS 9
#define ACQ_MEM_REGION_ID_IDX 22
-#define ACQ_MEM_REGION_ID_BITS 9
+#define ACQ_MEM_REGION_ID_BITS 9
#define ACQ_PACKET_LENGTH_TOKEN_MSB 21
#define ACQ_PACKET_LENGTH_TOKEN_LSB 13
#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_MSB 9
#define ACQ_PACKET_MEM_REGION_ID_TOKEN_MSB 12 /* only for capt_end_of_packet_written */
#define ACQ_PACKET_MEM_REGION_ID_TOKEN_LSB 4 /* only for capt_end_of_packet_written */
-
/* Command tokens IDs */
#define ACQ_READ_REGION_AUTO_INCR_TOKEN_ID 0 //0000b
#define ACQ_READ_REGION_TOKEN_ID 1 //0001b
-#define ACQ_READ_REGION_SOP_TOKEN_ID 2 //0010b
+#define ACQ_READ_REGION_SOP_TOKEN_ID 2 //0010b
#define ACQ_INIT_TOKEN_ID 8 //1000b
/* Acknowledge token IDs */
#define ACQ_TOKEN_NOFWORDS_MSB 21
#define ACQ_TOKEN_NOFWORDS_LSB 13
#define ACQ_TOKEN_STARTADDR_MSB 12
-#define ACQ_TOKEN_STARTADDR_LSB 4
-
+#define ACQ_TOKEN_STARTADDR_LSB 4
/* --------------------------------------------------*/
/* MIPI */
/* --------------------------------------------------*/
#define WORD_COUNT_WIDTH 16
-#define PKT_CODE_WIDTH 6
-#define CHN_NO_WIDTH 2
+#define PKT_CODE_WIDTH 6
+#define CHN_NO_WIDTH 2
#define ERROR_INFO_WIDTH 8
-
+
#define LONG_PKTCODE_MAX 63
#define LONG_PKTCODE_MIN 16
#define SHORT_PKTCODE_MAX 15
#define ACQ_LINE_PAYLOAD 4
#define ACQ_GEN_SH_PKT 5
-
/* bit definition */
#define ACQ_PKT_TYPE_IDX 16
#define ACQ_PKT_TYPE_BITS 6
#define ACQ_ACK_PKT_LEN_IDX 4
#define ACQ_ACK_PKT_LEN_BITS 16
-
/* --------------------------------------------------*/
/* Packet Data Type */
/* --------------------------------------------------*/
-
#define ACQ_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */
#define ACQ_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */
#define ACQ_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */
#define ACQ_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */
#define ACQ_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */
#define ACQ_RGB444_DATA 32 /* 10 0000 RGB444 */
-#define ACQ_RGB555_DATA 33 /* 10 0001 RGB555 */
-#define ACQ_RGB565_DATA 34 /* 10 0010 RGB565 */
-#define ACQ_RGB666_DATA 35 /* 10 0011 RGB666 */
-#define ACQ_RGB888_DATA 36 /* 10 0100 RGB888 */
-#define ACQ_RAW6_DATA 40 /* 10 1000 RAW6 */
-#define ACQ_RAW7_DATA 41 /* 10 1001 RAW7 */
-#define ACQ_RAW8_DATA 42 /* 10 1010 RAW8 */
-#define ACQ_RAW10_DATA 43 /* 10 1011 RAW10 */
-#define ACQ_RAW12_DATA 44 /* 10 1100 RAW12 */
-#define ACQ_RAW14_DATA 45 /* 10 1101 RAW14 */
-#define ACQ_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
-#define ACQ_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
-#define ACQ_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
-#define ACQ_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
-#define ACQ_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
-#define ACQ_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
-#define ACQ_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
-#define ACQ_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
-#define ACQ_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
-#define ACQ_SOF_DATA 0 /* 00 0000 frame start */
-#define ACQ_EOF_DATA 1 /* 00 0001 frame end */
-#define ACQ_SOL_DATA 2 /* 00 0010 line start */
-#define ACQ_EOL_DATA 3 /* 00 0011 line end */
-#define ACQ_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
-#define ACQ_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
-#define ACQ_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
-#define ACQ_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
-#define ACQ_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
-#define ACQ_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
-#define ACQ_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
-#define ACQ_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
-#define ACQ_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
-#define ACQ_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
+#define ACQ_RGB555_DATA 33 /* 10 0001 RGB555 */
+#define ACQ_RGB565_DATA 34 /* 10 0010 RGB565 */
+#define ACQ_RGB666_DATA 35 /* 10 0011 RGB666 */
+#define ACQ_RGB888_DATA 36 /* 10 0100 RGB888 */
+#define ACQ_RAW6_DATA 40 /* 10 1000 RAW6 */
+#define ACQ_RAW7_DATA 41 /* 10 1001 RAW7 */
+#define ACQ_RAW8_DATA 42 /* 10 1010 RAW8 */
+#define ACQ_RAW10_DATA 43 /* 10 1011 RAW10 */
+#define ACQ_RAW12_DATA 44 /* 10 1100 RAW12 */
+#define ACQ_RAW14_DATA 45 /* 10 1101 RAW14 */
+#define ACQ_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
+#define ACQ_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
+#define ACQ_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
+#define ACQ_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
+#define ACQ_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
+#define ACQ_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
+#define ACQ_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
+#define ACQ_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
+#define ACQ_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
+#define ACQ_SOF_DATA 0 /* 00 0000 frame start */
+#define ACQ_EOF_DATA 1 /* 00 0001 frame end */
+#define ACQ_SOL_DATA 2 /* 00 0010 line start */
+#define ACQ_EOL_DATA 3 /* 00 0011 line end */
+#define ACQ_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
+#define ACQ_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
+#define ACQ_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
+#define ACQ_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
+#define ACQ_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
+#define ACQ_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
+#define ACQ_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
+#define ACQ_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
+#define ACQ_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
+#define ACQ_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
#define ACQ_RESERVED_DATA_TYPE_MIN 56
#define ACQ_RESERVED_DATA_TYPE_MAX 63
#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MIN 19
/* --------------------------------------------------*/
-#endif /* _isp_acquisition_defs_h */
+#endif /* _isp_acquisition_defs_h */
#define _isp_capture_defs_h
#define _ISP_CAPTURE_REG_ALIGN 4 /* assuming 32 bit control bus width */
-#define _ISP_CAPTURE_BITS_PER_ELEM 32 /* only for data, not SOP */
-#define _ISP_CAPTURE_BYTES_PER_ELEM (_ISP_CAPTURE_BITS_PER_ELEM/8 )
-#define _ISP_CAPTURE_BYTES_PER_WORD 32 /* 256/8 */
-#define _ISP_CAPTURE_ELEM_PER_WORD _ISP_CAPTURE_BYTES_PER_WORD / _ISP_CAPTURE_BYTES_PER_ELEM
+#define _ISP_CAPTURE_BITS_PER_ELEM 32 /* only for data, not SOP */
+#define _ISP_CAPTURE_BYTES_PER_ELEM (_ISP_CAPTURE_BITS_PER_ELEM / 8)
+#define _ISP_CAPTURE_BYTES_PER_WORD 32 /* 256/8 */
+#define _ISP_CAPTURE_ELEM_PER_WORD _ISP_CAPTURE_BYTES_PER_WORD / _ISP_CAPTURE_BYTES_PER_ELEM
//#define CAPT_RCV_ACK 1
-//#define CAPT_WRT_ACK 2
-//#define CAPT_IRQ_ACK 3
+//#define CAPT_WRT_ACK 2
+//#define CAPT_IRQ_ACK 3
/* --------------------------------------------------*/
// Register id's of MMIO slave accesible registers
#define CAPT_START_MODE_REG_ID 0
-#define CAPT_START_ADDR_REG_ID 1
-#define CAPT_MEM_REGION_SIZE_REG_ID 2
-#define CAPT_NUM_MEM_REGIONS_REG_ID 3
-#define CAPT_INIT_REG_ID 4
+#define CAPT_START_ADDR_REG_ID 1
+#define CAPT_MEM_REGION_SIZE_REG_ID 2
+#define CAPT_NUM_MEM_REGIONS_REG_ID 3
+#define CAPT_INIT_REG_ID 4
#define CAPT_START_REG_ID 5
-#define CAPT_STOP_REG_ID 6
+#define CAPT_STOP_REG_ID 6
#define CAPT_PACKET_LENGTH_REG_ID 7
-#define CAPT_RECEIVED_LENGTH_REG_ID 8
-#define CAPT_RECEIVED_SHORT_PACKETS_REG_ID 9
-#define CAPT_RECEIVED_LONG_PACKETS_REG_ID 10
-#define CAPT_LAST_COMMAND_REG_ID 11
+#define CAPT_RECEIVED_LENGTH_REG_ID 8
+#define CAPT_RECEIVED_SHORT_PACKETS_REG_ID 9
+#define CAPT_RECEIVED_LONG_PACKETS_REG_ID 10
+#define CAPT_LAST_COMMAND_REG_ID 11
#define CAPT_NEXT_COMMAND_REG_ID 12
#define CAPT_LAST_ACKNOWLEDGE_REG_ID 13
#define CAPT_NEXT_ACKNOWLEDGE_REG_ID 14
#define CAPT_FSM_STATE_INFO_REG_ID 15
// Register width
-#define CAPT_START_MODE_REG_WIDTH 1
+#define CAPT_START_MODE_REG_WIDTH 1
//#define CAPT_START_ADDR_REG_WIDTH 9
//#define CAPT_MEM_REGION_SIZE_REG_WIDTH 9
//#define CAPT_NUM_MEM_REGIONS_REG_WIDTH 9
#define CAPT_WRITE2MEM_FSM_STATE_BITS 2
#define CAPT_SYNCHRONIZER_FSM_STATE_BITS 3
-
#define CAPT_PACKET_LENGTH_REG_WIDTH 17
-#define CAPT_RECEIVED_LENGTH_REG_WIDTH 17
+#define CAPT_RECEIVED_LENGTH_REG_WIDTH 17
#define CAPT_RECEIVED_SHORT_PACKETS_REG_WIDTH 32
#define CAPT_RECEIVED_LONG_PACKETS_REG_WIDTH 32
#define CAPT_LAST_COMMAND_REG_WIDTH 32
-/* #define CAPT_NEXT_COMMAND_REG_WIDTH 32 */
+/* #define CAPT_NEXT_COMMAND_REG_WIDTH 32 */
#define CAPT_LAST_ACKNOWLEDGE_REG_WIDTH 32
#define CAPT_NEXT_ACKNOWLEDGE_REG_WIDTH 32
#define CAPT_FSM_STATE_INFO_REG_WIDTH ((CAPT_WRITE2MEM_FSM_STATE_BITS * 3) + (CAPT_SYNCHRONIZER_FSM_STATE_BITS * 3))
-//#define CAPT_INIT_RESTART_MEM_ADDR_WIDTH 9
-//#define CAPT_INIT_RESTART_MEM_REGION_WIDTH 9
+//#define CAPT_INIT_RESTART_MEM_ADDR_WIDTH 9
+//#define CAPT_INIT_RESTART_MEM_REGION_WIDTH 9
/* register reset value */
-#define CAPT_START_MODE_REG_RSTVAL 0
+#define CAPT_START_MODE_REG_RSTVAL 0
#define CAPT_START_ADDR_REG_RSTVAL 0
#define CAPT_MEM_REGION_SIZE_REG_RSTVAL 128
-#define CAPT_NUM_MEM_REGIONS_REG_RSTVAL 3
+#define CAPT_NUM_MEM_REGIONS_REG_RSTVAL 3
#define CAPT_INIT_REG_RSTVAL 0
#define CAPT_START_REG_RSTVAL 0
#define CAPT_INIT_RESTART_MEM_REGION_LSB 15
#define CAPT_INIT_RESTART_MEM_REGION_MSB 25
-
#define CAPT_INIT_RST_REG_IDX CAPT_INIT_RST_REG_BIT
#define CAPT_INIT_RST_REG_BITS 1
#define CAPT_INIT_FLUSH_IDX CAPT_INIT_FLUSH_BIT
#define CAPT_INIT_RESYNC_IDX CAPT_INIT_RESYNC_BIT
#define CAPT_INIT_RESYNC_BITS 1
#define CAPT_INIT_RESTART_IDX CAPT_INIT_RESTART_BIT
-#define CAPT_INIT_RESTART_BITS 1
+#define CAPT_INIT_RESTART_BITS 1
#define CAPT_INIT_RESTART_MEM_ADDR_IDX CAPT_INIT_RESTART_MEM_ADDR_LSB
#define CAPT_INIT_RESTART_MEM_ADDR_BITS (CAPT_INIT_RESTART_MEM_ADDR_MSB - CAPT_INIT_RESTART_MEM_ADDR_LSB + 1)
#define CAPT_INIT_RESTART_MEM_REGION_IDX CAPT_INIT_RESTART_MEM_REGION_LSB
#define CAPT_INIT_RESTART_MEM_REGION_BITS (CAPT_INIT_RESTART_MEM_REGION_MSB - CAPT_INIT_RESTART_MEM_REGION_LSB + 1)
-
-
/* --------------------------------------------------*/
/* TOKEN INFO */
/* --------------------------------------------------*/
#define CAPT_TOKEN_ID_LSB 0
-#define CAPT_TOKEN_ID_MSB 3
+#define CAPT_TOKEN_ID_MSB 3
#define CAPT_TOKEN_WIDTH (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1) /* 4 */
/* Command tokens IDs */
#define CAPT_START_TOKEN_ID 0 /* 0000b */
#define CAPT_STOP_TOKEN_ID 1 /* 0001b */
-#define CAPT_FREEZE_TOKEN_ID 2 /* 0010b */
+#define CAPT_FREEZE_TOKEN_ID 2 /* 0010b */
#define CAPT_RESUME_TOKEN_ID 3 /* 0011b */
#define CAPT_INIT_TOKEN_ID 8 /* 1000b */
-#define CAPT_START_TOKEN_BIT 0
+#define CAPT_START_TOKEN_BIT 0
#define CAPT_STOP_TOKEN_BIT 0
#define CAPT_FREEZE_TOKEN_BIT 0
#define CAPT_RESUME_TOKEN_BIT 0
#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB 20
#define CAPT_PACKET_CH_ID_TOKEN_MSB 27
#define CAPT_PACKET_CH_ID_TOKEN_LSB 26
-#define CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB 29
-#define CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB 21
+#define CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB 29
+#define CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB 21
/* bit definition */
#define CAPT_CMD_IDX CAPT_TOKEN_ID_LSB
#define CAPT_INIT_TOKEN_INIT_IDX 4
#define CAPT_INIT_TOKEN_INIT_BITS 22
-
/* --------------------------------------------------*/
/* MIPI */
/* --------------------------------------------------*/
-#define CAPT_WORD_COUNT_WIDTH 16
-#define CAPT_PKT_CODE_WIDTH 6
-#define CAPT_CHN_NO_WIDTH 2
-#define CAPT_ERROR_INFO_WIDTH 8
+#define CAPT_WORD_COUNT_WIDTH 16
+#define CAPT_PKT_CODE_WIDTH 6
+#define CAPT_CHN_NO_WIDTH 2
+#define CAPT_ERROR_INFO_WIDTH 8
#define LONG_PKTCODE_MAX 63
#define LONG_PKTCODE_MIN 16
#define SHORT_PKTCODE_MAX 15
-
/* --------------------------------------------------*/
/* Packet Info */
/* --------------------------------------------------*/
#define CAPT_LINE_PAYLOAD 4
#define CAPT_GEN_SH_PKT 5
-
/* --------------------------------------------------*/
/* Packet Data Type */
/* --------------------------------------------------*/
#define CAPT_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */
#define CAPT_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */
#define CAPT_RGB444_DATA 32 /* 10 0000 RGB444 */
-#define CAPT_RGB555_DATA 33 /* 10 0001 RGB555 */
-#define CAPT_RGB565_DATA 34 /* 10 0010 RGB565 */
-#define CAPT_RGB666_DATA 35 /* 10 0011 RGB666 */
-#define CAPT_RGB888_DATA 36 /* 10 0100 RGB888 */
-#define CAPT_RAW6_DATA 40 /* 10 1000 RAW6 */
-#define CAPT_RAW7_DATA 41 /* 10 1001 RAW7 */
-#define CAPT_RAW8_DATA 42 /* 10 1010 RAW8 */
-#define CAPT_RAW10_DATA 43 /* 10 1011 RAW10 */
-#define CAPT_RAW12_DATA 44 /* 10 1100 RAW12 */
-#define CAPT_RAW14_DATA 45 /* 10 1101 RAW14 */
-#define CAPT_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
-#define CAPT_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
-#define CAPT_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
-#define CAPT_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
-#define CAPT_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
-#define CAPT_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
-#define CAPT_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
-#define CAPT_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
-#define CAPT_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
-#define CAPT_SOF_DATA 0 /* 00 0000 frame start */
-#define CAPT_EOF_DATA 1 /* 00 0001 frame end */
-#define CAPT_SOL_DATA 2 /* 00 0010 line start */
-#define CAPT_EOL_DATA 3 /* 00 0011 line end */
-#define CAPT_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
-#define CAPT_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
-#define CAPT_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
-#define CAPT_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
-#define CAPT_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
-#define CAPT_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
-#define CAPT_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
-#define CAPT_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
-#define CAPT_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
-#define CAPT_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
+#define CAPT_RGB555_DATA 33 /* 10 0001 RGB555 */
+#define CAPT_RGB565_DATA 34 /* 10 0010 RGB565 */
+#define CAPT_RGB666_DATA 35 /* 10 0011 RGB666 */
+#define CAPT_RGB888_DATA 36 /* 10 0100 RGB888 */
+#define CAPT_RAW6_DATA 40 /* 10 1000 RAW6 */
+#define CAPT_RAW7_DATA 41 /* 10 1001 RAW7 */
+#define CAPT_RAW8_DATA 42 /* 10 1010 RAW8 */
+#define CAPT_RAW10_DATA 43 /* 10 1011 RAW10 */
+#define CAPT_RAW12_DATA 44 /* 10 1100 RAW12 */
+#define CAPT_RAW14_DATA 45 /* 10 1101 RAW14 */
+#define CAPT_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
+#define CAPT_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
+#define CAPT_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
+#define CAPT_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
+#define CAPT_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
+#define CAPT_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
+#define CAPT_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
+#define CAPT_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
+#define CAPT_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
+#define CAPT_SOF_DATA 0 /* 00 0000 frame start */
+#define CAPT_EOF_DATA 1 /* 00 0001 frame end */
+#define CAPT_SOL_DATA 2 /* 00 0010 line start */
+#define CAPT_EOL_DATA 3 /* 00 0011 line end */
+#define CAPT_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
+#define CAPT_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
+#define CAPT_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
+#define CAPT_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
+#define CAPT_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
+#define CAPT_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
+#define CAPT_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
+#define CAPT_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
+#define CAPT_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
+#define CAPT_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
#define CAPT_RESERVED_DATA_TYPE_MIN 56
#define CAPT_RESERVED_DATA_TYPE_MAX 63
#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MIN 19
#define CAPT_RAW_RESERVED_DATA_TYPE_MIN 46
#define CAPT_RAW_RESERVED_DATA_TYPE_MAX 47
-
/* --------------------------------------------------*/
/* Capture Unit State */
/* --------------------------------------------------*/
#define CAPT_FREEZE 5
#define CAPT_RUN 6
-
/* --------------------------------------------------*/
-#endif /* _isp_capture_defs_h */
-
-
-
-
-
+#endif /* _isp_capture_defs_h */
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH 2
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH 3
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH (_HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH)
-#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */
+#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */
/* Definition of data format ID at the interface CSS_receiver capture/acquisition units */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8_CSPS 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10_CSPS 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
/* used reserved mipi positions for these */
-#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46
-#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47
-#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37
-#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38
+#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46
+#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47
+#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37
+#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38
//_HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 63
#define _HRT_MIPI_BACKEND_FMT_TYPE_CUSTOM 63
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB444 2 // 32
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB565 3 // 34
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB666 4 // 35
-#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42
+#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW10 6 // 43
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW6 7 // 40
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW7 8 // 41
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18 28 // ?
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_2 29 // ? Option 2 for depacketiser
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_3 30 // ? Option 3 for depacketiser
-#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding
+#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding
/* definition for state machine of data FIFO for decode different type of data */
-#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1
+#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV420_10_REPEAT_PTN 5
#define _HRT_CSS_RECEIVER_2400_YUV420_8L_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV422_8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV422_10_REPEAT_PTN 5
-#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2
+#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB555_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB565_REPEAT_PTN 2
-#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9
+#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9
#define _HRT_CSS_RECEIVER_2400_RGB888_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW6_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW7_REPEAT_PTN 7
#define _HRT_CSS_RECEIVER_2400_RAW8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_RAW10_REPEAT_PTN 5
-#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3
+#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW14_REPEAT_PTN 7
#define _HRT_CSS_RECEIVER_2400_MAX_REPEAT_PTN _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_7_12 5
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_8_12 6
-
/* packet bit definition */
#define _HRT_CSS_RECEIVER_2400_PKT_SOP_IDX 32
#define _HRT_CSS_RECEIVER_2400_PKT_SOP_BITS 1
#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_IDX 0
#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_BITS 32
-
/*************************************************************************************************/
/* Custom Decoding */
/* These Custom Defs are defined based on design-time config in "mipi_backend_pixel_formatter.chdl" !! */
/*************************************************************************************************/
/*
-#define BE_CUST_EN_IDX 0 // 2bits
-#define BE_CUST_EN_DATAID_IDX 2 // 6bits MIPI DATA ID
-#define BE_CUST_EN_WIDTH 8
-#define BE_CUST_MODE_ALL 1 // Enable Custom Decoding for all DATA IDs
-#define BE_CUST_MODE_ONE 3 // Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID
+#define BE_CUST_EN_IDX 0 // 2bits
+#define BE_CUST_EN_DATAID_IDX 2 // 6bits MIPI DATA ID
+#define BE_CUST_EN_WIDTH 8
+#define BE_CUST_MODE_ALL 1 // Enable Custom Decoding for all DATA IDs
+#define BE_CUST_MODE_ONE 3 // Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID
// Data State config = {get_bits(6bits), valid(1bit)} //
#define BE_CUST_DATA_STATE_S0_IDX 0 // 7bits
-#define BE_CUST_DATA_STATE_S1_IDX 8 //7 // 7bits
+#define BE_CUST_DATA_STATE_S1_IDX 8 //7 // 7bits
#define BE_CUST_DATA_STATE_S2_IDX 16//14 // 7bits /
-#define BE_CUST_DATA_STATE_WIDTH 24//21
-#define BE_CUST_DATA_STATE_VALID_IDX 0 // 1bits
-#define BE_CUST_DATA_STATE_GETBITS_IDX 1 // 6bits
-
-
-
+#define BE_CUST_DATA_STATE_WIDTH 24//21
+#define BE_CUST_DATA_STATE_VALID_IDX 0 // 1bits
+#define BE_CUST_DATA_STATE_GETBITS_IDX 1 // 6bits
-// Pixel Extractor config
-#define BE_CUST_PIX_EXT_DATA_ALIGN_IDX 0 // 6bits
-#define BE_CUST_PIX_EXT_PIX_ALIGN_IDX 6//5 // 5bits
+// Pixel Extractor config
+#define BE_CUST_PIX_EXT_DATA_ALIGN_IDX 0 // 6bits
+#define BE_CUST_PIX_EXT_PIX_ALIGN_IDX 6//5 // 5bits
#define BE_CUST_PIX_EXT_PIX_MASK_IDX 11//10 // 18bits
#define BE_CUST_PIX_EXT_PIX_EN_IDX 29 //28 // 1bits
-#define BE_CUST_PIX_EXT_WIDTH 30//29
+#define BE_CUST_PIX_EXT_WIDTH 30//29
-// Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)}
-#define BE_CUST_PIX_VALID_EOP_P0_IDX 0 // 4bits
-#define BE_CUST_PIX_VALID_EOP_P1_IDX 4 // 4bits
-#define BE_CUST_PIX_VALID_EOP_P2_IDX 8 // 4bits
-#define BE_CUST_PIX_VALID_EOP_P3_IDX 12 // 4bits
-#define BE_CUST_PIX_VALID_EOP_WIDTH 16
+// Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)}
+#define BE_CUST_PIX_VALID_EOP_P0_IDX 0 // 4bits
+#define BE_CUST_PIX_VALID_EOP_P1_IDX 4 // 4bits
+#define BE_CUST_PIX_VALID_EOP_P2_IDX 8 // 4bits
+#define BE_CUST_PIX_VALID_EOP_P3_IDX 12 // 4bits
+#define BE_CUST_PIX_VALID_EOP_WIDTH 16
#define BE_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 // Normal (NO less get_bits case) Valid - 1bits
-#define BE_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 // Normal (NO less get_bits case) EoP - 1bits
-#define BE_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 // Especial (less get_bits case) Valid - 1bits
+#define BE_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 // Normal (NO less get_bits case) EoP - 1bits
+#define BE_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 // Especial (less get_bits case) Valid - 1bits
#define BE_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 // Especial (less get_bits case) EoP - 1bits
*/
#endif /* _mipi_backend_common_defs_h_ */
-#endif /* _css_receiver_2400_common_defs_h_ */
+#endif /* _css_receiver_2400_common_defs_h_ */
#include "mipi_backend_common_defs.h"
-#define MIPI_BACKEND_REG_ALIGN 4 // assuming 32 bit control bus width
+#define MIPI_BACKEND_REG_ALIGN 4 // assuming 32 bit control bus width
-#define _HRT_MIPI_BACKEND_NOF_IRQS 3 // sid_lut
+#define _HRT_MIPI_BACKEND_NOF_IRQS 3 // sid_lut
// SH Backend Register IDs
-#define _HRT_MIPI_BACKEND_ENABLE_REG_IDX 0
-#define _HRT_MIPI_BACKEND_STATUS_REG_IDX 1
+#define _HRT_MIPI_BACKEND_ENABLE_REG_IDX 0
+#define _HRT_MIPI_BACKEND_STATUS_REG_IDX 1
//#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_IDX 2
#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX 2
#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG1_IDX 3
#define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX 9
#define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_IDX 10
////
-#define _HRT_MIPI_BACKEND_CUST_EN_REG_IDX 11
+#define _HRT_MIPI_BACKEND_CUST_EN_REG_IDX 11
#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX 12
#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX 13
#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P1_REG_IDX 14
#define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX 26
#define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX 27
//#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_IDX 28
-#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX 28
-#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_IDX 29
-#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_IDX 30
-#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_IDX 31
+#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX 28
+#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_IDX 29
+#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_IDX 30
+#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_IDX 31
#define _HRT_MIPI_BACKEND_NOF_REGISTERS 32 // excluding the LP LUT entries
#define _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX 32
-
/////////////////////////////////////////////////////////////////////////////////////////////////////
-#define _HRT_MIPI_BACKEND_ENABLE_REG_WIDTH 1
-#define _HRT_MIPI_BACKEND_STATUS_REG_WIDTH 1
+#define _HRT_MIPI_BACKEND_ENABLE_REG_WIDTH 1
+#define _HRT_MIPI_BACKEND_STATUS_REG_WIDTH 1
//#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_WIDTH 1
#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG_WIDTH 32
-#define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_WIDTH 7
+#define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_WIDTH 7
#define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_WIDTH 9
#define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_WIDTH 8
#define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_WIDTH _HRT_MIPI_BACKEND_NOF_IRQS
-#define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_WIDTH 0
+#define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_WIDTH 0
#define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_WIDTH 1
-#define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_WIDTH 1+2+6
+#define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_WIDTH 1 + 2 + 6
//#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_WIDTH 1
-//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_WIDTH 7
-//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_WIDTH 7
-//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_WIDTH 7
-//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_WIDTH 7
+//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_WIDTH 7
+//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_WIDTH 7
+//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_WIDTH 7
+//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_WIDTH 7
/////////////////////////////////////////////////////////////////////////////////////////////////////
#define _HRT_MIPI_BACKEND_NOF_SP_LUT_ENTRIES 4
//#define _HRT_MIPI_BACKEND_MAX_NOF_LP_LUT_ENTRIES 16 // to satisfy hss model static array declaration
-
#define _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH 2
#define _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH 6
/* These Custom Defs are defined based on design-time config in "mipi_backend_pixel_formatter.chdl" !! */
/*************************************************************************************************/
#define _HRT_MIPI_BACKEND_CUST_EN_IDX 0 /* 2bits */
-#define _HRT_MIPI_BACKEND_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */
+#define _HRT_MIPI_BACKEND_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */
#define _HRT_MIPI_BACKEND_CUST_EN_HIGH_PREC_IDX 8 // 1 bit
-#define _HRT_MIPI_BACKEND_CUST_EN_WIDTH 9
+#define _HRT_MIPI_BACKEND_CUST_EN_WIDTH 9
#define _HRT_MIPI_BACKEND_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */
#define _HRT_MIPI_BACKEND_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */
-#define _HRT_MIPI_BACKEND_CUST_EN_OPTION_IDX 1
+#define _HRT_MIPI_BACKEND_CUST_EN_OPTION_IDX 1
/* Data State config = {get_bits(6bits), valid(1bit)} */
-#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S0_IDX 0 /* 7bits */
-#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S1_IDX 8 /* 7bits */
+#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S0_IDX 0 /* 7bits */
+#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S1_IDX 8 /* 7bits */
#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S2_IDX 16 /* was 14 7bits */
#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_WIDTH 24 /* was 21*/
#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */
#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */
#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */
#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */
-#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_WIDTH 16
+#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_WIDTH 16
#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */
#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */
#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */
#define HRT_MIPI_BACKEND_STREAM_EOF_BIT 2
#define HRT_MIPI_BACKEND_STREAM_SOF_BIT 3
#define HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT 4
-#define HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT+(sid_width)-1)
-#define HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width,p) (HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width)+1+p)
+#define HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT + (sid_width) - 1)
+#define HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width, p) (HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width) + 1 + p)
-#define HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width,ppc,pix_width,p) (HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width,ppc)+ ((pix_width)*p))
-#define HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width,ppc,pix_width,p) (HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width,ppc,pix_width,p) + (pix_width) - 1)
+#define HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, p) (HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width, ppc) + ((pix_width) * p))
+#define HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width, ppc, pix_width, p) (HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, p) + (pix_width) - 1)
#if 0
//#define HRT_MIPI_BACKEND_STREAM_PIX_BITS 14
//#define HRT_MIPI_BACKEND_STREAM_PPC 4
#endif
-#define HRT_MIPI_BACKEND_STREAM_BITS(sid_width,ppc,pix_width) (HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width,ppc,pix_width,(ppc-1))+1)
-
+#define HRT_MIPI_BACKEND_STREAM_BITS(sid_width, ppc, pix_width) (HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width, ppc, pix_width, (ppc - 1)) + 1)
/* SP and LP LUT BIT POSITIONS */
-#define HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT 0 // 0
-#define HRT_MIPI_BACKEND_LUT_SID_LS_BIT HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT + 1 // 1
-#define HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_LUT_SID_LS_BIT+(sid_width)-1) // 1 + (4) - 1 = 4
+#define HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT 0 // 0
+#define HRT_MIPI_BACKEND_LUT_SID_LS_BIT HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT + 1 // 1
+#define HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_LUT_SID_LS_BIT + (sid_width) - 1) // 1 + (4) - 1 = 4
#define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_LS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) + 1 // 5
#define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_LS_BIT(sid_width) + _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH - 1 // 6
#define HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) + 1 // 7
-#define HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) + _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH - 1 // 12
+#define HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) + _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH - 1 // 12
/* #define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) + 1 // 7 */
-#define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) + 1
+#define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) + 1
#define HRT_MIPI_BACKEND_LP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) + 1 // 13
-
// temp solution
-//#define HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT + 1 // 8
+//#define HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT + 1 // 8
//#define HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT + 1 // 9
//#define HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT + 1 // 10
//#define HRT_MIPI_BACKEND_STREAM_PIXD_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT + 1 // 11
//#define HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 53
//#define HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT + 1 // 54
//#define HRT_MIPI_BACKEND_STREAM_PIXD_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 67
-
-// vc hidden in pixb data (passed as raw12 the pipe)
-#define HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width,ppc,pix_width) HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width,ppc,pix_width,1) + 10 //HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT + 10 // 36
-#define HRT_MIPI_BACKEND_STREAM_VC_MS_BIT(sid_width,ppc,pix_width) HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width,ppc,pix_width) + 1 // 37
-
-
+// vc hidden in pixb data (passed as raw12 the pipe)
+#define HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width, ppc, pix_width) HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, 1) + 10 //HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT + 10 // 36
+#define HRT_MIPI_BACKEND_STREAM_VC_MS_BIT(sid_width, ppc, pix_width) HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width, ppc, pix_width) + 1 // 37
#endif /* _mipi_backend_defs_h */
//#include "rx_csi_common_defs.h"
-
-
#define MIPI_PKT_DATA_WIDTH 32
//#define CLK_CROSSING_FIFO_DEPTH 16
#define _CSI_RX_REG_ALIGN 4
// REGISTER DESCRIPTION
//#define _HRT_CSI_RX_SOFTRESET_REG_IDX 0
#define _HRT_CSI_RX_ENABLE_REG_IDX 0
-#define _HRT_CSI_RX_NOF_ENABLED_LANES_REG_IDX 1
+#define _HRT_CSI_RX_NOF_ENABLED_LANES_REG_IDX 1
#define _HRT_CSI_RX_ERROR_HANDLING_REG_IDX 2
-#define _HRT_CSI_RX_STATUS_REG_IDX 3
-#define _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX 4
-#define _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX 5
-//#define _HRT_CSI_RX_IRQ_CONFIG_REG_IDX 6
+#define _HRT_CSI_RX_STATUS_REG_IDX 3
+#define _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX 4
+#define _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX 5
+//#define _HRT_CSI_RX_IRQ_CONFIG_REG_IDX 6
#define _HRT_CSI_RX_DLY_CNT_TERMEN_CLANE_REG_IDX 6
#define _HRT_CSI_RX_DLY_CNT_SETTLE_CLANE_REG_IDX 7
-#define _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane_idx) (8+(2*lane_idx))
-#define _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane_idx) (8+(2*lane_idx)+1)
-
-#define _HRT_CSI_RX_NOF_REGISTERS(nof_dlanes) (8+2*(nof_dlanes))
+#define _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane_idx) (8 + (2 * lane_idx))
+#define _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane_idx) (8 + (2 * lane_idx) + 1)
+#define _HRT_CSI_RX_NOF_REGISTERS(nof_dlanes) (8 + 2 * (nof_dlanes))
//#define _HRT_CSI_RX_SOFTRESET_REG_WIDTH 1
#define _HRT_CSI_RX_ENABLE_REG_WIDTH 1
#define _HRT_CSI_RX_NOF_ENABLED_LANES_REG_WIDTH 3
-#define _HRT_CSI_RX_ERROR_HANDLING_REG_WIDTH 4
-#define _HRT_CSI_RX_STATUS_REG_WIDTH 1
-#define _HRT_CSI_RX_STATUS_DLANE_HS_REG_WIDTH 8
+#define _HRT_CSI_RX_ERROR_HANDLING_REG_WIDTH 4
+#define _HRT_CSI_RX_STATUS_REG_WIDTH 1
+#define _HRT_CSI_RX_STATUS_DLANE_HS_REG_WIDTH 8
#define _HRT_CSI_RX_STATUS_DLANE_LP_REG_WIDTH 24
#define _HRT_CSI_RX_IRQ_CONFIG_REG_WIDTH (CSI_RX_NOF_IRQS_ISP_DOMAIN)
#define _HRT_CSI_RX_DLY_CNT_REG_WIDTH 24
-//#define _HRT_CSI_RX_IRQ_STATUS_REG_WIDTH NOF_IRQS
+//#define _HRT_CSI_RX_IRQ_STATUS_REG_WIDTH NOF_IRQS
//#define _HRT_CSI_RX_IRQ_CLEAR_REG_WIDTH 0
-
#define ONE_LANE_ENABLED 0
#define TWO_LANES_ENABLED 1
-#define THREE_LANES_ENABLED 2
+#define THREE_LANES_ENABLED 2
#define FOUR_LANES_ENABLED 3
// Error handling reg bit positions
#define _HRT_CSI_RX_IRQ_CONFIG_REG_VAL_POSEDGE 0
#define _HRT_CSI_RX_IRQ_CONFIG_REG_VAL_ORIGINAL 1
-// Interrupt bits
+// Interrupt bits
#define _HRT_RX_CSI_IRQ_SINGLE_PH_ERROR_CORRECTED 0
#define _HRT_RX_CSI_IRQ_MULTIPLE_PH_ERROR_DETECTED 1
#define _HRT_RX_CSI_IRQ_PAYLOAD_CHECKSUM_ERROR 2
#define _HRT_RX_CSI_IRQ_ERR_LINE_SYNC_BIT 16
*/
-
////Bit Description for reg _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX
#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE0 0
#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE1 1
#define _HRT_RX_CSI_DATA_FORMAT_ID_SOL 2 /* 00 0010 line start */
#define _HRT_RX_CSI_DATA_FORMAT_ID_EOL 3 /* 00 0011 line end */
-
-#endif /* _csi_rx_defs_h */
+#endif /* _csi_rx_defs_h */
#define _STREAM2MMIO_START_ADDR_REG_ID 3 /* master port address,NOT Byte */
#define _STREAM2MMIO_END_ADDR_REG_ID 4 /* master port address,NOT Byte */
#define _STREAM2MMIO_STRIDE_REG_ID 5 /* stride in master port words, increment is per packet for long sids, stride is not used for short sid's*/
-#define _STREAM2MMIO_NUM_ITEMS_REG_ID 6 /* number of packets for store packets cmd, number of words for store_words cmd */
+#define _STREAM2MMIO_NUM_ITEMS_REG_ID 6 /* number of packets for store packets cmd, number of words for store_words cmd */
#define _STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID 7 /* if this register is 1, input will be stalled if there is no pending command for this sid */
#define _STREAM2MMIO_REGS_PER_SID 8
#define _STREAM2MMIO_CMD_TOKEN_CMD_LSB 0 /* bits 1-0 is for the command field */
#define _STREAM2MMIO_CMD_TOKEN_CMD_MSB 1
-#define _STREAM2MMIO_CMD_TOKEN_WIDTH (_STREAM2MMIO_CMD_TOKEN_CMD_MSB+1-_STREAM2MMIO_CMD_TOKEN_CMD_LSB)
+#define _STREAM2MMIO_CMD_TOKEN_WIDTH (_STREAM2MMIO_CMD_TOKEN_CMD_MSB + 1 - _STREAM2MMIO_CMD_TOKEN_CMD_LSB)
#define _STREAM2MMIO_CMD_TOKEN_STORE_WORDS 0 /* command for storing a number of output words indicated by reg _STREAM2MMIO_NUM_ITEMS */
#define _STREAM2MMIO_CMD_TOKEN_STORE_PACKETS 1 /* command for storing a number of packets indicated by reg _STREAM2MMIO_NUM_ITEMS */
/* count - indicates number of words stored */
#define _STREAM2MMIO_PACK_NUM_ITEMS_BITS 16
#define _STREAM2MMIO_PACK_ACK_EOP_BIT _STREAM2MMIO_PACK_NUM_ITEMS_BITS
-#define _STREAM2MMIO_PACK_ACK_EOF_BIT (_STREAM2MMIO_PACK_ACK_EOP_BIT+1)
+#define _STREAM2MMIO_PACK_ACK_EOF_BIT (_STREAM2MMIO_PACK_ACK_EOP_BIT + 1)
/* acknowledge token definition */
#define _STREAM2MMIO_ACK_TOKEN_NUM_ITEMS_LSB 0 /* bits 3-0 is for the command field */
-#define _STREAM2MMIO_ACK_TOKEN_NUM_ITEMS_MSB (_STREAM2MMIO_PACK_NUM_ITEMS_BITS-1)
+#define _STREAM2MMIO_ACK_TOKEN_NUM_ITEMS_MSB (_STREAM2MMIO_PACK_NUM_ITEMS_BITS - 1)
#define _STREAM2MMIO_ACK_TOKEN_EOP_BIT _STREAM2MMIO_PACK_ACK_EOP_BIT
#define _STREAM2MMIO_ACK_TOKEN_EOF_BIT _STREAM2MMIO_PACK_ACK_EOF_BIT
-#define _STREAM2MMIO_ACK_TOKEN_VALID_BIT (_STREAM2MMIO_ACK_TOKEN_EOF_BIT+1) /* this bit indicates a valid ack */
- /* if there is no valid ack, a read */
- /* on the ack register returns 0 */
-#define _STREAM2MMIO_ACK_TOKEN_WIDTH (_STREAM2MMIO_ACK_TOKEN_VALID_BIT+1)
+#define _STREAM2MMIO_ACK_TOKEN_VALID_BIT (_STREAM2MMIO_ACK_TOKEN_EOF_BIT + 1) /* this bit indicates a valid ack */
+ /* if there is no valid ack, a read */
+ /* on the ack register returns 0 */
+#define _STREAM2MMIO_ACK_TOKEN_WIDTH (_STREAM2MMIO_ACK_TOKEN_VALID_BIT + 1)
/* commands for packer module */
#define _STREAM2MMIO_PACK_CMD_STORE_WORDS 0
#define _STREAM2MMIO_PACK_CMD_STORE_LONG_PACKET 1
#define _STREAM2MMIO_PACK_CMD_STORE_SHORT_PACKET 2
-
-
-
#endif /* _STREAM2MMIO_DEFS_H */
#define _HRT_TIMED_CONTROLLER_REG_ALIGN 4
-#endif /* _timed_controller_defs_h */
+#endif /* _timed_controller_defs_h */
#define hrt_host_type_of_ulong unsigned long
#define hrt_host_type_of_ptr void*
-#define HRT_TYPE_BYTES(cell, type) (HRT_TYPE_BITS(cell, type)/8)
+#define HRT_TYPE_BYTES(cell, type) (HRT_TYPE_BITS(cell, type) / 8)
#define HRT_HOST_TYPE(cell_type) HRTCAT(hrt_host_type_of_, cell_type)
#define HRT_INT_TYPE(type) HRTCAT(hrt_int_type_of_, type)
#ifdef C_RUN
#ifdef C_RUN_DYNAMIC_LINK_PROGRAMS
-extern void *csim_processor_get_crun_symbol(hive_proc_id p, const char *sym);
-#define _hrt_cell_get_crun_symbol(cell,sym) csim_processor_get_crun_symbol(cell,HRTSTR(sym))
-#define _hrt_cell_get_crun_indexed_symbol(cell,sym) csim_processor_get_crun_symbol(cell,HRTSTR(sym))
+void *csim_processor_get_crun_symbol(hive_proc_id p, const char *sym);
+#define _hrt_cell_get_crun_symbol(cell, sym) csim_processor_get_crun_symbol(cell, HRTSTR(sym))
+#define _hrt_cell_get_crun_indexed_symbol(cell, sym) csim_processor_get_crun_symbol(cell, HRTSTR(sym))
#else
-#define _hrt_cell_get_crun_symbol(cell,sym) (&sym)
-#define _hrt_cell_get_crun_indexed_symbol(cell,sym) (sym)
+#define _hrt_cell_get_crun_symbol(cell, sym) (&sym)
+#define _hrt_cell_get_crun_indexed_symbol(cell, sym) (sym)
#endif // C_RUN_DYNAMIC_LINK_PROGRAMS
#define hrt_scalar_store(cell, type, var, data) \
- ((*(HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_symbol(cell,var)) = (data))
+ ((*(HRT_HOST_TYPE(type) *)_hrt_cell_get_crun_symbol(cell, var)) = (data))
#define hrt_scalar_load(cell, type, var) \
- ((*(HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_symbol(cell,var)))
+ ((*(HRT_HOST_TYPE(type) *)_hrt_cell_get_crun_symbol(cell, var)))
#define hrt_indexed_store(cell, type, array, index, data) \
- ((((HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_indexed_symbol(cell,array))[index]) = (data))
+ ((((HRT_HOST_TYPE(type) *)_hrt_cell_get_crun_indexed_symbol(cell, array))[index]) = (data))
#define hrt_indexed_load(cell, type, array, index) \
- (((HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_indexed_symbol(cell,array))[index])
+ (((HRT_HOST_TYPE(type) *)_hrt_cell_get_crun_indexed_symbol(cell, array))[index])
#else /* C_RUN */
#define hrt_scalar_store(cell, type, var, data) \
- HRTCAT(hrt_mem_store_,HRT_TYPE_BITS(cell, type))(\
+ HRTCAT(hrt_mem_store_, HRT_TYPE_BITS(cell, type))(\
cell, \
- HRTCAT(HIVE_MEM_,var), \
- HRTCAT(HIVE_ADDR_,var), \
+ HRTCAT(HIVE_MEM_, var), \
+ HRTCAT(HIVE_ADDR_, var), \
(HRT_INT_TYPE(type))(data))
#define hrt_scalar_load(cell, type, var) \
- (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_,HRT_PROC_TYPE(cell),_,type) ( \
+ (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_, HRT_PROC_TYPE(cell), _, type) ( \
cell, \
- HRTCAT(HIVE_MEM_,var), \
- HRTCAT(HIVE_ADDR_,var)))
+ HRTCAT(HIVE_MEM_, var), \
+ HRTCAT(HIVE_ADDR_, var)))
#define hrt_indexed_store(cell, type, array, index, data) \
- HRTCAT(hrt_mem_store_,HRT_TYPE_BITS(cell, type))(\
+ HRTCAT(hrt_mem_store_, HRT_TYPE_BITS(cell, type))(\
cell, \
- HRTCAT(HIVE_MEM_,array), \
- (HRTCAT(HIVE_ADDR_,array))+((index)*HRT_TYPE_BYTES(cell, type)), \
+ HRTCAT(HIVE_MEM_, array), \
+ (HRTCAT(HIVE_ADDR_, array)) + ((index) * HRT_TYPE_BYTES(cell, type)), \
(HRT_INT_TYPE(type))(data))
#define hrt_indexed_load(cell, type, array, index) \
- (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_,HRT_PROC_TYPE(cell),_,type) ( \
- cell, \
- HRTCAT(HIVE_MEM_,array), \
- (HRTCAT(HIVE_ADDR_,array))+((index)*HRT_TYPE_BYTES(cell, type))))
+ (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_, HRT_PROC_TYPE(cell), _, type) ( \
+ cell, \
+ HRTCAT(HIVE_MEM_, array), \
+ (HRTCAT(HIVE_ADDR_, array)) + ((index) * HRT_TYPE_BYTES(cell, type))))
#endif /* C_RUN */
*/
#define _IBUF_CNTRL_MAIN_CNTRL_FSM_MASK 0xf
#define _IBUF_CNTRL_MAIN_CNTRL_FSM_NEXT_COMMAND_CHECK 0x9
-#define _IBUF_CNTRL_MAIN_CNTRL_MEM_INP_BUF_ALLOC (1 << 8)
+#define _IBUF_CNTRL_MAIN_CNTRL_MEM_INP_BUF_ALLOC BIT(8)
#define _IBUF_CNTRL_DMA_SYNC_WAIT_FOR_SYNC 1
#define _IBUF_CNTRL_DMA_SYNC_FSM_WAIT_FOR_ACK (0x3 << 1)
typedef struct ib_buffer_s ib_buffer_t;
struct ib_buffer_s {
- uint32_t start_addr; /* start address of the buffer in the
+ u32 start_addr; /* start address of the buffer in the
* "input-buffer hardware block"
*/
- uint32_t stride; /* stride per buffer line (in bytes) */
- uint32_t lines; /* lines in the buffer */
+ u32 stride; /* stride per buffer line (in bytes) */
+ u32 lines; /* lines in the buffer */
};
typedef struct ibuf_ctrl_cfg_s ibuf_ctrl_cfg_t;
struct ibuf_ctrl_cfg_s {
-
bool online;
struct {
/* DMA configuration */
- uint32_t channel;
- uint32_t cmd; /* must be _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND */
+ u32 channel;
+ u32 cmd; /* must be _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND */
/* DMA reconfiguration */
- uint32_t shift_returned_items;
- uint32_t elems_per_word_in_ibuf;
- uint32_t elems_per_word_in_dest;
+ u32 shift_returned_items;
+ u32 elems_per_word_in_ibuf;
+ u32 elems_per_word_in_dest;
} dma_cfg;
ib_buffer_t ib_buffer;
struct {
- uint32_t stride;
- uint32_t start_addr;
- uint32_t lines;
+ u32 stride;
+ u32 start_addr;
+ u32 lines;
} dest_buf_cfg;
- uint32_t items_per_store;
- uint32_t stores_per_frame;
+ u32 items_per_store;
+ u32 stores_per_frame;
struct {
- uint32_t sync_cmd; /* must be _STREAM2MMIO_CMD_TOKEN_SYNC_FRAME */
- uint32_t store_cmd; /* must be _STREAM2MMIO_CMD_TOKEN_STORE_PACKETS */
+ u32 sync_cmd; /* must be _STREAM2MMIO_CMD_TOKEN_SYNC_FRAME */
+ u32 store_cmd; /* must be _STREAM2MMIO_CMD_TOKEN_STORE_PACKETS */
} stream2mmio_cfg;
};
-extern const uint32_t N_IBUF_CTRL_PROCS[N_IBUF_CTRL_ID];
+extern const u32 N_IBUF_CTRL_PROCS[N_IBUF_CTRL_ID];
#endif /* __IBUF_CTRL_GLOBAL_H_INCLUDED__ */
*/
#include "pixelgen.h"
-
#define INPUT_SYSTEM_N_STREAM_ID 6 /* maximum number of simultaneous
virtual channels supported*/
bool online;
bool raw_packed;
- int8_t linked_isys_stream_id;
+ s8 linked_isys_stream_id;
struct {
bool comp_enable;
- int32_t active_lanes;
- int32_t fmt_type;
- int32_t ch_id;
- int32_t comp_predictor;
- int32_t comp_scheme;
+ s32 active_lanes;
+ s32 fmt_type;
+ s32 ch_id;
+ s32 comp_predictor;
+ s32 comp_scheme;
} csi_port_attr;
pixelgen_tpg_cfg_t tpg_port_attr;
pixelgen_prbs_cfg_t prbs_port_attr;
struct {
- int32_t align_req_in_bytes;
- int32_t bits_per_pixel;
- int32_t pixels_per_line;
- int32_t lines_per_frame;
+ s32 align_req_in_bytes;
+ s32 bits_per_pixel;
+ s32 pixels_per_line;
+ s32 lines_per_frame;
} input_port_resolution;
struct {
- int32_t left_padding;
- int32_t max_isp_input_width;
+ s32 left_padding;
+ s32 max_isp_input_width;
} output_port_attr;
struct {
bool enable;
- int32_t fmt_type;
- int32_t align_req_in_bytes;
- int32_t bits_per_pixel;
- int32_t pixels_per_line;
- int32_t lines_per_frame;
+ s32 fmt_type;
+ s32 align_req_in_bytes;
+ s32 bits_per_pixel;
+ s32 pixels_per_line;
+ s32 lines_per_frame;
} metadata;
};
typedef struct virtual_input_system_stream_s virtual_input_system_stream_t;
struct virtual_input_system_stream_s {
- uint32_t id; /*Used when multiple MIPI data types and/or virtual channels are used.
+ u32 id; /*Used when multiple MIPI data types and/or virtual channels are used.
Must be unique within one CSI RX
and lower than SH_CSS_MAX_ISYS_CHANNEL_NODES */
- uint8_t enable_metadata;
+ u8 enable_metadata;
input_system_input_port_t input_port;
input_system_channel_t channel;
input_system_channel_t md_channel; /* metadata channel */
- uint8_t online;
- int8_t linked_isys_stream_id;
- uint8_t valid;
+ u8 online;
+ s8 linked_isys_stream_id;
+ u8 valid;
#ifdef ISP2401
input_system_polling_mode_t polling_mode;
- int32_t subscr_index;
+ s32 subscr_index;
#endif
};
typedef struct virtual_input_system_stream_cfg_s virtual_input_system_stream_cfg_t;
struct virtual_input_system_stream_cfg_s {
- uint8_t enable_metadata;
+ u8 enable_metadata;
input_system_input_port_cfg_t input_port_cfg;
input_system_channel_cfg_t channel_cfg;
input_system_channel_cfg_t md_channel_cfg;
- uint8_t valid;
+ u8 valid;
};
#define ISP_INPUT_BUF_START_ADDR 0
#define LINES_OF_ISP_INPUT_BUF (NUM_OF_INPUT_BUF * NUM_OF_LINES_PER_BUF)
#define ISP_INPUT_BUF_STRIDE SH_CSS_MAX_SENSOR_WIDTH
-
#endif /* __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ */
********************************************************/
typedef struct isys2401_dma_port_cfg_s isys2401_dma_port_cfg_t;
struct isys2401_dma_port_cfg_s {
- uint32_t stride;
- uint32_t elements;
- uint32_t cropping;
- uint32_t width;
+ u32 stride;
+ u32 elements;
+ u32 cropping;
+ u32 width;
};
/* end of DMA Port */
isys2401_dma_channel channel;
isys2401_dma_connection connection;
isys2401_dma_extension extension;
- uint32_t height;
+ u32 height;
};
+
/* end of DMA Device */
/* isys2401_dma_channel limits per DMA ID */
typedef struct stream2mmio_cfg_s stream2mmio_cfg_t;
struct stream2mmio_cfg_s {
- uint32_t bits_per_pixel;
- uint32_t enable_blocking;
+ u32 bits_per_pixel;
+ u32 enable_blocking;
};
/* Stream2MMIO limits per ID*/
*/
typedef struct sync_generator_cfg_s sync_generator_cfg_t;
struct sync_generator_cfg_s {
- uint32_t hblank_cycles;
- uint32_t vblank_cycles;
- uint32_t pixels_per_clock;
- uint32_t nr_of_frames;
- uint32_t pixels_per_line;
- uint32_t lines_per_frame;
+ u32 hblank_cycles;
+ u32 vblank_cycles;
+ u32 pixels_per_clock;
+ u32 nr_of_frames;
+ u32 pixels_per_line;
+ u32 lines_per_frame;
};
typedef enum {
struct {
/* be used by CHBO and MON */
- uint32_t R1;
- uint32_t G1;
- uint32_t B1;
+ u32 R1;
+ u32 G1;
+ u32 B1;
/* be used by CHBO only */
- uint32_t R2;
- uint32_t G2;
- uint32_t B2;
+ u32 R2;
+ u32 G2;
+ u32 B2;
} color_cfg;
struct {
- uint32_t h_mask; /* horizontal mask */
- uint32_t v_mask; /* vertical mask */
- uint32_t hv_mask; /* horizontal+vertical mask? */
+ u32 h_mask; /* horizontal mask */
+ u32 v_mask; /* vertical mask */
+ u32 hv_mask; /* horizontal+vertical mask? */
} mask_cfg;
struct {
- int32_t h_delta; /* horizontal delta? */
- int32_t v_delta; /* vertical delta? */
+ s32 h_delta; /* horizontal delta? */
+ s32 v_delta; /* vertical delta? */
} delta_cfg;
sync_generator_cfg_t sync_gen_cfg;
*/
typedef struct pixelgen_prbs_cfg_s pixelgen_prbs_cfg_t;
struct pixelgen_prbs_cfg_s {
- int32_t seed0;
- int32_t seed1;
+ s32 seed0;
+ s32 seed1;
sync_generator_cfg_t sync_gen_cfg;
};
/* end of Pixel-generator: TPG. ("pixelgen_global.h") */
#endif /* __PIXELGEN_GLOBAL_H_INCLUDED__ */
-
#ifndef _sp_map_h_
#define _sp_map_h_
-
#ifndef _hrt_dummy_use_blob_sp
#define _hrt_dummy_use_blob_sp()
#endif
#define DMA_DDR_TO_VAMEM_WORKAROUND
#define DMA_DDR_TO_HMEM_WORKAROUND
-
/*
* Semi global. "HRT" is accessible from SP, but
* the HRT types do not fully apply
/*#define HRT_ADDRESS_WIDTH 64 */
#define HRT_DATA_WIDTH 32
-#define SIZEOF_HRT_REG (HRT_DATA_WIDTH>>3)
-#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH/8)
+#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
+#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8)
/* The main bus connecting all devices */
#define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH
/* per-frame parameter handling support */
#define SH_CSS_ENABLE_PER_FRAME_PARAMS
-typedef uint32_t hrt_bus_align_t;
+typedef u32 hrt_bus_align_t;
/*
* Enumerate the devices, device access through the API is by ID,
CSI_RX_FRONTEND0_ID = 0, /* map to ISYS2401_CSI_RX_A */
CSI_RX_FRONTEND1_ID, /* map to ISYS2401_CSI_RX_B */
CSI_RX_FRONTEND2_ID, /* map to ISYS2401_CSI_RX_C */
-#define N_CSI_RX_FRONTEND_ID (CSI_RX_FRONTEND2_ID+1)
+#define N_CSI_RX_FRONTEND_ID (CSI_RX_FRONTEND2_ID + 1)
} csi_rx_frontend_ID_t;
typedef enum {
IA_CSS_DDR,
N_IA_CSS_MEMORIES
};
+
#define IA_CSS_NUM_MEMORIES 9
/* For driver compatibility */
#define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_iterator() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.iterator.size;
offset = binary->info->mem_offsets.offsets.config->dmem.iterator.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_copy_output() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.copy_output.size;
offset = binary->info->mem_offsets.offsets.config->dmem.copy_output.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_crop() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.crop.size;
offset = binary->info->mem_offsets.offsets.config->dmem.crop.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_fpn() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.fpn.size;
offset = binary->info->mem_offsets.offsets.config->dmem.fpn.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_dvs() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.dvs.size;
offset = binary->info->mem_offsets.offsets.config->dmem.dvs.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_qplane() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.qplane.size;
offset = binary->info->mem_offsets.offsets.config->dmem.qplane.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output0() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output0.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output0.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output1() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output1.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output1.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_sc() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.sc.size;
offset = binary->info->mem_offsets.offsets.config->dmem.sc.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_raw() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.raw.size;
offset = binary->info->mem_offsets.offsets.config->dmem.raw.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_tnr() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.tnr.size;
offset = binary->info->mem_offsets.offsets.config->dmem.tnr.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_ref() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.ref.size;
offset = binary->info->mem_offsets.offsets.config->dmem.ref.offset;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() enter:\n");
{
- unsigned offset = 0;
- unsigned size = 0;
+ unsigned int offset = 0;
+ unsigned int size = 0;
+
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.vf.size;
offset = binary->info->mem_offsets.offsets.config->dmem.vf.offset;
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() leave:\n");
}
-
static void
ia_css_process_aa(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.aa.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.aa.size;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset;
if (size) {
struct sh_css_isp_aa_params *t = (struct sh_css_isp_aa_params *)
static void
ia_css_process_anr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.anr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.anr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr() leave:\n");
}
-
}
}
static void
ia_css_process_anr2(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr2() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr2() leave:\n");
}
-
}
}
static void
ia_css_process_bh(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bh.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.bh.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bh.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.bh.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() leave:\n");
}
-
}
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->hmem0.bh.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->hmem0.bh.size;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() leave:\n");
}
-
}
}
static void
ia_css_process_cnr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_cnr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_cnr() leave:\n");
}
-
}
}
static void
ia_css_process_crop(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.crop.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.crop.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.crop.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.crop.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_crop() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_crop() leave:\n");
}
-
}
}
static void
ia_css_process_csc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.csc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.csc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.csc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.csc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_csc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_csc() leave:\n");
}
-
}
}
static void
ia_css_process_dp(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.dp.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.dp.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.dp.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.dp.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_dp() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_dp() leave:\n");
}
-
}
}
static void
ia_css_process_bnr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bnr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bnr() leave:\n");
}
-
}
}
static void
ia_css_process_de(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.de.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.de.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.de.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.de.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_de() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_de() leave:\n");
}
-
}
}
static void
ia_css_process_ecd(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ecd() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ecd() leave:\n");
}
-
}
}
static void
ia_css_process_formats(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.formats.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.formats.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.formats.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.formats.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_formats() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_formats() leave:\n");
}
-
}
}
static void
ia_css_process_fpn(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fpn() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fpn() leave:\n");
}
-
}
}
static void
ia_css_process_gc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.gc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.gc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.gc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.gc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() leave:\n");
}
-
}
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() leave:\n");
}
-
}
}
static void
ia_css_process_ce(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ce.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.ce.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ce.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.ce.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ce() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ce() leave:\n");
}
-
}
}
static void
ia_css_process_yuv2rgb(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yuv2rgb() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yuv2rgb() leave:\n");
}
-
}
}
static void
ia_css_process_rgb2yuv(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_rgb2yuv() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_rgb2yuv() leave:\n");
}
-
}
}
static void
ia_css_process_r_gamma(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_r_gamma() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_r_gamma() leave:\n");
}
-
}
}
static void
ia_css_process_g_gamma(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_g_gamma() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_g_gamma() leave:\n");
}
-
}
}
static void
ia_css_process_b_gamma(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_b_gamma() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_b_gamma() leave:\n");
}
-
}
}
static void
ia_css_process_uds(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.uds.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.uds.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.uds.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.uds.offset;
if (size) {
struct sh_css_sp_uds_params *p;
+
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_uds() enter:\n");
p = (struct sh_css_sp_uds_params *)
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_uds() leave:\n");
}
-
}
}
static void
ia_css_process_raa(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.raa.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.raa.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.raa.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.raa.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_raa() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_raa() leave:\n");
}
-
}
}
static void
ia_css_process_s3a(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_s3a() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_s3a() leave:\n");
}
-
}
}
static void
ia_css_process_ob(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ob.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.ob.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ob.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.ob.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() leave:\n");
}
-
}
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.ob.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.ob.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.ob.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.ob.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() leave:\n");
}
-
}
}
static void
ia_css_process_output(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.output.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.output.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.output.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.output.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_output() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_output() leave:\n");
}
-
}
}
static void
ia_css_process_sc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.sc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.sc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sc() leave:\n");
}
-
}
}
static void
ia_css_process_bds(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bds.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.bds.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bds.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.bds.offset;
if (size) {
struct sh_css_isp_bds_params *p;
+
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bds() enter:\n");
p = (struct sh_css_isp_bds_params *)
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bds() leave:\n");
}
-
}
}
static void
ia_css_process_tnr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_tnr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_tnr() leave:\n");
}
-
}
}
static void
ia_css_process_macc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.macc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.macc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.macc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.macc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_macc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_macc() leave:\n");
}
-
}
}
static void
ia_css_process_sdis_horicoef(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horicoef() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horicoef() leave:\n");
}
-
}
}
static void
ia_css_process_sdis_vertcoef(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertcoef() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertcoef() leave:\n");
}
-
}
}
static void
ia_css_process_sdis_horiproj(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horiproj() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horiproj() leave:\n");
}
-
}
}
static void
ia_css_process_sdis_vertproj(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertproj() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertproj() leave:\n");
}
-
}
}
static void
ia_css_process_sdis2_horicoef(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horicoef() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horicoef() leave:\n");
}
-
}
}
static void
ia_css_process_sdis2_vertcoef(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertcoef() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertcoef() leave:\n");
}
-
}
}
static void
ia_css_process_sdis2_horiproj(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horiproj() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horiproj() leave:\n");
}
-
}
}
static void
ia_css_process_sdis2_vertproj(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertproj() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertproj() leave:\n");
}
-
}
}
static void
ia_css_process_wb(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.wb.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.wb.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.wb.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.wb.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_wb() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_wb() leave:\n");
}
-
}
}
static void
ia_css_process_nr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.nr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.nr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.nr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.nr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_nr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_nr() leave:\n");
}
-
}
}
static void
ia_css_process_yee(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.yee.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.yee.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.yee.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.yee.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yee() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yee() leave:\n");
}
-
}
}
static void
ia_css_process_ynr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ynr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ynr() leave:\n");
}
-
}
}
static void
ia_css_process_fc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.fc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.fc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.fc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.fc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fc() leave:\n");
}
-
}
}
static void
ia_css_process_ctc(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() leave:\n");
}
-
}
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() leave:\n");
}
-
}
}
static void
ia_css_process_xnr_table(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr_table() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr_table() leave:\n");
}
-
}
}
static void
ia_css_process_xnr(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr() leave:\n");
}
-
}
}
static void
ia_css_process_xnr3(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() leave:\n");
}
-
}
#ifdef ISP2401
{
- unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.size;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.offset;
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.offset;
if (size) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() enter:\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() leave:\n");
}
-
}
#endif
}
/* Code generated by genparam/gencode.c:gen_param_process_table() */
-void (* ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
- unsigned pipe_id,
+void (*ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params) = {
ia_css_process_aa,
static void
ia_css_get_dp_config(const struct ia_css_isp_parameters *params,
struct ia_css_dp_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_dp_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_dp_config() enter: config=%p\n",
+ config);
*config = params->dp_config;
ia_css_set_dp_config(struct ia_css_isp_parameters *params,
const struct ia_css_dp_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_dp_config() enter:\n");
ia_css_dp_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dp_config = *config;
params->config_changed[IA_CSS_DP_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_dp_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_dp_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_wb_config(const struct ia_css_isp_parameters *params,
struct ia_css_wb_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_wb_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_wb_config() enter: config=%p\n",
+ config);
*config = params->wb_config;
ia_css_set_wb_config(struct ia_css_isp_parameters *params,
const struct ia_css_wb_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_wb_config() enter:\n");
ia_css_wb_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->wb_config = *config;
params->config_changed[IA_CSS_WB_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_wb_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_wb_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_tnr_config(const struct ia_css_isp_parameters *params,
struct ia_css_tnr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_tnr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_tnr_config() enter: config=%p\n",
+ config);
*config = params->tnr_config;
ia_css_set_tnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_tnr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_tnr_config() enter:\n");
ia_css_tnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->tnr_config = *config;
params->config_changed[IA_CSS_TNR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_tnr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_tnr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_ob_config(const struct ia_css_isp_parameters *params,
struct ia_css_ob_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ob_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ob_config() enter: config=%p\n",
+ config);
*config = params->ob_config;
ia_css_set_ob_config(struct ia_css_isp_parameters *params,
const struct ia_css_ob_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ob_config() enter:\n");
ia_css_ob_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->ob_config = *config;
params->config_changed[IA_CSS_OB_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ob_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ob_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_de_config(const struct ia_css_isp_parameters *params,
struct ia_css_de_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_de_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_de_config() enter: config=%p\n",
+ config);
*config = params->de_config;
ia_css_set_de_config(struct ia_css_isp_parameters *params,
const struct ia_css_de_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_de_config() enter:\n");
ia_css_de_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->de_config = *config;
params->config_changed[IA_CSS_DE_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_de_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_de_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_anr_config(const struct ia_css_isp_parameters *params,
struct ia_css_anr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr_config() enter: config=%p\n",
+ config);
*config = params->anr_config;
ia_css_set_anr_config(struct ia_css_isp_parameters *params,
const struct ia_css_anr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_anr_config() enter:\n");
ia_css_anr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->anr_config = *config;
params->config_changed[IA_CSS_ANR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_anr2_config(const struct ia_css_isp_parameters *params,
struct ia_css_anr_thres *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr2_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr2_config() enter: config=%p\n",
+ config);
*config = params->anr_thres;
ia_css_set_anr2_config(struct ia_css_isp_parameters *params,
const struct ia_css_anr_thres *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_anr2_config() enter:\n");
ia_css_anr2_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->anr_thres = *config;
params->config_changed[IA_CSS_ANR2_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr2_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr2_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_ce_config(const struct ia_css_isp_parameters *params,
struct ia_css_ce_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ce_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ce_config() enter: config=%p\n",
+ config);
*config = params->ce_config;
ia_css_set_ce_config(struct ia_css_isp_parameters *params,
const struct ia_css_ce_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ce_config() enter:\n");
ia_css_ce_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->ce_config = *config;
params->config_changed[IA_CSS_CE_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ce_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ce_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_ecd_config(const struct ia_css_isp_parameters *params,
struct ia_css_ecd_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ecd_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ecd_config() enter: config=%p\n",
+ config);
*config = params->ecd_config;
ia_css_set_ecd_config(struct ia_css_isp_parameters *params,
const struct ia_css_ecd_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ecd_config() enter:\n");
ia_css_ecd_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->ecd_config = *config;
params->config_changed[IA_CSS_ECD_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ecd_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ecd_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_ynr_config(const struct ia_css_isp_parameters *params,
struct ia_css_ynr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ynr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ynr_config() enter: config=%p\n",
+ config);
*config = params->ynr_config;
ia_css_set_ynr_config(struct ia_css_isp_parameters *params,
const struct ia_css_ynr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ynr_config() enter:\n");
ia_css_ynr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->ynr_config = *config;
params->config_changed[IA_CSS_YNR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ynr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ynr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_fc_config(const struct ia_css_isp_parameters *params,
struct ia_css_fc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_fc_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_fc_config() enter: config=%p\n",
+ config);
*config = params->fc_config;
ia_css_set_fc_config(struct ia_css_isp_parameters *params,
const struct ia_css_fc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_fc_config() enter:\n");
ia_css_fc_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->fc_config = *config;
params->config_changed[IA_CSS_FC_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_fc_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_fc_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_cnr_config(const struct ia_css_isp_parameters *params,
struct ia_css_cnr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_cnr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_cnr_config() enter: config=%p\n",
+ config);
*config = params->cnr_config;
ia_css_set_cnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_cnr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_cnr_config() enter:\n");
ia_css_cnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->cnr_config = *config;
params->config_changed[IA_CSS_CNR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_cnr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_cnr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_macc_config(const struct ia_css_isp_parameters *params,
struct ia_css_macc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_macc_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_macc_config() enter: config=%p\n",
+ config);
*config = params->macc_config;
ia_css_set_macc_config(struct ia_css_isp_parameters *params,
const struct ia_css_macc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_macc_config() enter:\n");
ia_css_macc_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->macc_config = *config;
params->config_changed[IA_CSS_MACC_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_macc_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_macc_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_ctc_config(const struct ia_css_isp_parameters *params,
struct ia_css_ctc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ctc_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ctc_config() enter: config=%p\n",
+ config);
*config = params->ctc_config;
ia_css_set_ctc_config(struct ia_css_isp_parameters *params,
const struct ia_css_ctc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ctc_config() enter:\n");
ia_css_ctc_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->ctc_config = *config;
params->config_changed[IA_CSS_CTC_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ctc_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ctc_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_aa_config(const struct ia_css_isp_parameters *params,
struct ia_css_aa_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_aa_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_aa_config() enter: config=%p\n",
+ config);
*config = params->aa_config;
ia_css_set_aa_config(struct ia_css_isp_parameters *params,
const struct ia_css_aa_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_aa_config() enter:\n");
params->aa_config = *config;
params->config_changed[IA_CSS_AA_ID] = true;
params->config_changed[IA_CSS_AA_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_aa_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_aa_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_yuv2rgb_config(const struct ia_css_isp_parameters *params,
struct ia_css_cc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_yuv2rgb_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_yuv2rgb_config() enter: config=%p\n",
+ config);
*config = params->yuv2rgb_cc_config;
ia_css_set_yuv2rgb_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_yuv2rgb_config() enter:\n");
ia_css_yuv2rgb_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->yuv2rgb_cc_config = *config;
params->config_changed[IA_CSS_YUV2RGB_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_yuv2rgb_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_yuv2rgb_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_rgb2yuv_config(const struct ia_css_isp_parameters *params,
struct ia_css_cc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_rgb2yuv_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_rgb2yuv_config() enter: config=%p\n",
+ config);
*config = params->rgb2yuv_cc_config;
ia_css_set_rgb2yuv_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_rgb2yuv_config() enter:\n");
ia_css_rgb2yuv_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->rgb2yuv_cc_config = *config;
params->config_changed[IA_CSS_RGB2YUV_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_rgb2yuv_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_rgb2yuv_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_csc_config(const struct ia_css_isp_parameters *params,
struct ia_css_cc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_csc_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_csc_config() enter: config=%p\n",
+ config);
*config = params->cc_config;
ia_css_set_csc_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_csc_config() enter:\n");
ia_css_csc_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->cc_config = *config;
params->config_changed[IA_CSS_CSC_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_csc_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_csc_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_nr_config(const struct ia_css_isp_parameters *params,
struct ia_css_nr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_nr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_nr_config() enter: config=%p\n",
+ config);
*config = params->nr_config;
ia_css_set_nr_config(struct ia_css_isp_parameters *params,
const struct ia_css_nr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_nr_config() enter:\n");
ia_css_nr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->nr_config = *config;
params->config_changed[IA_CSS_NR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_nr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_nr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_gc_config(const struct ia_css_isp_parameters *params,
struct ia_css_gc_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_gc_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_gc_config() enter: config=%p\n",
+ config);
*config = params->gc_config;
ia_css_set_gc_config(struct ia_css_isp_parameters *params,
const struct ia_css_gc_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_gc_config() enter:\n");
ia_css_gc_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->gc_config = *config;
params->config_changed[IA_CSS_GC_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_gc_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_gc_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis_horicoef_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horicoef_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horicoef_config() enter: config=%p\n",
+ config);
*config = params->dvs_coefs;
ia_css_set_sdis_horicoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_horicoef_config() enter:\n");
ia_css_sdis_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs_coefs = *config;
params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horicoef_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horicoef_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis_vertcoef_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertcoef_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertcoef_config() enter: config=%p\n",
+ config);
*config = params->dvs_coefs;
ia_css_set_sdis_vertcoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_vertcoef_config() enter:\n");
ia_css_sdis_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs_coefs = *config;
params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertcoef_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertcoef_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis_horiproj_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horiproj_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horiproj_config() enter: config=%p\n",
+ config);
*config = params->dvs_coefs;
ia_css_set_sdis_horiproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_horiproj_config() enter:\n");
ia_css_sdis_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs_coefs = *config;
params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horiproj_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horiproj_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis_vertproj_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertproj_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertproj_config() enter: config=%p\n",
+ config);
*config = params->dvs_coefs;
ia_css_set_sdis_vertproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_vertproj_config() enter:\n");
ia_css_sdis_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs_coefs = *config;
params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertproj_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertproj_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis2_horicoef_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs2_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horicoef_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horicoef_config() enter: config=%p\n",
+ config);
*config = params->dvs2_coefs;
ia_css_set_sdis2_horicoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_horicoef_config() enter:\n");
ia_css_sdis2_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs2_coefs = *config;
params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horicoef_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horicoef_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis2_vertcoef_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs2_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertcoef_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertcoef_config() enter: config=%p\n",
+ config);
*config = params->dvs2_coefs;
ia_css_set_sdis2_vertcoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_vertcoef_config() enter:\n");
ia_css_sdis2_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs2_coefs = *config;
params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertcoef_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertcoef_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis2_horiproj_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs2_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horiproj_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horiproj_config() enter: config=%p\n",
+ config);
*config = params->dvs2_coefs;
ia_css_set_sdis2_horiproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_horiproj_config() enter:\n");
ia_css_sdis2_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs2_coefs = *config;
params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horiproj_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horiproj_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_sdis2_vertproj_config(const struct ia_css_isp_parameters *params,
struct ia_css_dvs2_coefficients *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertproj_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertproj_config() enter: config=%p\n",
+ config);
*config = params->dvs2_coefs;
ia_css_set_sdis2_vertproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_vertproj_config() enter:\n");
ia_css_sdis2_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->dvs2_coefs = *config;
params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertproj_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertproj_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_r_gamma_config(const struct ia_css_isp_parameters *params,
struct ia_css_rgb_gamma_table *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_r_gamma_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_r_gamma_config() enter: config=%p\n",
+ config);
*config = params->r_gamma_table;
ia_css_set_r_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_r_gamma_config() enter:\n");
ia_css_r_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->r_gamma_table = *config;
params->config_changed[IA_CSS_R_GAMMA_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_r_gamma_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_r_gamma_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_g_gamma_config(const struct ia_css_isp_parameters *params,
struct ia_css_rgb_gamma_table *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_g_gamma_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_g_gamma_config() enter: config=%p\n",
+ config);
*config = params->g_gamma_table;
ia_css_set_g_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_g_gamma_config() enter:\n");
ia_css_g_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->g_gamma_table = *config;
params->config_changed[IA_CSS_G_GAMMA_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_g_gamma_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_g_gamma_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_b_gamma_config(const struct ia_css_isp_parameters *params,
struct ia_css_rgb_gamma_table *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_b_gamma_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_b_gamma_config() enter: config=%p\n",
+ config);
*config = params->b_gamma_table;
ia_css_set_b_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_b_gamma_config() enter:\n");
ia_css_b_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->b_gamma_table = *config;
params->config_changed[IA_CSS_B_GAMMA_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_b_gamma_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_b_gamma_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_xnr_table_config(const struct ia_css_isp_parameters *params,
struct ia_css_xnr_table *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_table_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_table_config() enter: config=%p\n",
+ config);
*config = params->xnr_table;
ia_css_set_xnr_table_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr_table *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr_table_config() enter:\n");
ia_css_xnr_table_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->xnr_table = *config;
params->config_changed[IA_CSS_XNR_TABLE_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_table_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_table_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_formats_config(const struct ia_css_isp_parameters *params,
struct ia_css_formats_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_formats_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_formats_config() enter: config=%p\n",
+ config);
*config = params->formats_config;
ia_css_set_formats_config(struct ia_css_isp_parameters *params,
const struct ia_css_formats_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_formats_config() enter:\n");
ia_css_formats_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->formats_config = *config;
params->config_changed[IA_CSS_FORMATS_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_formats_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_formats_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_xnr_config(const struct ia_css_isp_parameters *params,
struct ia_css_xnr_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_config() enter: config=%p\n",
+ config);
*config = params->xnr_config;
ia_css_set_xnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr_config() enter:\n");
ia_css_xnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->xnr_config = *config;
params->config_changed[IA_CSS_XNR_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_xnr3_config(const struct ia_css_isp_parameters *params,
struct ia_css_xnr3_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr3_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr3_config() enter: config=%p\n",
+ config);
*config = params->xnr3_config;
ia_css_set_xnr3_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr3_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr3_config() enter:\n");
ia_css_xnr3_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->xnr3_config = *config;
params->config_changed[IA_CSS_XNR3_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr3_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr3_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_s3a_config(const struct ia_css_isp_parameters *params,
struct ia_css_3a_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_s3a_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_s3a_config() enter: config=%p\n",
+ config);
*config = params->s3a_config;
ia_css_set_s3a_config(struct ia_css_isp_parameters *params,
const struct ia_css_3a_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_s3a_config() enter:\n");
ia_css_s3a_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->s3a_config = *config;
params->config_changed[IA_CSS_S3A_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_s3a_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_s3a_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_get_function() */
static void
ia_css_get_output_config(const struct ia_css_isp_parameters *params,
struct ia_css_output_config *config){
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_output_config() enter: "
- "config=%p\n",config);
+ assert(params);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_output_config() enter: config=%p\n",
+ config);
*config = params->output_config;
ia_css_set_output_config(struct ia_css_isp_parameters *params,
const struct ia_css_output_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_output_config() enter:\n");
ia_css_output_debug_dtrace(config, IA_CSS_DEBUG_TRACE);
params->output_config = *config;
params->config_changed[IA_CSS_OUTPUT_ID] = true;
#endif
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_output_config() leave: "
- "return_void\n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_output_config() leave: return_void\n");
}
/* Code generated by genparam/gencode.c:gen_global_access_function() */
ia_css_set_s3a_config(params, config->s3a_config);
ia_css_set_output_config(params, config->output_config);
}
-
struct ia_css_pipeline_stage; /* forward declaration */
-extern void (* ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
- unsigned pipe_id,
+extern void (*ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.aa.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.aa.size;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset;
if (size)
memset(&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], 0, size);
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.cnr.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset;
if (size) {
ia_css_init_cnr_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset;
if (size) {
ia_css_init_cnr2_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.dp.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.dp.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset;
if (size) {
ia_css_init_dp_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.de.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.de.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.de.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.de.offset;
if (size) {
ia_css_init_de_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->dmem.tnr.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->dmem.tnr.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->dmem.tnr.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->dmem.tnr.offset;
if (size) {
ia_css_init_tnr_state((struct sh_css_isp_tnr_dmem_state *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->dmem.ref.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->dmem.ref.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->dmem.ref.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->dmem.ref.offset;
if (size) {
ia_css_init_ref_state((struct sh_css_isp_ref_dmem_state *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() leave:\n");
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() enter:\n");
{
- unsigned size = binary->info->mem_offsets.offsets.state->vmem.ynr.size;
+ unsigned int size = binary->info->mem_offsets.offsets.state->vmem.ynr.size;
- unsigned offset = binary->info->mem_offsets.offsets.state->vmem.ynr.offset;
+ unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.ynr.offset;
if (size) {
ia_css_init_ynr_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
-
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() leave:\n");
}
ia_css_initialize_ref_state,
ia_css_initialize_ynr_state,
};
-
#define _hrt_get_bit(w, b) \
(((w) >> (b)) & 1)
#define _hrt_set_bit(w, b, v) \
- (((w) & (~(1 << (b)))) | (((v)&1) << (b)))
+ (((w) & (~(1 << (b)))) | (((v) & 1) << (b)))
#define _hrt_set_lower_half(w, v) \
_hrt_set_bits(w, 0, 16, v)
#define _hrt_set_upper_half(w, v) \
#define SP_ICACHE_BLOCK_ADDRESS_BITS 11 /* 2048 lines capacity*/
#define SP_ICACHE_ADDRESS_BITS \
- (SP_ICACHE_TAG_BITS+SP_ICACHE_BLOCK_ADDRESS_BITS)
+ (SP_ICACHE_TAG_BITS + SP_ICACHE_BLOCK_ADDRESS_BITS)
-#define SP_PMEM_DEPTH (1<<SP_ICACHE_ADDRESS_BITS)
+#define SP_PMEM_DEPTH BIT(SP_ICACHE_ADDRESS_BITS)
#define SP_FIFO_0_DEPTH 0
#define SP_FIFO_1_DEPTH 0
#define SP_FIFO_6_DEPTH 0
#define SP_FIFO_7_DEPTH 0
-
#define SP_SLV_BUS_MAXBURSTSIZE 1
#endif /* _cell_params_h */
-
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH 2
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH 3
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH (_HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH)
-#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */
+#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */
/* Definition of data format ID at the interface CSS_receiver capture/acquisition units */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8_CSPS 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10_CSPS 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
/* used reserved mipi positions for these */
-#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46
-#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47
-#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37
-#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38
+#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46
+#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47
+#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37
+#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_WIDTH 6
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB444 2 // 32
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB565 3 // 34
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB666 4 // 35
-#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42
+#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW10 6 // 43
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW6 7 // 40
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW7 8 // 41
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18 28 // ?
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_2 29 // ? Option 2 for depacketiser
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_3 30 // ? Option 3 for depacketiser
-#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding
+#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding
/* definition for state machine of data FIFO for decode different type of data */
-#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1
+#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV420_10_REPEAT_PTN 5
#define _HRT_CSS_RECEIVER_2400_YUV420_8L_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV422_8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV422_10_REPEAT_PTN 5
-#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2
+#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB555_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB565_REPEAT_PTN 2
-#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9
+#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9
#define _HRT_CSS_RECEIVER_2400_RGB888_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW6_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW7_REPEAT_PTN 7
#define _HRT_CSS_RECEIVER_2400_RAW8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_RAW10_REPEAT_PTN 5
-#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3
+#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW14_REPEAT_PTN 7
#define _HRT_CSS_RECEIVER_2400_MAX_REPEAT_PTN _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_7_12 5
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_8_12 6
-
/* packet bit definition */
#define _HRT_CSS_RECEIVER_2400_PKT_SOP_IDX 32
#define _HRT_CSS_RECEIVER_2400_PKT_SOP_BITS 1
#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_IDX 0
#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_BITS 32
-
/*************************************************************************************************/
/* Custom Decoding */
/* These Custom Defs are defined based on design-time config in "csi_be_pixel_formatter.chdl" !! */
/*************************************************************************************************/
#define BE_CUST_EN_IDX 0 /* 2bits */
-#define BE_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */
-#define BE_CUST_EN_WIDTH 8
+#define BE_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */
+#define BE_CUST_EN_WIDTH 8
#define BE_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */
#define BE_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */
/* Data State config = {get_bits(6bits), valid(1bit)} */
-#define BE_CUST_DATA_STATE_S0_IDX 0 /* 7bits */
-#define BE_CUST_DATA_STATE_S1_IDX 7 /* 7bits */
+#define BE_CUST_DATA_STATE_S0_IDX 0 /* 7bits */
+#define BE_CUST_DATA_STATE_S1_IDX 7 /* 7bits */
#define BE_CUST_DATA_STATE_S2_IDX 14 /* 7bits */
-#define BE_CUST_DATA_STATE_WIDTH 21
+#define BE_CUST_DATA_STATE_WIDTH 21
#define BE_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */
#define BE_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */
#define BE_CUST_PIX_EXT_PIX_ALIGN_IDX 5 /* 5bits */
#define BE_CUST_PIX_EXT_PIX_MASK_IDX 10 /* 18bits */
#define BE_CUST_PIX_EXT_PIX_EN_IDX 28 /* 1bits */
-#define BE_CUST_PIX_EXT_WIDTH 29
+#define BE_CUST_PIX_EXT_WIDTH 29
/* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */
#define BE_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */
-#define BE_CUST_PIX_VALID_EOP_WIDTH 16
+#define BE_CUST_PIX_VALID_EOP_WIDTH 16
#define BE_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */
#define BE_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */
#define BE_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */
#define BE_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */
#endif /* _mipi_backend_common_defs_h_ */
-#endif /* _css_receiver_2400_common_defs_h_ */
+#endif /* _css_receiver_2400_common_defs_h_ */
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_ECC_TWO_BIT_ERR_IDX 6
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_DATA_ID_ERR_IDX 7
-
/* Bits for CSI2_FUNC_PROG register */
#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX 0
#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS 19
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_IDX 3
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_BITS 2
-
/* BITS for backend RAW16 and RAW 18 registers */
#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_IDX 0
#define _HRT_CSS_RECEIVER_2400_RAW16_EN_BITS 1
/* These hsync and vsync values are for HSS simulation only */
-#define _HRT_CSS_RECEIVER_2400_HSYNC_VAL (1<<16)
-#define _HRT_CSS_RECEIVER_2400_VSYNC_VAL (1<<17)
+#define _HRT_CSS_RECEIVER_2400_HSYNC_VAL BIT(16)
+#define _HRT_CSS_RECEIVER_2400_VSYNC_VAL BIT(17)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_WIDTH 28
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB 0
#define _DMA_V2_SPEC_DEV_B_XB_IDX (_DMA_V2_SPEC_DEV_A_XB_IDX + _DMA_V2_SPEC_DEV_A_XB_BITS)
#define _DMA_V2_SPEC_DEV_B_XB_BITS 8
#define _DMA_V2_SPEC_YB_IDX (_DMA_V2_SPEC_DEV_B_XB_IDX + _DMA_V2_SPEC_DEV_B_XB_BITS)
-#define _DMA_V2_SPEC_YB_BITS (32-_DMA_V2_SPEC_DEV_B_XB_BITS-_DMA_V2_SPEC_DEV_A_XB_BITS-_DMA_V2_CMD_BITS-_DMA_V2_CHANNEL_BITS)
+#define _DMA_V2_SPEC_YB_BITS (32 - _DMA_V2_SPEC_DEV_B_XB_BITS - _DMA_V2_SPEC_DEV_A_XB_BITS - _DMA_V2_CMD_BITS - _DMA_V2_CHANNEL_BITS)
/* */
#define _DMA_V2_CMD_CTRL_IDX 4
#define _DMA_V2_STRIDE_BITS 32
/* Command IDs */
-#define _DMA_V2_MOVE_B2A_COMMAND 0
-#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1
-#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2
-#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3
-#define _DMA_V2_MOVE_A2B_COMMAND 4
-#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5
-#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6
-#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7
-#define _DMA_V2_INIT_A_COMMAND 8
-#define _DMA_V2_INIT_A_BLOCK_COMMAND 9
-#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10
-#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11
-#define _DMA_V2_INIT_B_COMMAND 12
-#define _DMA_V2_INIT_B_BLOCK_COMMAND 13
-#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14
-#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15
-#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
-#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32
-#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33
-#define _DMA_V2_SET_CRUN_COMMAND 62
+#define _DMA_V2_MOVE_B2A_COMMAND 0
+#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1
+#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2
+#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3
+#define _DMA_V2_MOVE_A2B_COMMAND 4
+#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5
+#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6
+#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7
+#define _DMA_V2_INIT_A_COMMAND 8
+#define _DMA_V2_INIT_A_BLOCK_COMMAND 9
+#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10
+#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11
+#define _DMA_V2_INIT_B_COMMAND 12
+#define _DMA_V2_INIT_B_BLOCK_COMMAND 13
+#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14
+#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15
+#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
+#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32
+#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33
+#define _DMA_V2_SET_CRUN_COMMAND 62
/* Channel Parameter IDs */
-#define _DMA_V2_PACKING_SETUP_PARAM 0
-#define _DMA_V2_STRIDE_A_PARAM 1
-#define _DMA_V2_ELEM_CROPPING_A_PARAM 2
-#define _DMA_V2_WIDTH_A_PARAM 3
-#define _DMA_V2_STRIDE_B_PARAM 4
-#define _DMA_V2_ELEM_CROPPING_B_PARAM 5
-#define _DMA_V2_WIDTH_B_PARAM 6
-#define _DMA_V2_HEIGHT_PARAM 7
-#define _DMA_V2_QUEUED_CMDS 8
+#define _DMA_V2_PACKING_SETUP_PARAM 0
+#define _DMA_V2_STRIDE_A_PARAM 1
+#define _DMA_V2_ELEM_CROPPING_A_PARAM 2
+#define _DMA_V2_WIDTH_A_PARAM 3
+#define _DMA_V2_STRIDE_B_PARAM 4
+#define _DMA_V2_ELEM_CROPPING_B_PARAM 5
+#define _DMA_V2_WIDTH_B_PARAM 6
+#define _DMA_V2_HEIGHT_PARAM 7
+#define _DMA_V2_QUEUED_CMDS 8
/* Parameter Constants */
#define _DMA_V2_ZERO_EXTEND 0
#define _DMA_V2_ADDR_SEL_COMP_BITS 4
#define _DMA_V2_ADDR_SEL_CH_REG_IDX 2
#define _DMA_V2_ADDR_SEL_CH_REG_BITS 6
-#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS+_DMA_V2_ADDR_SEL_CH_REG_IDX)
+#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS + _DMA_V2_ADDR_SEL_CH_REG_IDX)
#define _DMA_V2_ADDR_SEL_PARAM_BITS 4
#define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX 2
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX 2
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS 6
-#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX+_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS)
+#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX + _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS)
#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS 4
#define _DMA_V2_FSM_GROUP_CMD_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_PACK_IDX 5
#define _DMA_V2_FSM_GROUP_FSM_REQ_IDX 6
#define _DMA_V2_FSM_GROUP_FSM_WR_IDX 7
-
+
#define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX 2
#define HRT_GDC_FRAC_BITS 10 /* Number of fractional bits in the GDC block, driven by the size of the LUT */
#define HRT_GDC_BLI_FRAC_BITS 4 /* Number of fractional bits for the bi-linear interpolation type */
-#define HRT_GDC_BLI_COEF_ONE (1 << HRT_GDC_BLI_FRAC_BITS)
+#define HRT_GDC_BLI_COEF_ONE BIT(HRT_GDC_BLI_FRAC_BITS)
#define HRT_GDC_BCI_COEF_BITS 14 /* 14 bits per coefficient */
-#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS-2)) /* We represent signed 10 bit coefficients. */
- /* The supported range is [-256, .., +256] */
- /* in 14-bit signed notation, */
- /* We need all ten bits (MSB must be zero). */
- /* -s is inserted to solve this issue, and */
- /* therefore "1" is equal to +256. */
-#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1)
+#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS - 2)) /* We represent signed 10 bit coefficients. */
+ /* The supported range is [-256, .., +256] */
+ /* in 14-bit signed notation, */
+ /* We need all ten bits (MSB must be zero). */
+ /* -s is inserted to solve this issue, and */
+ /* therefore "1" is equal to +256. */
+#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1)
-#define HRT_GDC_LUT_BYTES (HRT_GDC_N*4*2) /* 1024 addresses, 4 coefficients per address, */
- /* 2 bytes per coefficient */
+#define HRT_GDC_LUT_BYTES (HRT_GDC_N * 4 * 2) /* 1024 addresses, 4 coefficients per address, */
+ /* 2 bytes per coefficient */
-#define _HRT_GDC_REG_ALIGN 4
+#define _HRT_GDC_REG_ALIGN 4
// 31 30 29 25 24 0
// |-----|---|--------|------------------------|
// | CMD | C | Reg_ID | Value |
-
// There are just two commands possible for the GDC block:
- // 1 - Configure reg
- // 0 - Data token
-
+ // 1 - Configure reg
+ // 0 - Data token
+
// C - Reserved bit
// Used in protocol to indicate whether it is C-run or other type of runs
// In case of C-run, this bit has a value of 1, for all the other runs, it is 0.
// Reg_ID - Address of the register to be configured
-
+
// Value - Value to store to the addressed register, maximum of 24 bits
- // Configure reg command is not followed by any other token.
- // The address of the register and the data to be filled in is contained in the same token
-
+ // Configure reg command is not followed by any other token.
+ // The address of the register and the data to be filled in is contained in the same token
+
// When the first data token is received, it must be:
// 1. FRX and FRY (device configured in one of the scaling modes) ***DEFAULT MODE***, or,
// 2. P0'X (device configured in one of the tetragon modes)
// After the first data token is received, pre-defined number of tokens with the following meaning follow:
// 1. two tokens: SRC address ; DST address
// 2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address
-
+
#define HRT_GDC_CONFIG_CMD 1
#define HRT_GDC_DATA_CMD 0
-
#define HRT_GDC_CMD_POS 31
#define HRT_GDC_CMD_BITS 1
#define HRT_GDC_CRUN_POS 30
#define HRT_GDC_FRYIPXFRX_BITS 26
#define HRT_GDC_P0X_BITS 23
-
-#define HRT_GDC_MAX_OXDIM (8192-64)
+#define HRT_GDC_MAX_OXDIM (8192 - 64)
#define HRT_GDC_MAX_OYDIM 4095
-#define HRT_GDC_MAX_IXDIM (8192-64)
+#define HRT_GDC_MAX_IXDIM (8192 - 64)
#define HRT_GDC_MAX_IYDIM 4095
#define HRT_GDC_MAX_DS_FAC 16
-#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC*HRT_GDC_N - 1)
+#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC * HRT_GDC_N - 1)
#define HRT_GDC_MAX_DY HRT_GDC_MAX_DX
-
/* GDC lookup tables entries are 10 bits values, but they're
stored 2 by 2 as 32 bit values, yielding 16 bits per entry.
A GDC lookup table contains 64 * 4 elements */
#define HRT_GDC_MODE_SCALING 0
#define HRT_GDC_MODE_TETRAGON 1
-#define HRT_GDC_LUT_COEFF_OFFSET 16
-#define HRT_GDC_FRY_BIT_OFFSET 16
-// FRYIPXFRX is the only register where we store two values in one field,
-// to save one token in the scaling protocol.
-// Like this, we have three tokens in the scaling protocol,
+#define HRT_GDC_LUT_COEFF_OFFSET 16
+#define HRT_GDC_FRY_BIT_OFFSET 16
+// FRYIPXFRX is the only register where we store two values in one field,
+// to save one token in the scaling protocol.
+// Like this, we have three tokens in the scaling protocol,
// Otherwise, we would have had four.
// The register bit-map is:
// 31 26 25 16 15 10 9 0
// |------|----------|------|----------|
// | XXXX | FRY | IPX | FRX |
-
#define HRT_GDC_CE_FSM0_POS 0
#define HRT_GDC_CE_FSM0_LEN 2
#define HRT_GDC_CE_OPY_POS 2
// 31 16 15 2 1 0
// |----------------|-----------|----|
// | OPX | OPY |FSM0|
-// However, for the time being at least,
+// However, for the time being at least,
// this implementation is meaningless in hss model,
// So, we just return 0
-
#define HRT_GDC_CHK_ENGINE_IDX 0
#define HRT_GDC_WOIX_IDX 1
#define HRT_GDC_WOIY_IDX 2
#define HRT_GDC_LUT_IDX 32
-
#endif /* HRT_GDC_v2_defs_h_ */
#define HIVE_GP_TIMER_RESET_REG_IDX 0
#define HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX 1
#define HIVE_GP_TIMER_ENABLE_REG_IDX(timer) (HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX + 1 + timer)
-#define HIVE_GP_TIMER_VALUE_REG_IDX(timer,timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer)
-#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer,timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer)
-#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer,timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer)
-#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq,timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq)
-#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq)
-#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq)
+#define HIVE_GP_TIMER_VALUE_REG_IDX(timer, timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer)
+#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer, timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer)
+#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer, timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer)
+#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq, timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq)
+#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq)
+#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq)
#define HIVE_GP_TIMER_COUNT_TYPE_HIGH 0
#define HIVE_GP_TIMER_COUNT_TYPE_LOW 1
#define HIVE_GP_TIMER_COUNT_TYPE_NEGEDGE 3
#define HIVE_GP_TIMER_COUNT_TYPES 4
-#endif /* _gp_timer_defs_h */
+#endif /* _gp_timer_defs_h */
#define _gpio_block_reg_di_debounce_cnt_3 14
#define _gpio_block_reg_di_active_level 15
-
/* read-only registers */
#define _gpio_block_reg_di 16
* The definitions are taken from <system>_defs.h
*/
typedef enum hrt_isp_css_irq {
- hrt_isp_css_irq_gpio_pin_0 = HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_1 = HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_2 = HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_3 = HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_4 = HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_5 = HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_6 = HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_7 = HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_8 = HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_9 = HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_10 = HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID ,
- hrt_isp_css_irq_gpio_pin_11 = HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID ,
- hrt_isp_css_irq_sp = HIVE_GP_DEV_IRQ_SP_BIT_ID ,
- hrt_isp_css_irq_isp = HIVE_GP_DEV_IRQ_ISP_BIT_ID ,
- hrt_isp_css_irq_isys = HIVE_GP_DEV_IRQ_ISYS_BIT_ID ,
- hrt_isp_css_irq_isel = HIVE_GP_DEV_IRQ_ISEL_BIT_ID ,
- hrt_isp_css_irq_ifmt = HIVE_GP_DEV_IRQ_IFMT_BIT_ID ,
- hrt_isp_css_irq_sp_stream_mon = HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID ,
- hrt_isp_css_irq_isp_stream_mon = HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID ,
- hrt_isp_css_irq_mod_stream_mon = HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID ,
- hrt_isp_css_irq_is2401 = HIVE_GP_DEV_IRQ_IS2401_BIT_ID ,
- hrt_isp_css_irq_isp_bamem_error = HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID ,
- hrt_isp_css_irq_isp_dmem_error = HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID ,
- hrt_isp_css_irq_sp_icache_mem_error = HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID ,
- hrt_isp_css_irq_sp_dmem_error = HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID ,
- hrt_isp_css_irq_mmu_cache_mem_error = HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID ,
- hrt_isp_css_irq_gp_timer_0 = HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID ,
- hrt_isp_css_irq_gp_timer_1 = HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID ,
- hrt_isp_css_irq_sw_pin_0 = HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID ,
- hrt_isp_css_irq_sw_pin_1 = HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID ,
- hrt_isp_css_irq_dma = HIVE_GP_DEV_IRQ_DMA_BIT_ID ,
- hrt_isp_css_irq_sp_stream_mon_b = HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID ,
+ hrt_isp_css_irq_gpio_pin_0 = HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_1 = HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_2 = HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_3 = HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_4 = HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_5 = HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_6 = HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_7 = HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_8 = HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_9 = HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_10 = HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID,
+ hrt_isp_css_irq_gpio_pin_11 = HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID,
+ hrt_isp_css_irq_sp = HIVE_GP_DEV_IRQ_SP_BIT_ID,
+ hrt_isp_css_irq_isp = HIVE_GP_DEV_IRQ_ISP_BIT_ID,
+ hrt_isp_css_irq_isys = HIVE_GP_DEV_IRQ_ISYS_BIT_ID,
+ hrt_isp_css_irq_isel = HIVE_GP_DEV_IRQ_ISEL_BIT_ID,
+ hrt_isp_css_irq_ifmt = HIVE_GP_DEV_IRQ_IFMT_BIT_ID,
+ hrt_isp_css_irq_sp_stream_mon = HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID,
+ hrt_isp_css_irq_isp_stream_mon = HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID,
+ hrt_isp_css_irq_mod_stream_mon = HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID,
+ hrt_isp_css_irq_is2401 = HIVE_GP_DEV_IRQ_IS2401_BIT_ID,
+ hrt_isp_css_irq_isp_bamem_error = HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID,
+ hrt_isp_css_irq_isp_dmem_error = HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID,
+ hrt_isp_css_irq_sp_icache_mem_error = HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID,
+ hrt_isp_css_irq_sp_dmem_error = HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID,
+ hrt_isp_css_irq_mmu_cache_mem_error = HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID,
+ hrt_isp_css_irq_gp_timer_0 = HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID,
+ hrt_isp_css_irq_gp_timer_1 = HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID,
+ hrt_isp_css_irq_sw_pin_0 = HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID,
+ hrt_isp_css_irq_sw_pin_1 = HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID,
+ hrt_isp_css_irq_dma = HIVE_GP_DEV_IRQ_DMA_BIT_ID,
+ hrt_isp_css_irq_sp_stream_mon_b = HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID,
/* this must (obviously) be the last on in the enum */
hrt_isp_css_irq_num_irqs
} hrt_isp_css_irq_t;
and in the DMA parameter list */
#define HIVE_ISP_DDR_DMA_SPECS {{32, 8}, {16, 16}, {18, 14}, {25, 10}, {21, 12}}
#define HIVE_ISP_DDR_WORD_BITS 256
-#define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS/8)
+#define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS / 8)
#define HIVE_ISP_DDR_BYTES (512 * 1024 * 1024)
#define HIVE_ISP_DDR_BYTES_RTL (127 * 1024 * 1024)
#define HIVE_ISP_DDR_SMALL_BYTES (128 * 256 / 8)
#define HIVE_ISP_PAGE_SHIFT 12
-#define HIVE_ISP_PAGE_SIZE (1<<HIVE_ISP_PAGE_SHIFT)
+#define HIVE_ISP_PAGE_SIZE BIT(HIVE_ISP_PAGE_SHIFT)
#define CSS_DDR_WORD_BITS HIVE_ISP_DDR_WORD_BITS
#define CSS_DDR_WORD_BYTES HIVE_ISP_DDR_WORD_BYTES
#define HIVE_VMEM_VECTOR_ELEMENTS 64
#define HIVE_VMEM_ELEMENT_BITS 14
#define HIVE_XMEM_ELEMENT_BITS 16
-#define HIVE_VMEM_VECTOR_BYTES (HIVE_VMEM_VECTOR_ELEMENTS*HIVE_XMEM_ELEMENT_BITS/8) /* used for # addr bytes for one vector */
-#define HIVE_XMEM_PACKED_WORD_VMEM_ELEMENTS (HIVE_XMEM_WIDTH/HIVE_VMEM_ELEMENT_BITS)
-#define HIVE_XMEM_WORD_VMEM_ELEMENTS (HIVE_XMEM_WIDTH/HIVE_XMEM_ELEMENT_BITS)
+#define HIVE_VMEM_VECTOR_BYTES (HIVE_VMEM_VECTOR_ELEMENTS * HIVE_XMEM_ELEMENT_BITS / 8) /* used for # addr bytes for one vector */
+#define HIVE_XMEM_PACKED_WORD_VMEM_ELEMENTS (HIVE_XMEM_WIDTH / HIVE_VMEM_ELEMENT_BITS)
+#define HIVE_XMEM_WORD_VMEM_ELEMENTS (HIVE_XMEM_WIDTH / HIVE_XMEM_ELEMENT_BITS)
#define XMEM_INT_SIZE 4
-
-
-#define HIVE_ISYS_INP_BUFFER_BYTES (64*1024) /* 64 kByte = 2k words (of 256 bits) */
+#define HIVE_ISYS_INP_BUFFER_BYTES (64 * 1024) /* 64 kByte = 2k words (of 256 bits) */
/* If HIVE_ISP_DDR_BASE_OFFSET is set to a non-zero value, the wide bus just before the DDRAM gets an extra dummy port where */
/* address range 0 .. HIVE_ISP_DDR_BASE_OFFSET-1 maps onto. This effectively creates an offset for the DDRAM from system perspective */
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I4_I0 51
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I5_I0 52
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I6_I0 53
-#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I7_I0 54
+#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I7_I0 54
#define HIVE_GP_TIMER_MIPI_SOL_BIT_ID 55
#define HIVE_GP_TIMER_MIPI_EOL_BIT_ID 56
#define HIVE_GP_TIMER_MIPI_SOF_BIT_ID 57
/* port definititions SP streaming monitor, monitors the status of streaming ports at the SP side of the streaming FIFO's */
#define SP_STR_MON_PORT_SP2SIF 0
#define SP_STR_MON_PORT_SIF2SP 1
-#define SP_STR_MON_PORT_SP2MC 2
+#define SP_STR_MON_PORT_SP2MC 2
#define SP_STR_MON_PORT_MC2SP 3
-#define SP_STR_MON_PORT_SP2DMA 4
+#define SP_STR_MON_PORT_SP2DMA 4
#define SP_STR_MON_PORT_DMA2SP 5
-#define SP_STR_MON_PORT_SP2ISP 6
+#define SP_STR_MON_PORT_SP2ISP 6
#define SP_STR_MON_PORT_ISP2SP 7
#define SP_STR_MON_PORT_SP2GPD 8
#define SP_STR_MON_PORT_FA2SP 9
-#define SP_STR_MON_PORT_SP2ISYS 10
+#define SP_STR_MON_PORT_SP2ISYS 10
#define SP_STR_MON_PORT_ISYS2SP 11
#define SP_STR_MON_PORT_SP2PIFA 12
#define SP_STR_MON_PORT_PIFA2SP 13
/* port definititions ISP streaming monitor, monitors the status of streaming ports at the ISP side of the streaming FIFO's */
#define ISP_STR_MON_PORT_ISP2PIFA 0
#define ISP_STR_MON_PORT_PIFA2ISP 1
-#define ISP_STR_MON_PORT_ISP2PIFB 2
+#define ISP_STR_MON_PORT_ISP2PIFB 2
#define ISP_STR_MON_PORT_PIFB2ISP 3
-#define ISP_STR_MON_PORT_ISP2DMA 4
+#define ISP_STR_MON_PORT_ISP2DMA 4
#define ISP_STR_MON_PORT_DMA2ISP 5
-#define ISP_STR_MON_PORT_ISP2GDC1 6
+#define ISP_STR_MON_PORT_ISP2GDC1 6
#define ISP_STR_MON_PORT_GDC12ISP 7
-#define ISP_STR_MON_PORT_ISP2GDC2 8
+#define ISP_STR_MON_PORT_ISP2GDC2 8
#define ISP_STR_MON_PORT_GDC22ISP 9
-#define ISP_STR_MON_PORT_ISP2GPD 10
+#define ISP_STR_MON_PORT_ISP2GPD 10
#define ISP_STR_MON_PORT_FA2ISP 11
-#define ISP_STR_MON_PORT_ISP2SP 12
+#define ISP_STR_MON_PORT_ISP2SP 12
#define ISP_STR_MON_PORT_SP2ISP 13
/* previously used ISP streaming monitor port identifiers, kept for backward compatibility */
#define ISP_STR_MON_PORT_SND_PIF_A ISP_STR_MON_PORT_ISP2PIFA
#define ISP_STR_MON_PORT_RCV_PIF_A ISP_STR_MON_PORT_PIFA2ISP
-#define ISP_STR_MON_PORT_SND_PIF_B ISP_STR_MON_PORT_ISP2PIFB
+#define ISP_STR_MON_PORT_SND_PIF_B ISP_STR_MON_PORT_ISP2PIFB
#define ISP_STR_MON_PORT_RCV_PIF_B ISP_STR_MON_PORT_PIFB2ISP
-#define ISP_STR_MON_PORT_SND_DMA ISP_STR_MON_PORT_ISP2DMA
-#define ISP_STR_MON_PORT_RCV_DMA ISP_STR_MON_PORT_DMA2ISP
-#define ISP_STR_MON_PORT_SND_GDC ISP_STR_MON_PORT_ISP2GDC1
+#define ISP_STR_MON_PORT_SND_DMA ISP_STR_MON_PORT_ISP2DMA
+#define ISP_STR_MON_PORT_RCV_DMA ISP_STR_MON_PORT_DMA2ISP
+#define ISP_STR_MON_PORT_SND_GDC ISP_STR_MON_PORT_ISP2GDC1
#define ISP_STR_MON_PORT_RCV_GDC ISP_STR_MON_PORT_GDC12ISP
-#define ISP_STR_MON_PORT_SND_GPD ISP_STR_MON_PORT_ISP2GPD
+#define ISP_STR_MON_PORT_SND_GPD ISP_STR_MON_PORT_ISP2GPD
#define ISP_STR_MON_PORT_RCV_GPD ISP_STR_MON_PORT_FA2ISP
#define ISP_STR_MON_PORT_SND_SP ISP_STR_MON_PORT_ISP2SP
#define ISP_STR_MON_PORT_RCV_SP ISP_STR_MON_PORT_SP2ISP
-
+
/* port definititions MOD streaming monitor, monitors the status of streaming ports at the module side of the streaming FIFO's */
#define MOD_STR_MON_PORT_PIFA2CELLS 0
#define MOD_STR_MON_PORT_SND_GDC 12
#define MOD_STR_MON_PORT_RCV_GDC 13
-
/* testbench signals: */
/* testbench GP adapter register ids */
#define ISP testbench_isp_isp_css_sec_part_isp
#define SP testbench_isp_isp_css_sec_part_scp
-#define IF_PRIM testbench_isp_isp_css_part_is_2400_ifmt_ift_prim
+#define IF_PRIM testbench_isp_isp_css_part_is_2400_ifmt_ift_prim
#define IF_PRIM_B testbench_isp_isp_css_part_is_2400_ifmt_ift_prim_b
#define IF_SEC testbench_isp_isp_css_part_is_2400_ifmt_ift_sec
#define IF_SEC_MASTER testbench_isp_isp_css_part_is_2400_ifmt_ift_sec_mt_out
#define ISYS2401_IBUF_CNTRL_C testbench_isp_isp_css_part_is_2401_is_pipe_c_ibuf_ctrl
#define ISYS2401_IRQ_CTRL_C testbench_isp_isp_css_part_is_2401_is_pipe_c_irq_ctrl_pipe
-
/* Testbench identifiers */
#define DDR testbench_ddram
#define DDR_SMALL testbench_ddram_small
#include <streaming_to_mipi_defs.h>
-#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS)-1)
-#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS)-1)
+#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS) - 1)
+#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS) - 1)
#define _HIVE_STR_TO_MIPI_FMT_TYPE_LSB (HIVE_STR_TO_MIPI_CH_ID_LSB + HIVE_ISP_CH_ID_BITS)
#define _HIVE_STR_TO_MIPI_DATA_B_LSB (HIVE_STR_TO_MIPI_DATA_A_LSB + HIVE_IF_PIXEL_WIDTH)
-
+
#endif /* _hive_isp_css_streaming_to_mipi_types_hrt_h_ */
* more details.
*/
-#ifndef _HRT_HIVE_TYPES_H
-#define _HRT_HIVE_TYPES_H
+#ifndef _HRT_HIVE_TYPES_H
+#define _HRT_HIVE_TYPES_H
#include "version.h"
#include "defs.h"
#ifndef HRTCAT3
-#define _HRTCAT3(m,n,o) m##n##o
-#define HRTCAT3(m,n,o) _HRTCAT3(m,n,o)
+#define _HRTCAT3(m, n, o) m##n##o
+#define HRTCAT3(m, n, o) _HRTCAT3(m, n, o)
#endif
#ifndef HRTCAT4
-#define _HRTCAT4(m,n,o,p) m##n##o##p
-#define HRTCAT4(m,n,o,p) _HRTCAT4(m,n,o,p)
+#define _HRTCAT4(m, n, o, p) m##n##o##p
+#define HRTCAT4(m, n, o, p) _HRTCAT4(m, n, o, p)
#endif
#ifndef HRTMIN
-#define HRTMIN(a,b) (((a)<(b))?(a):(b))
+#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
-
+
#ifndef HRTMAX
-#define HRTMAX(a,b) (((a)>(b))?(a):(b))
+#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
/* boolean data type */
#define HRT_ADDRESS_WIDTH 32
#endif
-#define HRT_DATA_BYTES (HRT_DATA_WIDTH/8)
-#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH/8)
+#define HRT_DATA_BYTES (HRT_DATA_WIDTH / 8)
+#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH / 8)
#if HRT_DATA_WIDTH == 64
typedef hive_uint64 hrt_data;
#endif
#if HRT_ADDRESS_WIDTH == 64
-typedef hive_uint64 hrt_address;
+typedef hive_uint64 hrt_address;
#elif HRT_ADDRESS_WIDTH == 32
typedef hive_uint32 hrt_address;
#else
typedef hive_uint hive_mmio_id;
typedef hive_mmio_id hive_slave_id;
typedef hive_mmio_id hive_port_id;
-typedef hive_mmio_id hive_master_id;
+typedef hive_mmio_id hive_master_id;
typedef hive_mmio_id hive_mem_id;
typedef hive_mmio_id hive_dev_id;
typedef hive_mmio_id hive_fifo_id;
typedef hive_uint hive_msink_id;
/* HRT specific */
-typedef char* hive_program;
-typedef char* hive_function;
+typedef char *hive_program;
+typedef char *hive_function;
#endif /* _HRT_HIVE_TYPES_H */
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_4 4
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_5 5
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_6 6
-#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7
+#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_FSYNC_LUT_REG 8
#define HIVE_IFMT_GP_REGS_SRST_IDX 9
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IDX 10
#define HIVE_ISEL_GP_REGS_SYNCGEN_ENABLE_IDX 0
#define HIVE_ISEL_GP_REGS_SYNCGEN_FREE_RUNNING_IDX 1
#define HIVE_ISEL_GP_REGS_SYNCGEN_PAUSE_IDX 2
-#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_FRAMES_IDX 3
-#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_PIX_IDX 4
-#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_LINES_IDX 5
-#define HIVE_ISEL_GP_REGS_SYNCGEN_HBLANK_CYCLES_IDX 6
-#define HIVE_ISEL_GP_REGS_SYNCGEN_VBLANK_CYCLES_IDX 7
+#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_FRAMES_IDX 3
+#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_PIX_IDX 4
+#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_LINES_IDX 5
+#define HIVE_ISEL_GP_REGS_SYNCGEN_HBLANK_CYCLES_IDX 6
+#define HIVE_ISEL_GP_REGS_SYNCGEN_VBLANK_CYCLES_IDX 7
-#define HIVE_ISEL_GP_REGS_SOF_IDX 8
-#define HIVE_ISEL_GP_REGS_EOF_IDX 9
-#define HIVE_ISEL_GP_REGS_SOL_IDX 10
-#define HIVE_ISEL_GP_REGS_EOL_IDX 11
+#define HIVE_ISEL_GP_REGS_SOF_IDX 8
+#define HIVE_ISEL_GP_REGS_EOF_IDX 9
+#define HIVE_ISEL_GP_REGS_SOL_IDX 10
+#define HIVE_ISEL_GP_REGS_EOL_IDX 11
-#define HIVE_ISEL_GP_REGS_PRBS_ENABLE 12
-#define HIVE_ISEL_GP_REGS_PRBS_ENABLE_PORT_B 13
-#define HIVE_ISEL_GP_REGS_PRBS_LFSR_RESET_VALUE 14
+#define HIVE_ISEL_GP_REGS_PRBS_ENABLE 12
+#define HIVE_ISEL_GP_REGS_PRBS_ENABLE_PORT_B 13
+#define HIVE_ISEL_GP_REGS_PRBS_LFSR_RESET_VALUE 14
-#define HIVE_ISEL_GP_REGS_TPG_ENABLE 15
-#define HIVE_ISEL_GP_REGS_TPG_ENABLE_PORT_B 16
-#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_MASK_IDX 17
-#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_MASK_IDX 18
-#define HIVE_ISEL_GP_REGS_TPG_XY_CNT_MASK_IDX 19
-#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_DELTA_IDX 20
-#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_DELTA_IDX 21
-#define HIVE_ISEL_GP_REGS_TPG_MODE_IDX 22
-#define HIVE_ISEL_GP_REGS_TPG_R1_IDX 23
+#define HIVE_ISEL_GP_REGS_TPG_ENABLE 15
+#define HIVE_ISEL_GP_REGS_TPG_ENABLE_PORT_B 16
+#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_MASK_IDX 17
+#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_MASK_IDX 18
+#define HIVE_ISEL_GP_REGS_TPG_XY_CNT_MASK_IDX 19
+#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_DELTA_IDX 20
+#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_DELTA_IDX 21
+#define HIVE_ISEL_GP_REGS_TPG_MODE_IDX 22
+#define HIVE_ISEL_GP_REGS_TPG_R1_IDX 23
#define HIVE_ISEL_GP_REGS_TPG_G1_IDX 24
#define HIVE_ISEL_GP_REGS_TPG_B1_IDX 25
#define HIVE_ISEL_GP_REGS_TPG_R2_IDX 26
#define HIVE_ISEL_GP_REGS_TPG_G2_IDX 27
#define HIVE_ISEL_GP_REGS_TPG_B2_IDX 28
-
#define HIVE_ISEL_GP_REGS_CH_ID_IDX 29
#define HIVE_ISEL_GP_REGS_FMT_TYPE_IDX 30
#define HIVE_ISEL_GP_REGS_DATA_SEL_IDX 31
#ifndef _input_switch_2400_defs_h
#define _input_switch_2400_defs_h
-#define _HIVE_INPUT_SWITCH_GET_LUT_REG_ID(ch_id, fmt_type) (((ch_id)*2) + ((fmt_type)>=16))
-#define _HIVE_INPUT_SWITCH_GET_LUT_REG_LSB(fmt_type) (((fmt_type)%16) * 2)
+#define _HIVE_INPUT_SWITCH_GET_LUT_REG_ID(ch_id, fmt_type) (((ch_id) * 2) + ((fmt_type) >= 16))
+#define _HIVE_INPUT_SWITCH_GET_LUT_REG_LSB(fmt_type) (((fmt_type) % 16) * 2)
#define HIVE_INPUT_SWITCH_SELECT_NO_OUTPUT 0
#define HIVE_INPUT_SWITCH_SELECT_IF_PRIM 1
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID 20
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID 21
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID 22
-
/* register reset value */
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL 128
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL 128
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL 128
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL 3
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL 3
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL 3
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL 3
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL 3
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL 3
#define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL 0
-#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL 128
-#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3
+#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL 128
+#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3
#define ISYS_CTRL_INIT_REG_RSTVAL 0
-#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
+#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL 0
-#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL 0
+#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL 0
/* register width value */
-#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH 9
-#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH 9
-#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH 9
-#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH 9
-#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
-#define ISYS_CTRL_INIT_REG_WIDTH 3
+#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH 9
+#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH 9
+#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH 9
+#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH 9
+#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
+#define ISYS_CTRL_INIT_REG_WIDTH 3
#define ISYS_CTRL_LAST_COMMAND_REG_WIDTH 32 /* slave data width */
#define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH 32
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH 32
/*
InpSysCaptFramesAcq 1/0 [3:0] - 'b0000
[7:4] - CaptPortId,
- CaptA-'b0000
- CaptB-'b0001
- CaptC-'b0010
+ CaptA-'b0000
+ CaptB-'b0001
+ CaptC-'b0010
[31:16] - NOF_frames
InpSysCaptFrameExt 2/0 [3:0] - 'b0001'
[7:4] - CaptPortId,
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
2/1 [31:0] - external capture address
-InpSysAcqFrame 2/0 [3:0] - 'b0010,
+InpSysAcqFrame 2/0 [3:0] - 'b0010,
[31:4] - NOF_ext_mem_words
2/1 [31:0] - external memory read start address
-InpSysOverruleON 1/0 [3:0] - 'b0011,
+InpSysOverruleON 1/0 [3:0] - 'b0011,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
-
-InpSysOverruleOFF 1/0 [3:0] - 'b0100,
+InpSysOverruleOFF 1/0 [3:0] - 'b0100,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
-
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
-InpSysOverruleCmd 2/0 [3:0] - 'b0101,
+InpSysOverruleCmd 2/0 [3:0] - 'b0101,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
-
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
2/1 [31:0] - command token value for port opid
-
acknowledge tokens:
InpSysAckCFA 1/0 [3:0] - 'b0000
[7:4] - CaptPortId,
- CaptA-'b0000
- CaptB- 'b0001
- CaptC-'b0010
+ CaptA-'b0000
+ CaptB- 'b0001
+ CaptC-'b0010
[31:16] - NOF_frames
InpSysAckCFE 1/0 [3:0] - 'b0001'
[7:4] - CaptPortId,
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
InpSysAckAF 1/0 [3:0] - 'b0010
-InpSysAckOverruleON 1/0 [3:0] - 'b0011,
+InpSysAckOverruleON 1/0 [3:0] - 'b0011,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
-
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
-InpSysAckOverruleOFF 1/0 [3:0] - 'b0100,
+InpSysAckOverruleOFF 1/0 [3:0] - 'b0100,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
-
-InpSysAckOverrule 2/0 [3:0] - 'b0101,
+InpSysAckOverrule 2/0 [3:0] - 'b0101,
[7:4] - overrule port id (opid)
- 'b0000 - CaptA
- 'b0001 - CaptB
- 'b0010 - CaptC
- 'b0011 - Acq
- 'b0100 - DMA
-
+ 'b0000 - CaptA
+ 'b0001 - CaptB
+ 'b0010 - CaptC
+ 'b0011 - Acq
+ 'b0100 - DMA
2/1 [31:0] - acknowledge token value from port opid
-
-
*/
-
/* Command and acknowledge tokens IDs */
#define ISYS_CTRL_CAPT_FRAMES_ACQ_TOKEN_ID 0 /* 0000b */
#define ISYS_CTRL_CAPT_FRAME_EXT_TOKEN_ID 1 /* 0001b */
#define ISYS_CTRL_TOKEN_ID_IDX 0
#define ISYS_CTRL_TOKEN_ID_BITS (ISYS_CTRL_TOKEN_ID_MSB - ISYS_CTRL_TOKEN_ID_LSB + 1)
#define ISYS_CTRL_PORT_ID_IDX (ISYS_CTRL_TOKEN_ID_IDX + ISYS_CTRL_TOKEN_ID_BITS)
-#define ISYS_CTRL_PORT_ID_BITS (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB +1)
-#define ISYS_CTRL_NOF_CAPT_IDX ISYS_CTRL_NOF_CAPT_TOKEN_LSB
+#define ISYS_CTRL_PORT_ID_BITS (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB + 1)
+#define ISYS_CTRL_NOF_CAPT_IDX ISYS_CTRL_NOF_CAPT_TOKEN_LSB
#define ISYS_CTRL_NOF_CAPT_BITS (ISYS_CTRL_NOF_CAPT_TOKEN_MSB - ISYS_CTRL_NOF_CAPT_TOKEN_LSB + 1)
-#define ISYS_CTRL_NOF_EXT_IDX ISYS_CTRL_NOF_EXT_TOKEN_LSB
+#define ISYS_CTRL_NOF_EXT_IDX ISYS_CTRL_NOF_EXT_TOKEN_LSB
#define ISYS_CTRL_NOF_EXT_BITS (ISYS_CTRL_NOF_EXT_TOKEN_MSB - ISYS_CTRL_NOF_EXT_TOKEN_LSB + 1)
#define ISYS_CTRL_PORT_ID_CAPT_A 0 /* device ID for capture unit A */
#define ISYS_CTRL_PORT_ID_DMA_ACQ 7 /* device ID for dma unit */
#define ISYS_CTRL_NO_ACQ_ACK 16 /* no ack from acquisition unit */
-#define ISYS_CTRL_NO_DMA_ACK 0
+#define ISYS_CTRL_NO_DMA_ACK 0
#define ISYS_CTRL_NO_CAPT_ACK 16
-#endif /* _input_system_ctrl_defs_h */
+#endif /* _input_system_ctrl_defs_h */
#define _HRT_IRQ_CONTROLLER_REG_ALIGN 4
-#endif /* _irq_controller_defs_h */
+#endif /* _irq_controller_defs_h */
#define ISP_SRU_GUARDING 1
#define ISP_VLSU_GUARDING 1
-#define ISP_VRF_RAM 1
-#define ISP_SRF_RAM 1
+#define ISP_VRF_RAM 1
+#define ISP_SRF_RAM 1
#define ISP_SPLIT_VMUL_VADD_IS 0
#define ISP_RFSPLIT_FPGA 0
#define ISP_NWAY ISP_VEC_NELEMS
#define NBITS ISP_VEC_ELEMBITS
-#define _isp_ceil_div(a,b) (((a)+(b)-1)/(b))
+#define _isp_ceil_div(a, b) (((a) + (b) - 1) / (b))
#ifdef C_RUN
-#define ISP_VEC_ALIGN (_isp_ceil_div(ISP_VEC_WIDTH, 64)*8)
+#define ISP_VEC_ALIGN (_isp_ceil_div(ISP_VEC_WIDTH, 64) * 8)
#else
#define ISP_VEC_ALIGN ISP_VMEM_ALIGN
#endif
#define _isp_acquisition_defs_h
#define _ISP_ACQUISITION_REG_ALIGN 4 /* assuming 32 bit control bus width */
-#define _ISP_ACQUISITION_BYTES_PER_ELEM 4
+#define _ISP_ACQUISITION_BYTES_PER_ELEM 4
/* --------------------------------------------------*/
/* REGISTER INFO */
/* --------------------------------------------------*/
-#define NOF_ACQ_REGS 12
+#define NOF_ACQ_REGS 12
// Register id's of MMIO slave accesible registers
-#define ACQ_START_ADDR_REG_ID 0
+#define ACQ_START_ADDR_REG_ID 0
#define ACQ_MEM_REGION_SIZE_REG_ID 1
#define ACQ_NUM_MEM_REGIONS_REG_ID 2
-#define ACQ_INIT_REG_ID 3
+#define ACQ_INIT_REG_ID 3
#define ACQ_RECEIVED_SHORT_PACKETS_REG_ID 4
#define ACQ_RECEIVED_LONG_PACKETS_REG_ID 5
#define ACQ_LAST_COMMAND_REG_ID 6
#define ACQ_NEXT_ACKNOWLEDGE_REG_ID 9
#define ACQ_FSM_STATE_INFO_REG_ID 10
#define ACQ_INT_CNTR_INFO_REG_ID 11
-
+
// Register width
-#define ACQ_START_ADDR_REG_WIDTH 9
-#define ACQ_MEM_REGION_SIZE_REG_WIDTH 9
-#define ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
-#define ACQ_INIT_REG_WIDTH 3
-#define ACQ_RECEIVED_SHORT_PACKETS_REG_WIDTH 32
-#define ACQ_RECEIVED_LONG_PACKETS_REG_WIDTH 32
-#define ACQ_LAST_COMMAND_REG_WIDTH 32
-#define ACQ_NEXT_COMMAND_REG_WIDTH 32
-#define ACQ_LAST_ACKNOWLEDGE_REG_WIDTH 32
-#define ACQ_NEXT_ACKNOWLEDGE_REG_WIDTH 32
-#define ACQ_FSM_STATE_INFO_REG_WIDTH ((MEM2STREAM_FSM_STATE_BITS * 3) + (ACQ_SYNCHRONIZER_FSM_STATE_BITS *3))
+#define ACQ_START_ADDR_REG_WIDTH 9
+#define ACQ_MEM_REGION_SIZE_REG_WIDTH 9
+#define ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
+#define ACQ_INIT_REG_WIDTH 3
+#define ACQ_RECEIVED_SHORT_PACKETS_REG_WIDTH 32
+#define ACQ_RECEIVED_LONG_PACKETS_REG_WIDTH 32
+#define ACQ_LAST_COMMAND_REG_WIDTH 32
+#define ACQ_NEXT_COMMAND_REG_WIDTH 32
+#define ACQ_LAST_ACKNOWLEDGE_REG_WIDTH 32
+#define ACQ_NEXT_ACKNOWLEDGE_REG_WIDTH 32
+#define ACQ_FSM_STATE_INFO_REG_WIDTH ((MEM2STREAM_FSM_STATE_BITS * 3) + (ACQ_SYNCHRONIZER_FSM_STATE_BITS * 3))
#define ACQ_INT_CNTR_INFO_REG_WIDTH 32
/* register reset value */
-#define ACQ_START_ADDR_REG_RSTVAL 0
+#define ACQ_START_ADDR_REG_RSTVAL 0
#define ACQ_MEM_REGION_SIZE_REG_RSTVAL 128
#define ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3
-#define ACQ_INIT_REG_RSTVAL 0
+#define ACQ_INIT_REG_RSTVAL 0
#define ACQ_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0
#define ACQ_RECEIVED_LONG_PACKETS_REG_RSTVAL 0
#define ACQ_LAST_COMMAND_REG_RSTVAL 0
#define ACQ_NEXT_COMMAND_REG_RSTVAL 0
#define ACQ_LAST_ACKNOWLEDGE_REG_RSTVAL 0
-#define ACQ_NEXT_ACKNOWLEDGE_REG_RSTVAL 0
+#define ACQ_NEXT_ACKNOWLEDGE_REG_RSTVAL 0
#define ACQ_FSM_STATE_INFO_REG_RSTVAL 0
-#define ACQ_INT_CNTR_INFO_REG_RSTVAL 0
+#define ACQ_INT_CNTR_INFO_REG_RSTVAL 0
/* bit definitions */
#define ACQ_INIT_RST_REG_BIT 0
/* TOKEN INFO */
/* --------------------------------------------------*/
#define ACQ_TOKEN_ID_LSB 0
-#define ACQ_TOKEN_ID_MSB 3
+#define ACQ_TOKEN_ID_MSB 3
#define ACQ_TOKEN_WIDTH (ACQ_TOKEN_ID_MSB - ACQ_TOKEN_ID_LSB + 1) // 4
#define ACQ_TOKEN_ID_IDX 0
#define ACQ_TOKEN_ID_BITS ACQ_TOKEN_WIDTH
#define ACQ_CMD_START_ADDR_IDX 4
#define ACQ_CMD_START_ADDR_BITS 9
#define ACQ_CMD_NOFWORDS_IDX 13
-#define ACQ_CMD_NOFWORDS_BITS 9
+#define ACQ_CMD_NOFWORDS_BITS 9
#define ACQ_MEM_REGION_ID_IDX 22
-#define ACQ_MEM_REGION_ID_BITS 9
+#define ACQ_MEM_REGION_ID_BITS 9
#define ACQ_PACKET_LENGTH_TOKEN_MSB 21
#define ACQ_PACKET_LENGTH_TOKEN_LSB 13
#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_MSB 9
#define ACQ_PACKET_MEM_REGION_ID_TOKEN_MSB 12 /* only for capt_end_of_packet_written */
#define ACQ_PACKET_MEM_REGION_ID_TOKEN_LSB 4 /* only for capt_end_of_packet_written */
-
/* Command tokens IDs */
#define ACQ_READ_REGION_AUTO_INCR_TOKEN_ID 0 //0000b
#define ACQ_READ_REGION_TOKEN_ID 1 //0001b
-#define ACQ_READ_REGION_SOP_TOKEN_ID 2 //0010b
+#define ACQ_READ_REGION_SOP_TOKEN_ID 2 //0010b
#define ACQ_INIT_TOKEN_ID 8 //1000b
/* Acknowledge token IDs */
#define ACQ_TOKEN_NOFWORDS_MSB 21
#define ACQ_TOKEN_NOFWORDS_LSB 13
#define ACQ_TOKEN_STARTADDR_MSB 12
-#define ACQ_TOKEN_STARTADDR_LSB 4
-
+#define ACQ_TOKEN_STARTADDR_LSB 4
/* --------------------------------------------------*/
/* MIPI */
/* --------------------------------------------------*/
#define WORD_COUNT_WIDTH 16
-#define PKT_CODE_WIDTH 6
-#define CHN_NO_WIDTH 2
+#define PKT_CODE_WIDTH 6
+#define CHN_NO_WIDTH 2
#define ERROR_INFO_WIDTH 8
-
+
#define LONG_PKTCODE_MAX 63
#define LONG_PKTCODE_MIN 16
#define SHORT_PKTCODE_MAX 15
#define ACQ_LINE_PAYLOAD 4
#define ACQ_GEN_SH_PKT 5
-
/* bit definition */
#define ACQ_PKT_TYPE_IDX 16
#define ACQ_PKT_TYPE_BITS 6
#define ACQ_ACK_PKT_LEN_IDX 4
#define ACQ_ACK_PKT_LEN_BITS 16
-
/* --------------------------------------------------*/
/* Packet Data Type */
/* --------------------------------------------------*/
-
#define ACQ_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */
#define ACQ_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */
#define ACQ_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */
#define ACQ_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */
#define ACQ_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */
#define ACQ_RGB444_DATA 32 /* 10 0000 RGB444 */
-#define ACQ_RGB555_DATA 33 /* 10 0001 RGB555 */
-#define ACQ_RGB565_DATA 34 /* 10 0010 RGB565 */
-#define ACQ_RGB666_DATA 35 /* 10 0011 RGB666 */
-#define ACQ_RGB888_DATA 36 /* 10 0100 RGB888 */
-#define ACQ_RAW6_DATA 40 /* 10 1000 RAW6 */
-#define ACQ_RAW7_DATA 41 /* 10 1001 RAW7 */
-#define ACQ_RAW8_DATA 42 /* 10 1010 RAW8 */
-#define ACQ_RAW10_DATA 43 /* 10 1011 RAW10 */
-#define ACQ_RAW12_DATA 44 /* 10 1100 RAW12 */
-#define ACQ_RAW14_DATA 45 /* 10 1101 RAW14 */
-#define ACQ_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
-#define ACQ_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
-#define ACQ_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
-#define ACQ_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
-#define ACQ_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
-#define ACQ_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
-#define ACQ_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
-#define ACQ_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
-#define ACQ_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
-#define ACQ_SOF_DATA 0 /* 00 0000 frame start */
-#define ACQ_EOF_DATA 1 /* 00 0001 frame end */
-#define ACQ_SOL_DATA 2 /* 00 0010 line start */
-#define ACQ_EOL_DATA 3 /* 00 0011 line end */
-#define ACQ_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
-#define ACQ_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
-#define ACQ_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
-#define ACQ_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
-#define ACQ_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
-#define ACQ_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
-#define ACQ_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
-#define ACQ_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
-#define ACQ_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
-#define ACQ_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
+#define ACQ_RGB555_DATA 33 /* 10 0001 RGB555 */
+#define ACQ_RGB565_DATA 34 /* 10 0010 RGB565 */
+#define ACQ_RGB666_DATA 35 /* 10 0011 RGB666 */
+#define ACQ_RGB888_DATA 36 /* 10 0100 RGB888 */
+#define ACQ_RAW6_DATA 40 /* 10 1000 RAW6 */
+#define ACQ_RAW7_DATA 41 /* 10 1001 RAW7 */
+#define ACQ_RAW8_DATA 42 /* 10 1010 RAW8 */
+#define ACQ_RAW10_DATA 43 /* 10 1011 RAW10 */
+#define ACQ_RAW12_DATA 44 /* 10 1100 RAW12 */
+#define ACQ_RAW14_DATA 45 /* 10 1101 RAW14 */
+#define ACQ_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
+#define ACQ_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
+#define ACQ_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
+#define ACQ_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
+#define ACQ_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
+#define ACQ_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
+#define ACQ_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
+#define ACQ_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
+#define ACQ_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
+#define ACQ_SOF_DATA 0 /* 00 0000 frame start */
+#define ACQ_EOF_DATA 1 /* 00 0001 frame end */
+#define ACQ_SOL_DATA 2 /* 00 0010 line start */
+#define ACQ_EOL_DATA 3 /* 00 0011 line end */
+#define ACQ_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
+#define ACQ_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
+#define ACQ_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
+#define ACQ_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
+#define ACQ_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
+#define ACQ_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
+#define ACQ_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
+#define ACQ_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
+#define ACQ_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
+#define ACQ_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
#define ACQ_RESERVED_DATA_TYPE_MIN 56
#define ACQ_RESERVED_DATA_TYPE_MAX 63
#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MIN 19
/* --------------------------------------------------*/
-#endif /* _isp_acquisition_defs_h */
+#endif /* _isp_acquisition_defs_h */
#define _isp_capture_defs_h
#define _ISP_CAPTURE_REG_ALIGN 4 /* assuming 32 bit control bus width */
-#define _ISP_CAPTURE_BITS_PER_ELEM 32 /* only for data, not SOP */
-#define _ISP_CAPTURE_BYTES_PER_ELEM (_ISP_CAPTURE_BITS_PER_ELEM/8 )
-#define _ISP_CAPTURE_BYTES_PER_WORD 32 /* 256/8 */
-#define _ISP_CAPTURE_ELEM_PER_WORD _ISP_CAPTURE_BYTES_PER_WORD / _ISP_CAPTURE_BYTES_PER_ELEM
+#define _ISP_CAPTURE_BITS_PER_ELEM 32 /* only for data, not SOP */
+#define _ISP_CAPTURE_BYTES_PER_ELEM (_ISP_CAPTURE_BITS_PER_ELEM / 8)
+#define _ISP_CAPTURE_BYTES_PER_WORD 32 /* 256/8 */
+#define _ISP_CAPTURE_ELEM_PER_WORD _ISP_CAPTURE_BYTES_PER_WORD / _ISP_CAPTURE_BYTES_PER_ELEM
//#define CAPT_RCV_ACK 1
-//#define CAPT_WRT_ACK 2
-//#define CAPT_IRQ_ACK 3
+//#define CAPT_WRT_ACK 2
+//#define CAPT_IRQ_ACK 3
/* --------------------------------------------------*/
// Register id's of MMIO slave accesible registers
#define CAPT_START_MODE_REG_ID 0
-#define CAPT_START_ADDR_REG_ID 1
-#define CAPT_MEM_REGION_SIZE_REG_ID 2
-#define CAPT_NUM_MEM_REGIONS_REG_ID 3
-#define CAPT_INIT_REG_ID 4
+#define CAPT_START_ADDR_REG_ID 1
+#define CAPT_MEM_REGION_SIZE_REG_ID 2
+#define CAPT_NUM_MEM_REGIONS_REG_ID 3
+#define CAPT_INIT_REG_ID 4
#define CAPT_START_REG_ID 5
-#define CAPT_STOP_REG_ID 6
+#define CAPT_STOP_REG_ID 6
#define CAPT_PACKET_LENGTH_REG_ID 7
-#define CAPT_RECEIVED_LENGTH_REG_ID 8
-#define CAPT_RECEIVED_SHORT_PACKETS_REG_ID 9
-#define CAPT_RECEIVED_LONG_PACKETS_REG_ID 10
-#define CAPT_LAST_COMMAND_REG_ID 11
+#define CAPT_RECEIVED_LENGTH_REG_ID 8
+#define CAPT_RECEIVED_SHORT_PACKETS_REG_ID 9
+#define CAPT_RECEIVED_LONG_PACKETS_REG_ID 10
+#define CAPT_LAST_COMMAND_REG_ID 11
#define CAPT_NEXT_COMMAND_REG_ID 12
#define CAPT_LAST_ACKNOWLEDGE_REG_ID 13
#define CAPT_NEXT_ACKNOWLEDGE_REG_ID 14
#define CAPT_FSM_STATE_INFO_REG_ID 15
// Register width
-#define CAPT_START_MODE_REG_WIDTH 1
+#define CAPT_START_MODE_REG_WIDTH 1
//#define CAPT_START_ADDR_REG_WIDTH 9
//#define CAPT_MEM_REGION_SIZE_REG_WIDTH 9
//#define CAPT_NUM_MEM_REGIONS_REG_WIDTH 9
#define CAPT_WRITE2MEM_FSM_STATE_BITS 2
#define CAPT_SYNCHRONIZER_FSM_STATE_BITS 3
-
#define CAPT_PACKET_LENGTH_REG_WIDTH 17
-#define CAPT_RECEIVED_LENGTH_REG_WIDTH 17
+#define CAPT_RECEIVED_LENGTH_REG_WIDTH 17
#define CAPT_RECEIVED_SHORT_PACKETS_REG_WIDTH 32
#define CAPT_RECEIVED_LONG_PACKETS_REG_WIDTH 32
#define CAPT_LAST_COMMAND_REG_WIDTH 32
-/* #define CAPT_NEXT_COMMAND_REG_WIDTH 32 */
+/* #define CAPT_NEXT_COMMAND_REG_WIDTH 32 */
#define CAPT_LAST_ACKNOWLEDGE_REG_WIDTH 32
#define CAPT_NEXT_ACKNOWLEDGE_REG_WIDTH 32
#define CAPT_FSM_STATE_INFO_REG_WIDTH ((CAPT_WRITE2MEM_FSM_STATE_BITS * 3) + (CAPT_SYNCHRONIZER_FSM_STATE_BITS * 3))
-//#define CAPT_INIT_RESTART_MEM_ADDR_WIDTH 9
-//#define CAPT_INIT_RESTART_MEM_REGION_WIDTH 9
+//#define CAPT_INIT_RESTART_MEM_ADDR_WIDTH 9
+//#define CAPT_INIT_RESTART_MEM_REGION_WIDTH 9
/* register reset value */
-#define CAPT_START_MODE_REG_RSTVAL 0
+#define CAPT_START_MODE_REG_RSTVAL 0
#define CAPT_START_ADDR_REG_RSTVAL 0
#define CAPT_MEM_REGION_SIZE_REG_RSTVAL 128
-#define CAPT_NUM_MEM_REGIONS_REG_RSTVAL 3
+#define CAPT_NUM_MEM_REGIONS_REG_RSTVAL 3
#define CAPT_INIT_REG_RSTVAL 0
#define CAPT_START_REG_RSTVAL 0
#define CAPT_INIT_RESTART_MEM_REGION_LSB 15
#define CAPT_INIT_RESTART_MEM_REGION_MSB 25
-
#define CAPT_INIT_RST_REG_IDX CAPT_INIT_RST_REG_BIT
#define CAPT_INIT_RST_REG_BITS 1
#define CAPT_INIT_FLUSH_IDX CAPT_INIT_FLUSH_BIT
#define CAPT_INIT_RESYNC_IDX CAPT_INIT_RESYNC_BIT
#define CAPT_INIT_RESYNC_BITS 1
#define CAPT_INIT_RESTART_IDX CAPT_INIT_RESTART_BIT
-#define CAPT_INIT_RESTART_BITS 1
+#define CAPT_INIT_RESTART_BITS 1
#define CAPT_INIT_RESTART_MEM_ADDR_IDX CAPT_INIT_RESTART_MEM_ADDR_LSB
#define CAPT_INIT_RESTART_MEM_ADDR_BITS (CAPT_INIT_RESTART_MEM_ADDR_MSB - CAPT_INIT_RESTART_MEM_ADDR_LSB + 1)
#define CAPT_INIT_RESTART_MEM_REGION_IDX CAPT_INIT_RESTART_MEM_REGION_LSB
#define CAPT_INIT_RESTART_MEM_REGION_BITS (CAPT_INIT_RESTART_MEM_REGION_MSB - CAPT_INIT_RESTART_MEM_REGION_LSB + 1)
-
-
/* --------------------------------------------------*/
/* TOKEN INFO */
/* --------------------------------------------------*/
#define CAPT_TOKEN_ID_LSB 0
-#define CAPT_TOKEN_ID_MSB 3
+#define CAPT_TOKEN_ID_MSB 3
#define CAPT_TOKEN_WIDTH (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1) /* 4 */
/* Command tokens IDs */
#define CAPT_START_TOKEN_ID 0 /* 0000b */
#define CAPT_STOP_TOKEN_ID 1 /* 0001b */
-#define CAPT_FREEZE_TOKEN_ID 2 /* 0010b */
+#define CAPT_FREEZE_TOKEN_ID 2 /* 0010b */
#define CAPT_RESUME_TOKEN_ID 3 /* 0011b */
#define CAPT_INIT_TOKEN_ID 8 /* 1000b */
-#define CAPT_START_TOKEN_BIT 0
+#define CAPT_START_TOKEN_BIT 0
#define CAPT_STOP_TOKEN_BIT 0
#define CAPT_FREEZE_TOKEN_BIT 0
#define CAPT_RESUME_TOKEN_BIT 0
#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB 20
#define CAPT_PACKET_CH_ID_TOKEN_MSB 27
#define CAPT_PACKET_CH_ID_TOKEN_LSB 26
-#define CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB 29
-#define CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB 21
+#define CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB 29
+#define CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB 21
/* bit definition */
#define CAPT_CMD_IDX CAPT_TOKEN_ID_LSB
#define CAPT_INIT_TOKEN_INIT_IDX 4
#define CAPT_INIT_TOKEN_INIT_BITS 22
-
/* --------------------------------------------------*/
/* MIPI */
/* --------------------------------------------------*/
-#define CAPT_WORD_COUNT_WIDTH 16
-#define CAPT_PKT_CODE_WIDTH 6
-#define CAPT_CHN_NO_WIDTH 2
-#define CAPT_ERROR_INFO_WIDTH 8
+#define CAPT_WORD_COUNT_WIDTH 16
+#define CAPT_PKT_CODE_WIDTH 6
+#define CAPT_CHN_NO_WIDTH 2
+#define CAPT_ERROR_INFO_WIDTH 8
#define LONG_PKTCODE_MAX 63
#define LONG_PKTCODE_MIN 16
#define SHORT_PKTCODE_MAX 15
-
/* --------------------------------------------------*/
/* Packet Info */
/* --------------------------------------------------*/
#define CAPT_LINE_PAYLOAD 4
#define CAPT_GEN_SH_PKT 5
-
/* --------------------------------------------------*/
/* Packet Data Type */
/* --------------------------------------------------*/
#define CAPT_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */
#define CAPT_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */
#define CAPT_RGB444_DATA 32 /* 10 0000 RGB444 */
-#define CAPT_RGB555_DATA 33 /* 10 0001 RGB555 */
-#define CAPT_RGB565_DATA 34 /* 10 0010 RGB565 */
-#define CAPT_RGB666_DATA 35 /* 10 0011 RGB666 */
-#define CAPT_RGB888_DATA 36 /* 10 0100 RGB888 */
-#define CAPT_RAW6_DATA 40 /* 10 1000 RAW6 */
-#define CAPT_RAW7_DATA 41 /* 10 1001 RAW7 */
-#define CAPT_RAW8_DATA 42 /* 10 1010 RAW8 */
-#define CAPT_RAW10_DATA 43 /* 10 1011 RAW10 */
-#define CAPT_RAW12_DATA 44 /* 10 1100 RAW12 */
-#define CAPT_RAW14_DATA 45 /* 10 1101 RAW14 */
-#define CAPT_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
-#define CAPT_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
-#define CAPT_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
-#define CAPT_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
-#define CAPT_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
-#define CAPT_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
-#define CAPT_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
-#define CAPT_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
-#define CAPT_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
-#define CAPT_SOF_DATA 0 /* 00 0000 frame start */
-#define CAPT_EOF_DATA 1 /* 00 0001 frame end */
-#define CAPT_SOL_DATA 2 /* 00 0010 line start */
-#define CAPT_EOL_DATA 3 /* 00 0011 line end */
-#define CAPT_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
-#define CAPT_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
-#define CAPT_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
-#define CAPT_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
-#define CAPT_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
-#define CAPT_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
-#define CAPT_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
-#define CAPT_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
-#define CAPT_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
-#define CAPT_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
+#define CAPT_RGB555_DATA 33 /* 10 0001 RGB555 */
+#define CAPT_RGB565_DATA 34 /* 10 0010 RGB565 */
+#define CAPT_RGB666_DATA 35 /* 10 0011 RGB666 */
+#define CAPT_RGB888_DATA 36 /* 10 0100 RGB888 */
+#define CAPT_RAW6_DATA 40 /* 10 1000 RAW6 */
+#define CAPT_RAW7_DATA 41 /* 10 1001 RAW7 */
+#define CAPT_RAW8_DATA 42 /* 10 1010 RAW8 */
+#define CAPT_RAW10_DATA 43 /* 10 1011 RAW10 */
+#define CAPT_RAW12_DATA 44 /* 10 1100 RAW12 */
+#define CAPT_RAW14_DATA 45 /* 10 1101 RAW14 */
+#define CAPT_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
+#define CAPT_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
+#define CAPT_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
+#define CAPT_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
+#define CAPT_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
+#define CAPT_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
+#define CAPT_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
+#define CAPT_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
+#define CAPT_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
+#define CAPT_SOF_DATA 0 /* 00 0000 frame start */
+#define CAPT_EOF_DATA 1 /* 00 0001 frame end */
+#define CAPT_SOL_DATA 2 /* 00 0010 line start */
+#define CAPT_EOL_DATA 3 /* 00 0011 line end */
+#define CAPT_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
+#define CAPT_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
+#define CAPT_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
+#define CAPT_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
+#define CAPT_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
+#define CAPT_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
+#define CAPT_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
+#define CAPT_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
+#define CAPT_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
+#define CAPT_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
#define CAPT_RESERVED_DATA_TYPE_MIN 56
#define CAPT_RESERVED_DATA_TYPE_MAX 63
#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MIN 19
#define CAPT_RAW_RESERVED_DATA_TYPE_MIN 46
#define CAPT_RAW_RESERVED_DATA_TYPE_MAX 47
-
/* --------------------------------------------------*/
/* Capture Unit State */
/* --------------------------------------------------*/
#define CAPT_FREEZE 5
#define CAPT_RUN 6
-
/* --------------------------------------------------*/
-#endif /* _isp_capture_defs_h */
-
-
-
-
-
+#endif /* _isp_capture_defs_h */
#define _HRT_TIMED_CONTROLLER_REG_ALIGN 4
-#endif /* _timed_controller_defs_h */
+#endif /* _timed_controller_defs_h */
#define hrt_host_type_of_ulong unsigned long
#define hrt_host_type_of_ptr void*
-#define HRT_TYPE_BYTES(cell, type) (HRT_TYPE_BITS(cell, type)/8)
+#define HRT_TYPE_BYTES(cell, type) (HRT_TYPE_BITS(cell, type) / 8)
#define HRT_HOST_TYPE(cell_type) HRTCAT(hrt_host_type_of_, cell_type)
#define HRT_INT_TYPE(type) HRTCAT(hrt_int_type_of_, type)
#ifdef C_RUN
#ifdef C_RUN_DYNAMIC_LINK_PROGRAMS
-extern void *csim_processor_get_crun_symbol(hive_proc_id p, const char *sym);
-#define _hrt_cell_get_crun_symbol(cell,sym) csim_processor_get_crun_symbol(cell,HRTSTR(sym))
-#define _hrt_cell_get_crun_indexed_symbol(cell,sym) csim_processor_get_crun_symbol(cell,HRTSTR(sym))
+void *csim_processor_get_crun_symbol(hive_proc_id p, const char *sym);
+#define _hrt_cell_get_crun_symbol(cell, sym) csim_processor_get_crun_symbol(cell, HRTSTR(sym))
+#define _hrt_cell_get_crun_indexed_symbol(cell, sym) csim_processor_get_crun_symbol(cell, HRTSTR(sym))
#else
-#define _hrt_cell_get_crun_symbol(cell,sym) (&sym)
-#define _hrt_cell_get_crun_indexed_symbol(cell,sym) (sym)
+#define _hrt_cell_get_crun_symbol(cell, sym) (&sym)
+#define _hrt_cell_get_crun_indexed_symbol(cell, sym) (sym)
#endif // C_RUN_DYNAMIC_LINK_PROGRAMS
#define hrt_scalar_store(cell, type, var, data) \
- ((*(HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_symbol(cell,var)) = (data))
+ ((*(HRT_HOST_TYPE(type) *)_hrt_cell_get_crun_symbol(cell, var)) = (data))
#define hrt_scalar_load(cell, type, var) \
- ((*(HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_symbol(cell,var)))
+ ((*(HRT_HOST_TYPE(type) *)_hrt_cell_get_crun_symbol(cell, var)))
#define hrt_indexed_store(cell, type, array, index, data) \
- ((((HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_indexed_symbol(cell,array))[index]) = (data))
+ ((((HRT_HOST_TYPE(type) *)_hrt_cell_get_crun_indexed_symbol(cell, array))[index]) = (data))
#define hrt_indexed_load(cell, type, array, index) \
- (((HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_indexed_symbol(cell,array))[index])
+ (((HRT_HOST_TYPE(type) *)_hrt_cell_get_crun_indexed_symbol(cell, array))[index])
#else /* C_RUN */
#define hrt_scalar_store(cell, type, var, data) \
- HRTCAT(hrt_mem_store_,HRT_TYPE_BITS(cell, type))(\
+ HRTCAT(hrt_mem_store_, HRT_TYPE_BITS(cell, type))(\
cell, \
- HRTCAT(HIVE_MEM_,var), \
- HRTCAT(HIVE_ADDR_,var), \
+ HRTCAT(HIVE_MEM_, var), \
+ HRTCAT(HIVE_ADDR_, var), \
(HRT_INT_TYPE(type))(data))
#define hrt_scalar_load(cell, type, var) \
- (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_,HRT_PROC_TYPE(cell),_,type) ( \
+ (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_, HRT_PROC_TYPE(cell), _, type) ( \
cell, \
- HRTCAT(HIVE_MEM_,var), \
- HRTCAT(HIVE_ADDR_,var)))
+ HRTCAT(HIVE_MEM_, var), \
+ HRTCAT(HIVE_ADDR_, var)))
#define hrt_indexed_store(cell, type, array, index, data) \
- HRTCAT(hrt_mem_store_,HRT_TYPE_BITS(cell, type))(\
+ HRTCAT(hrt_mem_store_, HRT_TYPE_BITS(cell, type))(\
cell, \
- HRTCAT(HIVE_MEM_,array), \
- (HRTCAT(HIVE_ADDR_,array))+((index)*HRT_TYPE_BYTES(cell, type)), \
+ HRTCAT(HIVE_MEM_, array), \
+ (HRTCAT(HIVE_ADDR_, array)) + ((index) * HRT_TYPE_BYTES(cell, type)), \
(HRT_INT_TYPE(type))(data))
#define hrt_indexed_load(cell, type, array, index) \
- (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_,HRT_PROC_TYPE(cell),_,type) ( \
- cell, \
- HRTCAT(HIVE_MEM_,array), \
- (HRTCAT(HIVE_ADDR_,array))+((index)*HRT_TYPE_BYTES(cell, type))))
+ (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_, HRT_PROC_TYPE(cell), _, type) ( \
+ cell, \
+ HRTCAT(HIVE_MEM_, array), \
+ (HRTCAT(HIVE_ADDR_, array)) + ((index) * HRT_TYPE_BYTES(cell, type))))
#endif /* C_RUN */
#ifndef _sp_map_h_
#define _sp_map_h_
-
#ifndef _hrt_dummy_use_blob_sp
#define _hrt_dummy_use_blob_sp()
#endif
/* one tracer item: major, minor and counter. The counter value can be used for GP data */
struct trace_item_t {
- uint8_t major;
- uint8_t minor;
- uint16_t counter;
+ u8 major;
+ u8 minor;
+ u16 counter;
};
#ifdef ISP2401
#else
/* 1st dword: descriptor */
#endif
- uint8_t version;
- uint8_t max_threads;
- uint16_t max_tracer_points;
+ u8 version;
+ u8 max_threads;
+ u16 max_tracer_points;
#ifdef ISP2401
/* 2nd field: command + data */
#endif
/* 2nd dword */
- uint32_t command;
+ u32 command;
/* 3rd & 4th dword */
#ifndef ISP2401
- uint32_t data[2];
+ u32 data[2];
#else
- uint32_t data[MAX_CMD_DATA];
+ u32 data[MAX_CMD_DATA];
/* 3rd field: debug pointer */
#endif
/* 5th & 6th dword: debug pointer mechanism */
- uint32_t debug_ptr_signature;
- uint32_t debug_ptr_value;
+ u32 debug_ptr_signature;
+ u32 debug_ptr_value;
#ifdef ISP2401
/* Rest of the header: status & scratch data */
- uint8_t thr_status_byte[SH_CSS_MAX_SP_THREADS];
- uint16_t thr_status_word[SH_CSS_MAX_SP_THREADS];
- uint32_t thr_status_dword[SH_CSS_MAX_SP_THREADS];
- uint32_t scratch_debug[MAX_SCRATCH_DATA];
+ u8 thr_status_byte[SH_CSS_MAX_SP_THREADS];
+ u16 thr_status_word[SH_CSS_MAX_SP_THREADS];
+ u32 thr_status_dword[SH_CSS_MAX_SP_THREADS];
+ u32 scratch_debug[MAX_SCRATCH_DATA];
#endif
};
};
#endif
-
/* currently divided as follows:*/
#if (TRACE_ENABLE_SP0 + TRACE_ENABLE_SP1 + TRACE_ENABLE_ISP == 3)
/* can be divided as needed */
-#define TRACE_SP0_SIZE (TRACE_BUFF_SIZE/4)
-#define TRACE_SP1_SIZE (TRACE_BUFF_SIZE/4)
-#define TRACE_ISP_SIZE (TRACE_BUFF_SIZE/2)
+#define TRACE_SP0_SIZE (TRACE_BUFF_SIZE / 4)
+#define TRACE_SP1_SIZE (TRACE_BUFF_SIZE / 4)
+#define TRACE_ISP_SIZE (TRACE_BUFF_SIZE / 2)
#elif (TRACE_ENABLE_SP0 + TRACE_ENABLE_SP1 + TRACE_ENABLE_ISP == 2)
#if TRACE_ENABLE_SP0
-#define TRACE_SP0_SIZE (TRACE_BUFF_SIZE/2)
+#define TRACE_SP0_SIZE (TRACE_BUFF_SIZE / 2)
#else
#define TRACE_SP0_SIZE (0)
#endif
#if TRACE_ENABLE_SP1
-#define TRACE_SP1_SIZE (TRACE_BUFF_SIZE/2)
+#define TRACE_SP1_SIZE (TRACE_BUFF_SIZE / 2)
#else
#define TRACE_SP1_SIZE (0)
#endif
#if TRACE_ENABLE_ISP
-#define TRACE_ISP_SIZE (TRACE_BUFF_SIZE/2)
+#define TRACE_ISP_SIZE (TRACE_BUFF_SIZE / 2)
#else
#define TRACE_ISP_SIZE (0)
#endif
/* shared macros in traces infrastructure */
/* increment the pointer cyclicly */
-#define DBG_NEXT_ITEM(x, max_items) (((x+1) >= max_items) ? 0 : x+1)
-#define DBG_PREV_ITEM(x, max_items) ((x) ? x-1 : max_items-1)
+#define DBG_NEXT_ITEM(x, max_items) (((x + 1) >= max_items) ? 0 : x + 1)
+#define DBG_PREV_ITEM(x, max_items) ((x) ? x - 1 : max_items - 1)
#define FIELD_MASK(width) (((1 << (width)) - 1))
-#define FIELD_PACK(value,mask,offset) (((value) & (mask)) << (offset))
-#define FIELD_UNPACK(value,mask,offset) (((value) >> (offset)) & (mask))
-
+#define FIELD_PACK(value, mask, offset) (((value) & (mask)) << (offset))
+#define FIELD_UNPACK(value, mask, offset) (((value) >> (offset)) & (mask))
#define FIELD_VALUE_OFFSET (0)
#define FIELD_VALUE_WIDTH (16)
#define FIELD_VALUE_MASK FIELD_MASK(FIELD_VALUE_WIDTH)
-#define FIELD_VALUE_PACK(f) FIELD_PACK(f,FIELD_VALUE_MASK,FIELD_VALUE_OFFSET)
+#define FIELD_VALUE_PACK(f) FIELD_PACK(f, FIELD_VALUE_MASK, FIELD_VALUE_OFFSET)
#ifndef ISP2401
-#define FIELD_VALUE_UNPACK(f) FIELD_UNPACK(f,FIELD_VALUE_MASK,FIELD_VALUE_OFFSET)
+#define FIELD_VALUE_UNPACK(f) FIELD_UNPACK(f, FIELD_VALUE_MASK, FIELD_VALUE_OFFSET)
#else
-#define FIELD_VALUE_UNPACK(f) FIELD_UNPACK(f,FIELD_VALUE_MASK,FIELD_VALUE_OFFSET)
+#define FIELD_VALUE_UNPACK(f) FIELD_UNPACK(f, FIELD_VALUE_MASK, FIELD_VALUE_OFFSET)
#endif
#define FIELD_MINOR_OFFSET (FIELD_VALUE_OFFSET + FIELD_VALUE_WIDTH)
#define FIELD_MINOR_WIDTH (8)
#define FIELD_MINOR_MASK FIELD_MASK(FIELD_MINOR_WIDTH)
-#define FIELD_MINOR_PACK(f) FIELD_PACK(f,FIELD_MINOR_MASK,FIELD_MINOR_OFFSET)
+#define FIELD_MINOR_PACK(f) FIELD_PACK(f, FIELD_MINOR_MASK, FIELD_MINOR_OFFSET)
#ifndef ISP2401
-#define FIELD_MINOR_UNPACK(f) FIELD_UNPACK(f,FIELD_MINOR_MASK,FIELD_MINOR_OFFSET)
+#define FIELD_MINOR_UNPACK(f) FIELD_UNPACK(f, FIELD_MINOR_MASK, FIELD_MINOR_OFFSET)
#else
-#define FIELD_MINOR_UNPACK(f) FIELD_UNPACK(f,FIELD_MINOR_MASK,FIELD_MINOR_OFFSET)
+#define FIELD_MINOR_UNPACK(f) FIELD_UNPACK(f, FIELD_MINOR_MASK, FIELD_MINOR_OFFSET)
#endif
#define FIELD_MAJOR_OFFSET (FIELD_MINOR_OFFSET + FIELD_MINOR_WIDTH)
#define FIELD_MAJOR_WIDTH (5)
#define FIELD_MAJOR_MASK FIELD_MASK(FIELD_MAJOR_WIDTH)
-#define FIELD_MAJOR_PACK(f) FIELD_PACK(f,FIELD_MAJOR_MASK,FIELD_MAJOR_OFFSET)
+#define FIELD_MAJOR_PACK(f) FIELD_PACK(f, FIELD_MAJOR_MASK, FIELD_MAJOR_OFFSET)
#ifndef ISP2401
-#define FIELD_MAJOR_UNPACK(f) FIELD_UNPACK(f,FIELD_MAJOR_MASK,FIELD_MAJOR_OFFSET)
+#define FIELD_MAJOR_UNPACK(f) FIELD_UNPACK(f, FIELD_MAJOR_MASK, FIELD_MAJOR_OFFSET)
#else
-#define FIELD_MAJOR_UNPACK(f) FIELD_UNPACK(f,FIELD_MAJOR_MASK,FIELD_MAJOR_OFFSET)
+#define FIELD_MAJOR_UNPACK(f) FIELD_UNPACK(f, FIELD_MAJOR_MASK, FIELD_MAJOR_OFFSET)
#endif
#ifndef ISP2401
#define FIELD_FORMAT_OFFSET (FIELD_MAJOR_OFFSET + FIELD_MAJOR_WIDTH)
-#define FIELD_FORMAT_WIDTH (3)
-#define FIELD_FORMAT_MASK FIELD_MASK(FIELD_FORMAT_WIDTH)
-#define FIELD_FORMAT_PACK(f) FIELD_PACK(f,FIELD_FORMAT_MASK,FIELD_FORMAT_OFFSET)
-#define FIELD_FORMAT_UNPACK(f) FIELD_UNPACK(f,FIELD_FORMAT_MASK,FIELD_FORMAT_OFFSET)
+#define FIELD_FORMAT_WIDTH (3)
+#define FIELD_FORMAT_MASK FIELD_MASK(FIELD_FORMAT_WIDTH)
+#define FIELD_FORMAT_PACK(f) FIELD_PACK(f, FIELD_FORMAT_MASK, FIELD_FORMAT_OFFSET)
+#define FIELD_FORMAT_UNPACK(f) FIELD_UNPACK(f, FIELD_FORMAT_MASK, FIELD_FORMAT_OFFSET)
#else
/* for quick traces - only insertion, compatible with the regular point */
#define FIELD_FULL_MAJOR_WIDTH (8)
#define FIELD_FULL_MAJOR_MASK FIELD_MASK(FIELD_FULL_MAJOR_WIDTH)
-#define FIELD_FULL_MAJOR_PACK(f) FIELD_PACK(f,FIELD_FULL_MAJOR_MASK,FIELD_MAJOR_OFFSET)
+#define FIELD_FULL_MAJOR_PACK(f) FIELD_PACK(f, FIELD_FULL_MAJOR_MASK, FIELD_MAJOR_OFFSET)
/* The following 2 fields are used only when FIELD_TID value is 111b.
* it means we don't want to use thread id, but format. In this case,
#define FIELD_MAJOR_W_FMT_OFFSET FIELD_MAJOR_OFFSET
#define FIELD_MAJOR_W_FMT_WIDTH (3)
#define FIELD_MAJOR_W_FMT_MASK FIELD_MASK(FIELD_MAJOR_W_FMT_WIDTH)
-#define FIELD_MAJOR_W_FMT_PACK(f) FIELD_PACK(f,FIELD_MAJOR_W_FMT_MASK,FIELD_MAJOR_W_FMT_OFFSET)
-#define FIELD_MAJOR_W_FMT_UNPACK(f) FIELD_UNPACK(f,FIELD_MAJOR_W_FMT_MASK,FIELD_MAJOR_W_FMT_OFFSET)
+#define FIELD_MAJOR_W_FMT_PACK(f) FIELD_PACK(f, FIELD_MAJOR_W_FMT_MASK, FIELD_MAJOR_W_FMT_OFFSET)
+#define FIELD_MAJOR_W_FMT_UNPACK(f) FIELD_UNPACK(f, FIELD_MAJOR_W_FMT_MASK, FIELD_MAJOR_W_FMT_OFFSET)
#define FIELD_FORMAT_OFFSET (FIELD_MAJOR_OFFSET + FIELD_MAJOR_W_FMT_WIDTH)
-#define FIELD_FORMAT_WIDTH (2)
-#define FIELD_FORMAT_MASK FIELD_MASK(FIELD_MAJOR_W_FMT_WIDTH)
-#define FIELD_FORMAT_PACK(f) FIELD_PACK(f,FIELD_FORMAT_MASK,FIELD_FORMAT_OFFSET)
-#define FIELD_FORMAT_UNPACK(f) FIELD_UNPACK(f,FIELD_FORMAT_MASK,FIELD_FORMAT_OFFSET)
+#define FIELD_FORMAT_WIDTH (2)
+#define FIELD_FORMAT_MASK FIELD_MASK(FIELD_MAJOR_W_FMT_WIDTH)
+#define FIELD_FORMAT_PACK(f) FIELD_PACK(f, FIELD_FORMAT_MASK, FIELD_FORMAT_OFFSET)
+#define FIELD_FORMAT_UNPACK(f) FIELD_UNPACK(f, FIELD_FORMAT_MASK, FIELD_FORMAT_OFFSET)
#define FIELD_TID_SEL_FORMAT_PAT (7)
#define FIELD_TID_OFFSET (FIELD_MAJOR_OFFSET + FIELD_MAJOR_WIDTH)
#define FIELD_TID_WIDTH (3)
#define FIELD_TID_MASK FIELD_MASK(FIELD_TID_WIDTH)
-#define FIELD_TID_PACK(f) FIELD_PACK(f,FIELD_TID_MASK,FIELD_TID_OFFSET)
-#define FIELD_TID_UNPACK(f) FIELD_UNPACK(f,FIELD_TID_MASK,FIELD_TID_OFFSET)
+#define FIELD_TID_PACK(f) FIELD_PACK(f, FIELD_TID_MASK, FIELD_TID_OFFSET)
+#define FIELD_TID_UNPACK(f) FIELD_UNPACK(f, FIELD_TID_MASK, FIELD_TID_OFFSET)
#endif
#define FIELD_VALUE_24_OFFSET (0)
#else
#define FIELD_VALUE_24_MASK FIELD_MASK(FIELD_VALUE_24_WIDTH)
#endif
-#define FIELD_VALUE_24_PACK(f) FIELD_PACK(f,FIELD_VALUE_24_MASK,FIELD_VALUE_24_OFFSET)
-#define FIELD_VALUE_24_UNPACK(f) FIELD_UNPACK(f,FIELD_VALUE_24_MASK,FIELD_VALUE_24_OFFSET)
+#define FIELD_VALUE_24_PACK(f) FIELD_PACK(f, FIELD_VALUE_24_MASK, FIELD_VALUE_24_OFFSET)
+#define FIELD_VALUE_24_UNPACK(f) FIELD_UNPACK(f, FIELD_VALUE_24_MASK, FIELD_VALUE_24_OFFSET)
#ifndef ISP2401
-#define PACK_TRACEPOINT(format,major, minor, value) \
+#define PACK_TRACEPOINT(format, major, minor, value) \
(FIELD_FORMAT_PACK(format) | FIELD_MAJOR_PACK(major) | FIELD_MINOR_PACK(minor) | FIELD_VALUE_PACK(value))
#else
#define PACK_TRACEPOINT(tid, major, minor, value) \
* #define HAS_WATCHDOG_SP_THREAD_DEBUG
*/
-
/*
* The linear buffer mode will accept data until the first
* overflow and then stop accepting new data
} debug_buf_mode_t;
struct debug_data_s {
- uint32_t enable;
- uint32_t bufmode;
- uint32_t head;
- uint32_t tail;
- uint32_t buf[DEBUG_BUF_SIZE];
+ u32 enable;
+ u32 bufmode;
+ u32 head;
+ u32 tail;
+ u32 buf[DEBUG_BUF_SIZE];
};
/* thread.sp.c doesn't have a notion of HIVE_ISP_DDR_WORD_BYTES
#ifdef HIVE_ISP_DDR_WORD_BYTES
struct debug_data_ddr_s {
- uint32_t enable;
- int8_t padding1[HIVE_ISP_DDR_WORD_BYTES-sizeof(uint32_t)];
- uint32_t bufmode;
- int8_t padding2[HIVE_ISP_DDR_WORD_BYTES-sizeof(uint32_t)];
- uint32_t head;
- int8_t padding3[HIVE_ISP_DDR_WORD_BYTES-sizeof(uint32_t)];
- uint32_t tail;
- int8_t padding4[HIVE_ISP_DDR_WORD_BYTES-sizeof(uint32_t)];
- uint32_t buf[DEBUG_BUF_SIZE];
+ u32 enable;
+ s8 padding1[HIVE_ISP_DDR_WORD_BYTES - sizeof(uint32_t)];
+ u32 bufmode;
+ s8 padding2[HIVE_ISP_DDR_WORD_BYTES - sizeof(uint32_t)];
+ u32 head;
+ s8 padding3[HIVE_ISP_DDR_WORD_BYTES - sizeof(uint32_t)];
+ u32 tail;
+ s8 padding4[HIVE_ISP_DDR_WORD_BYTES - sizeof(uint32_t)];
+ u32 buf[DEBUG_BUF_SIZE];
};
#endif
#endif /* __DEBUG_GLOBAL_H_INCLUDED__ */
-
#define _DMA_ZERO_EXTEND _DMA_V2_ZERO_EXTEND
#define _DMA_SIGN_EXTEND _DMA_V2_SIGN_EXTEND
-
typedef unsigned int dma_channel;
typedef enum {
dma_sign_extension = _DMA_SIGN_EXTEND
} dma_extension;
-
#define DMA_PROP_SHIFT(val, param) ((val) << _DMA_V2_ ## param ## _IDX)
-#define DMA_PROP_MASK(param) ((1U << _DMA_V2_ ## param ## _BITS)-1)
+#define DMA_PROP_MASK(param) ((1U << _DMA_V2_ ## param ## _BITS) - 1)
#define DMA_PACK(val, param) DMA_PROP_SHIFT((val) & DMA_PROP_MASK(param), param)
#define DMA_PACK_COMMAND(cmd) DMA_PACK(cmd, CMD)
#define hive_dma_move_data(dma_id, read, channel, addr_a, addr_b, to_is_var, from_is_var) \
{ \
hive_dma_snd(dma_id, DMA_PACK(_DMA_V2_SET_CRUN_COMMAND, CMD)); \
- hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(read?_DMA_V2_MOVE_B2A_COMMAND:_DMA_V2_MOVE_A2B_COMMAND, channel)); \
- hive_dma_snd(dma_id, read?(unsigned)(addr_b):(unsigned)(addr_a)); \
- hive_dma_snd(dma_id, read?(unsigned)(addr_a):(unsigned)(addr_b)); \
+ hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(read ? _DMA_V2_MOVE_B2A_COMMAND : _DMA_V2_MOVE_A2B_COMMAND, channel)); \
+ hive_dma_snd(dma_id, read ? (unsigned int)(addr_b) : (unsigned int)(addr_a)); \
+ hive_dma_snd(dma_id, read ? (unsigned int)(addr_a) : (unsigned int)(addr_b)); \
hive_dma_snd(dma_id, to_is_var); \
hive_dma_snd(dma_id, from_is_var); \
}
+
#define hive_dma_move_data_no_ack(dma_id, read, channel, addr_a, addr_b, to_is_var, from_is_var) \
{ \
hive_dma_snd(dma_id, DMA_PACK(_DMA_V2_SET_CRUN_COMMAND, CMD)); \
- hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(read?_DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND:_DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND, channel)); \
- hive_dma_snd(dma_id, read?(unsigned)(addr_b):(unsigned)(addr_a)); \
- hive_dma_snd(dma_id, read?(unsigned)(addr_a):(unsigned)(addr_b)); \
+ hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(read ? _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND : _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND, channel)); \
+ hive_dma_snd(dma_id, read ? (unsigned int)(addr_b) : (unsigned int)(addr_a)); \
+ hive_dma_snd(dma_id, read ? (unsigned int)(addr_a) : (unsigned int)(addr_b)); \
hive_dma_snd(dma_id, to_is_var); \
hive_dma_snd(dma_id, from_is_var); \
}
} dma_config_type_t;
struct dma_port_config {
- uint8_t crop, elems;
- uint16_t width;
- uint32_t stride;
+ u8 crop, elems;
+ u16 width;
+ u32 stride;
};
/* Descriptor for dma configuration */
struct dma_channel_config {
- uint8_t connection;
- uint8_t extension;
- uint8_t height;
+ u8 connection;
+ u8 extension;
+ u8 height;
struct dma_port_config a, b;
};
/* The GDC is capable of higher internal precision than the parameter data structures */
#define HRT_GDC_COORD_SCALE_BITS 6
-#define HRT_GDC_COORD_SCALE (1 << HRT_GDC_COORD_SCALE_BITS)
+#define HRT_GDC_COORD_SCALE BIT(HRT_GDC_COORD_SCALE_BITS)
typedef enum {
GDC_CH0_ID = 0,
} gdc_bits_per_pixel_t;
typedef struct gdc_scale_param_mem_s {
- uint16_t params[N_GDC_PARAM];
- uint16_t ipx_start_array[N_GDC_PARAM];
- uint16_t ibuf_offset[N_GDC_PARAM];
- uint16_t obuf_offset[N_GDC_PARAM];
+ u16 params[N_GDC_PARAM];
+ u16 ipx_start_array[N_GDC_PARAM];
+ u16 ibuf_offset[N_GDC_PARAM];
+ u16 obuf_offset[N_GDC_PARAM];
} gdc_scale_param_mem_t;
typedef struct gdc_warp_param_mem_s {
- uint32_t origin_x;
- uint32_t origin_y;
- uint32_t in_addr_offset;
- uint32_t in_block_width;
- uint32_t in_block_height;
- uint32_t p0_x;
- uint32_t p0_y;
- uint32_t p1_x;
- uint32_t p1_y;
- uint32_t p2_x;
- uint32_t p2_y;
- uint32_t p3_x;
- uint32_t p3_y;
- uint32_t padding[3];
+ u32 origin_x;
+ u32 origin_y;
+ u32 in_addr_offset;
+ u32 in_block_width;
+ u32 in_block_height;
+ u32 p0_x;
+ u32 p0_y;
+ u32 p1_x;
+ u32 p1_y;
+ u32 p2_x;
+ u32 p2_y;
+ u32 p3_x;
+ u32 p3_y;
+ u32 padding[3];
} gdc_warp_param_mem_t;
-
#endif /* __GDC_GLOBAL_H_INCLUDED__ */
#define _REG_GP_SYNCGEN_FRAME_CNT_ADDR 0x00090090
#define _REG_GP_SOFT_RESET_ADDR 0x00090094
-
#endif /* __GP_DEVICE_GLOBAL_H_INCLUDED__ */
*/
#define ISP_HIST_ALIGNMENT_LOG2 2
-#define HMEM_SIZE_LOG2 (ISP_HIST_ADDRESS_BITS-ISP_HIST_ALIGNMENT_LOG2)
+#define HMEM_SIZE_LOG2 (ISP_HIST_ADDRESS_BITS - ISP_HIST_ALIGNMENT_LOG2)
#define HMEM_SIZE ISP_HIST_DEPTH
-#define HMEM_UNIT_SIZE (HMEM_SIZE/ISP_HIST_COMPONENTS)
+#define HMEM_UNIT_SIZE (HMEM_SIZE / ISP_HIST_COMPONENTS)
#define HMEM_UNIT_COUNT ISP_HIST_COMPONENTS
#define HMEM_RANGE_LOG2 ISP_HIST_WIDTH
-#define HMEM_RANGE (1UL<<HMEM_RANGE_LOG2)
+#define HMEM_RANGE BIT(HMEM_RANGE_LOG2)
-typedef uint32_t hmem_data_t;
+typedef u32 hmem_data_t;
#endif /* __HMEM_GLOBAL_H_INCLUDED__ */
#include "assert_support.h"
/* The address of the remote copy */
-hrt_address debug_buffer_address = (hrt_address)-1;
+hrt_address debug_buffer_address = (hrt_address) - 1;
hrt_vaddress debug_buffer_ddr_address = (hrt_vaddress)-1;
/* The local copy */
static debug_data_t debug_data;
void debug_buffer_ddr_init(const hrt_vaddress addr)
{
debug_buf_mode_t mode = DEBUG_BUFFER_MODE_LINEAR;
- uint32_t enable = 1;
- uint32_t head = 0;
- uint32_t tail = 0;
+ u32 enable = 1;
+ u32 head = 0;
+ u32 tail = 0;
/* set the ddr queue */
debug_buffer_ddr_address = addr;
mmgr_store(addr + DEBUG_DATA_BUF_MODE_DDR_ADDR,
sp_dmem_store_uint32(SP0_ID,
debug_buffer_address + DEBUG_DATA_BUF_MODE_ADDR, mode);
}
-
#include "debug_global.h"
#endif /* __DEBUG_LOCAL_H_INCLUDED__ */
-
{
hrt_data value = 0;
- assert(debug_buffer_address != ((hrt_address)-1));
+ assert(debug_buffer_address != ((hrt_address) - 1));
debug_synch_queue();
STORAGE_CLASS_DEBUG_C void debug_synch_queue(void)
{
- uint32_t remote_tail = sp_dmem_load_uint32(SP0_ID, debug_buffer_address + DEBUG_DATA_TAIL_ADDR);
+ u32 remote_tail = sp_dmem_load_uint32(SP0_ID, debug_buffer_address + DEBUG_DATA_TAIL_ADDR);
/* We could move the remote head after the upload, but we would have to limit the upload w.r.t. the local head. This is easier */
if (remote_tail > debug_data_ptr->tail) {
size_t delta = remote_tail - debug_data_ptr->tail;
- sp_dmem_load(SP0_ID, debug_buffer_address + DEBUG_DATA_BUF_ADDR + debug_data_ptr->tail*sizeof(uint32_t), (void *)&(debug_data_ptr->buf[debug_data_ptr->tail]), delta*sizeof(uint32_t));
+
+ sp_dmem_load(SP0_ID, debug_buffer_address + DEBUG_DATA_BUF_ADDR + debug_data_ptr->tail * sizeof(uint32_t), (void *)&debug_data_ptr->buf[debug_data_ptr->tail], delta * sizeof(uint32_t));
} else if (remote_tail < debug_data_ptr->tail) {
size_t delta = DEBUG_BUF_SIZE - debug_data_ptr->tail;
- sp_dmem_load(SP0_ID, debug_buffer_address + DEBUG_DATA_BUF_ADDR + debug_data_ptr->tail*sizeof(uint32_t), (void *)&(debug_data_ptr->buf[debug_data_ptr->tail]), delta*sizeof(uint32_t));
- sp_dmem_load(SP0_ID, debug_buffer_address + DEBUG_DATA_BUF_ADDR, (void *)&(debug_data_ptr->buf[0]), remote_tail*sizeof(uint32_t));
+
+ sp_dmem_load(SP0_ID, debug_buffer_address + DEBUG_DATA_BUF_ADDR + debug_data_ptr->tail * sizeof(uint32_t), (void *)&debug_data_ptr->buf[debug_data_ptr->tail], delta * sizeof(uint32_t));
+ sp_dmem_load(SP0_ID, debug_buffer_address + DEBUG_DATA_BUF_ADDR, (void *)&debug_data_ptr->buf[0], remote_tail * sizeof(uint32_t));
} /* else we are up to date */
debug_data_ptr->tail = remote_tail;
}
STORAGE_CLASS_DEBUG_C void debug_synch_queue_isp(void)
{
- uint32_t remote_tail = isp_dmem_load_uint32(ISP0_ID, DEBUG_BUFFER_ISP_DMEM_ADDR + DEBUG_DATA_TAIL_ADDR);
+ u32 remote_tail = isp_dmem_load_uint32(ISP0_ID, DEBUG_BUFFER_ISP_DMEM_ADDR + DEBUG_DATA_TAIL_ADDR);
/* We could move the remote head after the upload, but we would have to limit the upload w.r.t. the local head. This is easier */
if (remote_tail > debug_data_ptr->tail) {
size_t delta = remote_tail - debug_data_ptr->tail;
- isp_dmem_load(ISP0_ID, DEBUG_BUFFER_ISP_DMEM_ADDR + DEBUG_DATA_BUF_ADDR + debug_data_ptr->tail*sizeof(uint32_t), (void *)&(debug_data_ptr->buf[debug_data_ptr->tail]), delta*sizeof(uint32_t));
+
+ isp_dmem_load(ISP0_ID, DEBUG_BUFFER_ISP_DMEM_ADDR + DEBUG_DATA_BUF_ADDR + debug_data_ptr->tail * sizeof(uint32_t), (void *)&debug_data_ptr->buf[debug_data_ptr->tail], delta * sizeof(uint32_t));
} else if (remote_tail < debug_data_ptr->tail) {
size_t delta = DEBUG_BUF_SIZE - debug_data_ptr->tail;
- isp_dmem_load(ISP0_ID, DEBUG_BUFFER_ISP_DMEM_ADDR + DEBUG_DATA_BUF_ADDR + debug_data_ptr->tail*sizeof(uint32_t), (void *)&(debug_data_ptr->buf[debug_data_ptr->tail]), delta*sizeof(uint32_t));
- isp_dmem_load(ISP0_ID, DEBUG_BUFFER_ISP_DMEM_ADDR + DEBUG_DATA_BUF_ADDR, (void *)&(debug_data_ptr->buf[0]), remote_tail*sizeof(uint32_t));
+
+ isp_dmem_load(ISP0_ID, DEBUG_BUFFER_ISP_DMEM_ADDR + DEBUG_DATA_BUF_ADDR + debug_data_ptr->tail * sizeof(uint32_t), (void *)&debug_data_ptr->buf[debug_data_ptr->tail], delta * sizeof(uint32_t));
+ isp_dmem_load(ISP0_ID, DEBUG_BUFFER_ISP_DMEM_ADDR + DEBUG_DATA_BUF_ADDR, (void *)&debug_data_ptr->buf[0], remote_tail * sizeof(uint32_t));
} /* else we are up to date */
debug_data_ptr->tail = remote_tail;
}
STORAGE_CLASS_DEBUG_C void debug_synch_queue_ddr(void)
{
- uint32_t remote_tail;
+ u32 remote_tail;
mmgr_load(debug_buffer_ddr_address + DEBUG_DATA_TAIL_DDR_ADDR, &remote_tail, sizeof(uint32_t));
/* We could move the remote head after the upload, but we would have to limit the upload w.r.t. the local head. This is easier */
if (remote_tail > debug_data_ptr->tail) {
size_t delta = remote_tail - debug_data_ptr->tail;
- mmgr_load(debug_buffer_ddr_address + DEBUG_DATA_BUF_DDR_ADDR + debug_data_ptr->tail*sizeof(uint32_t), (void *)&(debug_data_ptr->buf[debug_data_ptr->tail]), delta*sizeof(uint32_t));
+
+ mmgr_load(debug_buffer_ddr_address + DEBUG_DATA_BUF_DDR_ADDR + debug_data_ptr->tail * sizeof(uint32_t), (void *)&debug_data_ptr->buf[debug_data_ptr->tail], delta * sizeof(uint32_t));
} else if (remote_tail < debug_data_ptr->tail) {
size_t delta = DEBUG_BUF_SIZE - debug_data_ptr->tail;
- mmgr_load(debug_buffer_ddr_address + DEBUG_DATA_BUF_DDR_ADDR + debug_data_ptr->tail*sizeof(uint32_t), (void *)&(debug_data_ptr->buf[debug_data_ptr->tail]), delta*sizeof(uint32_t));
- mmgr_load(debug_buffer_ddr_address + DEBUG_DATA_BUF_DDR_ADDR, (void *)&(debug_data_ptr->buf[0]), remote_tail*sizeof(uint32_t));
+
+ mmgr_load(debug_buffer_ddr_address + DEBUG_DATA_BUF_DDR_ADDR + debug_data_ptr->tail * sizeof(uint32_t), (void *)&debug_data_ptr->buf[debug_data_ptr->tail], delta * sizeof(uint32_t));
+ mmgr_load(debug_buffer_ddr_address + DEBUG_DATA_BUF_DDR_ADDR, (void *)&debug_data_ptr->buf[0], remote_tail * sizeof(uint32_t));
} /* else we are up to date */
debug_data_ptr->tail = remote_tail;
}
#endif /* __DEBUG_PRIVATE_H_INCLUDED__ */
-
hrt_data tmp;
assert(ID < N_DMA_ID);
- assert(state != NULL);
+ assert(state);
tmp = dma_reg_load(ID, DMA_COMMAND_FSM_REG_IDX);
//reg [3:0] : flags error [3], stall, run, idle [0]
state->fsm_command_run = tmp & 0x2;
state->fsm_command_stalling = tmp & 0x4;
state->fsm_command_error = tmp & 0x8;
- state->last_command_channel = (tmp>>10 & 0x1F);
- state->last_command_param = (tmp>>15 & 0x0F);
- tmp = (tmp>>4) & 0x3F;
+ state->last_command_channel = (tmp >> 10 & 0x1F);
+ state->last_command_param = (tmp >> 15 & 0x0F);
+ tmp = (tmp >> 4) & 0x3F;
/* state->last_command = (dma_commands_t)tmp; */
/* if the enumerator is made non-linear */
/* AM: the list below does not cover all the cases*/
_DMA_FSM_GROUP_FSM_WR_IDX));
for (i = 0; i < HIVE_ISP_NUM_DMA_CONNS; i++) {
- dma_port_state_t *port = &(state->port_states[i]);
+ dma_port_state_t *port = &state->port_states[i];
tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(0, i));
port->req_cs = ((tmp & 0x1) != 0);
}
for (i = 0; i < HIVE_DMA_NUM_CHANNELS; i++) {
- dma_channel_state_t *ch = &(state->channel_states[i]);
+ dma_channel_state_t *ch = &state->channel_states[i];
ch->connection = DMA_GET_CONNECTION(dma_reg_load(ID,
DMA_CHANNEL_PARAM_REG_IDX(i,
int fsm_ctrl_pack_extension;
int pack_idle;
int pack_run;
- int pack_stalling;
+ int pack_stalling;
int pack_error;
int pack_cnt_height;
int pack_src_cnt_width;
const hrt_data value)
{
assert(ID < N_DMA_ID);
- assert(DMA_BASE[ID] != (hrt_address)-1);
- ia_css_device_store_uint32(DMA_BASE[ID] + reg*sizeof(hrt_data), value);
+ assert(DMA_BASE[ID] != (hrt_address) - 1);
+ ia_css_device_store_uint32(DMA_BASE[ID] + reg * sizeof(hrt_data), value);
}
STORAGE_CLASS_DMA_C hrt_data dma_reg_load(const dma_ID_t ID,
const unsigned int reg)
{
assert(ID < N_DMA_ID);
- assert(DMA_BASE[ID] != (hrt_address)-1);
- return ia_css_device_load_uint32(DMA_BASE[ID] + reg*sizeof(hrt_data));
+ assert(DMA_BASE[ID] != (hrt_address) - 1);
+ return ia_css_device_load_uint32(DMA_BASE[ID] + reg * sizeof(hrt_data));
}
#endif /* __DMA_PRIVATE_H_INCLUDED__ */
STORAGE_CLASS_EVENT_C void event_wait_for(const event_ID_t ID)
{
assert(ID < N_EVENT_ID);
- assert(event_source_addr[ID] != ((hrt_address)-1));
+ assert(event_source_addr[ID] != ((hrt_address) - 1));
(void)ia_css_device_load_uint32(event_source_addr[ID]);
return;
}
STORAGE_CLASS_EVENT_C hrt_data event_receive_token(const event_ID_t ID)
{
assert(ID < N_EVENT_ID);
- assert(event_source_addr[ID] != ((hrt_address)-1));
+ assert(event_source_addr[ID] != ((hrt_address) - 1));
return ia_css_device_load_uint32(event_source_addr[ID]);
}
const hrt_data token)
{
assert(ID < N_EVENT_ID);
- assert(event_sink_addr[ID] != ((hrt_address)-1));
+ assert(event_sink_addr[ID] != ((hrt_address) - 1));
ia_css_device_store_uint32(event_sink_addr[ID], token);
}
STORAGE_CLASS_EVENT_C bool is_event_pending(const event_ID_t ID)
{
hrt_data value;
+
assert(ID < N_EVENT_ID);
- assert(event_source_query_addr[ID] != ((hrt_address)-1));
+ assert(event_source_query_addr[ID] != ((hrt_address) - 1));
value = ia_css_device_load_uint32(event_source_query_addr[ID]);
return !_hrt_get_bit(value, EVENT_QUERY_BIT);
}
STORAGE_CLASS_EVENT_C bool can_event_send_token(const event_ID_t ID)
{
hrt_data value;
+
assert(ID < N_EVENT_ID);
- assert(event_sink_query_addr[ID] != ((hrt_address)-1));
+ assert(event_sink_query_addr[ID] != ((hrt_address) - 1));
value = ia_css_device_load_uint32(event_sink_query_addr[ID]);
return !_hrt_get_bit(value, EVENT_QUERY_BIT);
}
#include "fifo_monitor_private.h"
#endif /* __INLINE_FIFO_MONITOR__ */
-static inline bool fifo_monitor_status_valid (
+static inline bool fifo_monitor_status_valid(
const fifo_monitor_ID_t ID,
const unsigned int reg,
const unsigned int port_id);
const unsigned int reg,
const unsigned int port_id);
-
void fifo_channel_get_state(
const fifo_monitor_ID_t ID,
const fifo_channel_t channel_id,
fifo_channel_state_t *state)
{
assert(channel_id < N_FIFO_CHANNEL);
- assert(state != NULL);
+ assert(state);
switch (channel_id) {
case FIFO_CHANNEL_ISP0_TO_SP0:
ISP_STR_MON_PORT_SND_GPD);
{
hrt_data value = ia_css_device_load_uint32(0x0000000000380014ULL);
+
state->fifo_valid = !_hrt_get_bit(value, 0);
state->sink_accept = false; /* no monitor connected */
}
case FIFO_CHANNEL_HOST0_TO_ISP0:
{
hrt_data value = ia_css_device_load_uint32(0x000000000038001CULL);
+
state->fifo_valid = false; /* no monitor connected */
state->sink_accept = !_hrt_get_bit(value, 0);
}
SP_STR_MON_PORT_SND_GPD);
{
hrt_data value = ia_css_device_load_uint32(0x0000000000380010ULL);
+
state->fifo_valid = !_hrt_get_bit(value, 0);
state->sink_accept = false; /* no monitor connected */
}
case FIFO_CHANNEL_HOST0_TO_SP0:
{
hrt_data value = ia_css_device_load_uint32(0x0000000000380018ULL);
+
state->fifo_valid = false; /* no monitor connected */
state->sink_accept = !_hrt_get_bit(value, 0);
}
assert(ID == FIFO_MONITOR0_ID);
assert(switch_id < N_FIFO_SWITCH);
- assert(state != NULL);
+ assert(state);
(void)ID;
fifo_switch_t sw_id;
assert(ID < N_FIFO_MONITOR_ID);
- assert(state != NULL);
+ assert(state);
for (ch_id = 0; ch_id < N_FIFO_CHANNEL; ch_id++) {
fifo_channel_get_state(ID, ch_id,
- &(state->fifo_channels[ch_id]));
+ &state->fifo_channels[ch_id]);
}
for (sw_id = 0; sw_id < N_FIFO_SWITCH; sw_id++) {
fifo_switch_get_state(ID, sw_id,
- &(state->fifo_switches[sw_id]));
+ &state->fifo_switches[sw_id]);
}
return;
}
-static inline bool fifo_monitor_status_valid (
+static inline bool fifo_monitor_status_valid(
const fifo_monitor_ID_t ID,
const unsigned int reg,
const unsigned int port_id)
const hrt_data sel)
{
assert(ID == FIFO_MONITOR0_ID);
- assert(FIFO_MONITOR_BASE[ID] != (hrt_address)-1);
+ assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1);
assert(switch_id < N_FIFO_SWITCH);
(void)ID;
const fifo_switch_t switch_id)
{
assert(ID == FIFO_MONITOR0_ID);
- assert(FIFO_MONITOR_BASE[ID] != (hrt_address)-1);
+ assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1);
assert(switch_id < N_FIFO_SWITCH);
(void)ID;
return gp_device_reg_load(GP_DEVICE0_ID, FIFO_SWITCH_ADDR[switch_id]);
}
-
STORAGE_CLASS_FIFO_MONITOR_C void fifo_monitor_reg_store(
const fifo_monitor_ID_t ID,
const unsigned int reg,
const hrt_data value)
{
assert(ID < N_FIFO_MONITOR_ID);
- assert(FIFO_MONITOR_BASE[ID] != (hrt_address)-1);
- ia_css_device_store_uint32(FIFO_MONITOR_BASE[ID] + reg*sizeof(hrt_data), value);
+ assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1);
+ ia_css_device_store_uint32(FIFO_MONITOR_BASE[ID] + reg * sizeof(hrt_data), value);
return;
}
const unsigned int reg)
{
assert(ID < N_FIFO_MONITOR_ID);
- assert(FIFO_MONITOR_BASE[ID] != (hrt_address)-1);
- return ia_css_device_load_uint32(FIFO_MONITOR_BASE[ID] + reg*sizeof(hrt_data));
+ assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1);
+ return ia_css_device_load_uint32(FIFO_MONITOR_BASE[ID] + reg * sizeof(hrt_data));
}
#endif /* __FIFO_MONITOR_PRIVATE_H_INCLUDED__ */
const gdc_ID_t ID,
const unsigned int reg);
-
#ifndef __INLINE_GDC__
#include "gdc_private.h"
#endif /* __INLINE_GDC__ */
unsigned int i, lut_offset = HRT_GDC_LUT_IDX;
assert(ID < N_GDC_ID);
- assert(HRT_GDC_LUT_COEFF_OFFSET <= (4*sizeof(hrt_data)));
+ assert(HRT_GDC_LUT_COEFF_OFFSET <= (4 * sizeof(hrt_data)));
for (i = 0; i < HRT_GDC_N; i++) {
hrt_data entry_0 = data[0][i] & HRT_GDC_BCI_COEF_MASK;
return (int)(1UL << HRT_GDC_FRAC_BITS);
}
-
/*
* Local function implementations
*/
const unsigned int reg,
const hrt_data value)
{
- ia_css_device_store_uint32(GDC_BASE[ID] + reg*sizeof(hrt_data), value);
+ ia_css_device_store_uint32(GDC_BASE[ID] + reg * sizeof(hrt_data), value);
return;
}
const gdc_ID_t ID,
const unsigned int reg)
{
- return ia_css_device_load_uint32(GDC_BASE[ID] + reg*sizeof(hrt_data));
+ return ia_css_device_load_uint32(GDC_BASE[ID] + reg * sizeof(hrt_data));
}
gp_device_state_t *state)
{
assert(ID < N_GP_DEVICE_ID);
- assert(state != NULL);
+ assert(state);
state->syncgen_enable = gp_device_reg_load(ID,
_REG_GP_SYNCGEN_ENABLE_ADDR);
const hrt_data value)
{
assert(ID < N_GP_DEVICE_ID);
- assert(GP_DEVICE_BASE[ID] != (hrt_address)-1);
+ assert(GP_DEVICE_BASE[ID] != (hrt_address) - 1);
assert((reg_addr % sizeof(hrt_data)) == 0);
ia_css_device_store_uint32(GP_DEVICE_BASE[ID] + reg_addr, value);
return;
gp_timer_reg_load(uint32_t reg);
static void
-gp_timer_reg_store(uint32_t reg, uint32_t value);
+gp_timer_reg_store(u32 reg, uint32_t value);
static uint32_t
gp_timer_reg_load(uint32_t reg)
}
static void
-gp_timer_reg_store(uint32_t reg, uint32_t value)
+gp_timer_reg_store(u32 reg, uint32_t value)
{
ia_css_device_store_uint32((GP_TIMER_BASE +
(reg * sizeof(uint32_t))),
/*Register offsets for timers [1,7] can be obtained
* by adding (GP_TIMERx_ID * sizeof(uint32_t))*/
#define _REG_GP_TIMER_ENABLE_ID(timer_id) HIVE_GP_TIMER_ENABLE_REG_IDX(timer_id)
-#define _REG_GP_TIMER_VALUE_ID(timer_id) HIVE_GP_TIMER_VALUE_REG_IDX(timer_id, HIVE_GP_TIMER_NUM_COUNTERS)
+#define _REG_GP_TIMER_VALUE_ID(timer_id) HIVE_GP_TIMER_VALUE_REG_IDX(timer_id, HIVE_GP_TIMER_NUM_COUNTERS)
#define _REG_GP_TIMER_COUNT_TYPE_ID(timer_id) HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer_id, HIVE_GP_TIMER_NUM_COUNTERS)
#define _REG_GP_TIMER_SIGNAL_SELECT_ID(timer_id) HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer_id, HIVE_GP_TIMER_NUM_COUNTERS)
-
#define _REG_GP_TIMER_IRQ_TRIGGER_VALUE_ID(irq_id) HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq_id, HIVE_GP_TIMER_NUM_COUNTERS)
#define _REG_GP_TIMER_IRQ_TIMER_SELECT_ID(irq_id) \
#define _REG_GP_TIMER_IRQ_ENABLE_ID(irq_id) \
HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq_id, HIVE_GP_TIMER_NUM_COUNTERS, HIVE_GP_TIMER_NUM_IRQS)
-
#endif /*__GP_TIMER_LOCAL_H_INCLUDED__*/
const hrt_data value)
{
OP___assert(ID < N_GPIO_ID);
-OP___assert(GPIO_BASE[ID] != (hrt_address)-1);
- ia_css_device_store_uint32(GPIO_BASE[ID] + reg*sizeof(hrt_data), value);
+OP___assert(GPIO_BASE[ID] != (hrt_address) - 1);
+ ia_css_device_store_uint32(GPIO_BASE[ID] + reg * sizeof(hrt_data), value);
return;
}
const unsigned int reg)
{
OP___assert(ID < N_GPIO_ID);
-OP___assert(GPIO_BASE[ID] != (hrt_address)-1);
- return ia_css_device_load_uint32(GPIO_BASE[ID] + reg*sizeof(hrt_data));
+OP___assert(GPIO_BASE[ID] != (hrt_address) - 1);
+ return ia_css_device_load_uint32(GPIO_BASE[ID] + reg * sizeof(hrt_data));
}
#endif /* __GPIO_PRIVATE_H_INCLUDED__ */
{
assert(ID < N_HMEM_ID);
(void)ID;
- return HMEM_SIZE*sizeof(hmem_data_t);
+ return HMEM_SIZE * sizeof(hmem_data_t);
}
#endif /* __HMEM_PRIVATE_H_INCLUDED__ */
INPUT_FORMATTER2_SRST_MASK,
INPUT_FORMATTER3_SRST_MASK};
-const uint8_t HIVE_IF_SWITCH_CODE[N_INPUT_FORMATTER_ID] = {
+const u8 HIVE_IF_SWITCH_CODE[N_INPUT_FORMATTER_ID] = {
HIVE_INPUT_SWITCH_SELECT_IF_PRIM,
HIVE_INPUT_SWITCH_SELECT_IF_PRIM,
HIVE_INPUT_SWITCH_SELECT_IF_SEC,
input_formatter_switch_state_t *state)
{
assert(ID < N_INPUT_FORMATTER_ID);
- assert(state != NULL);
+ assert(state);
/* We'll change this into an intelligent function to get switch info per IF */
(void)ID;
input_formatter_state_t *state)
{
assert(ID < N_INPUT_FORMATTER_ID);
- assert(state != NULL);
+ assert(state);
/*
state->reset = input_formatter_reg_load(ID,
HIVE_IF_RESET_ADDRESS);
input_formatter_bin_state_t *state)
{
assert(ID < N_INPUT_FORMATTER_ID);
- assert(state != NULL);
+ assert(state);
state->reset = input_formatter_reg_load(ID,
HIVE_STR2MEM_SOFT_RESET_REG_ADDRESS);
};
struct input_formatter_bin_state_s {
- uint32_t reset;
- uint32_t input_endianness;
- uint32_t output_endianness;
- uint32_t bitswap;
- uint32_t block_synch;
- uint32_t packet_synch;
- uint32_t readpostwrite_synch;
- uint32_t is_2ppc;
- uint32_t en_status_update;
+ u32 reset;
+ u32 input_endianness;
+ u32 output_endianness;
+ u32 bitswap;
+ u32 block_synch;
+ u32 packet_synch;
+ u32 readpostwrite_synch;
+ u32 is_2ppc;
+ u32 en_status_update;
};
static const unsigned int input_formatter_alignment[N_INPUT_FORMATTER_ID] = {
#define ZERO (0x0)
#define ONE (1U)
-static const ib_buffer_t IB_BUFFER_NULL = {0 ,0, 0 };
+static const ib_buffer_t IB_BUFFER_NULL = {0, 0, 0 };
static input_system_error_t input_system_configure_channel(
const channel_cfg_t channel);
static void capture_unit_configure(
const input_system_ID_t ID,
const sub_system_ID_t sub_id,
- const ib_buffer_t* const cfg);
+ const ib_buffer_t * const cfg);
static void acquisition_unit_configure(
const input_system_ID_t ID,
const sub_system_ID_t sub_id,
- const ib_buffer_t* const cfg);
+ const ib_buffer_t * const cfg);
static void ctrl_unit_configure(
const input_system_ID_t ID,
const sub_system_ID_t sub_id,
- const ctrl_unit_cfg_t* const cfg);
+ const ctrl_unit_cfg_t * const cfg);
static void input_system_network_configure(
const input_system_ID_t ID,
- const input_system_network_cfg_t * const cfg);
+ const input_system_network_cfg_t * const cfg);
// MW: CSI is previously named as "rx" short for "receiver"
static input_system_error_t set_csi_cfg(
- csi_cfg_t* const lhs,
- const csi_cfg_t* const rhs,
- input_system_config_flags_t* const flags);
+ csi_cfg_t * const lhs,
+ const csi_cfg_t * const rhs,
+ input_system_config_flags_t * const flags);
static input_system_error_t set_source_type(
- input_system_source_t* const lhs,
- const input_system_source_t rhs,
- input_system_config_flags_t* const flags);
+ input_system_source_t * const lhs,
+ const input_system_source_t rhs,
+ input_system_config_flags_t * const flags);
static input_system_error_t input_system_multiplexer_cfg(
- input_system_multiplex_t* const lhs,
+ input_system_multiplex_t * const lhs,
const input_system_multiplex_t rhs,
- input_system_config_flags_t* const flags);
-
-
+ input_system_config_flags_t * const flags);
static inline void capture_unit_get_state(
const input_system_ID_t ID,
static void input_switch_cfg(
const gp_device_ID_t ID,
- const input_switch_cfg_t * const cfg
+ const input_switch_cfg_t * const cfg
);
void input_system_get_state(
sub_system_ID_t sub_id;
assert(ID < N_INPUT_SYSTEM_ID);
- assert(state != NULL);
+ assert(state);
state->str_multicastA_sel = input_system_sub_system_reg_load(ID,
GPREGS_UNIT0_ID,
for (sub_id = CAPTURE_UNIT0_ID; sub_id < CAPTURE_UNIT0_ID + N_CAPTURE_UNIT_ID; sub_id++) {
capture_unit_get_state(ID, sub_id,
- &(state->capture_unit[sub_id - CAPTURE_UNIT0_ID]));
+ &state->capture_unit[sub_id - CAPTURE_UNIT0_ID]);
}
for (sub_id = ACQUISITION_UNIT0_ID; sub_id < ACQUISITION_UNIT0_ID + N_ACQUISITION_UNIT_ID; sub_id++) {
acquisition_unit_get_state(ID, sub_id,
- &(state->acquisition_unit[sub_id - ACQUISITION_UNIT0_ID]));
+ &state->acquisition_unit[sub_id - ACQUISITION_UNIT0_ID]);
}
for (sub_id = CTRL_UNIT0_ID; sub_id < CTRL_UNIT0_ID + N_CTRL_UNIT_ID; sub_id++) {
ctrl_unit_get_state(ID, sub_id,
- &(state->ctrl_unit_state[sub_id - CTRL_UNIT0_ID]));
+ &state->ctrl_unit_state[sub_id - CTRL_UNIT0_ID]);
}
return;
unsigned int ch_id;
assert(ID < N_RX_ID);
- assert(state != NULL);
+ assert(state);
state->fs_to_ls_delay = (uint8_t)receiver_reg_load(ID,
_HRT_CSS_RECEIVER_FS_TO_LS_DELAY_REG_IDX);
for (port_id = (enum mipi_port_id)0; port_id < N_MIPI_PORT_ID; port_id++) {
mipi_port_get_state(ID, port_id,
- &(state->mipi_port_state[port_id]));
+ &state->mipi_port_state[port_id]);
}
- for (ch_id = (unsigned int)0; ch_id < N_RX_CHANNEL_ID; ch_id++) {
+ for (ch_id = 0U; ch_id < N_RX_CHANNEL_ID; ch_id++) {
rx_channel_get_state(ID, ch_id,
- &(state->rx_channel_state[ch_id]));
+ &state->rx_channel_state[ch_id]);
}
state->be_gsp_acc_ovl = receiver_reg_load(ID,
val = (((uint8_t)pred) << 3) | comp;
switch (ch_id) {
- case 0: addr = ((field_id<6)?_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX:_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX);
+ case 0: addr = ((field_id < 6) ? _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX : _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX);
break;
- case 1: addr = ((field_id<6)?_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX:_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX);
+ case 1: addr = ((field_id < 6) ? _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX : _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX);
break;
- case 2: addr = ((field_id<6)?_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX:_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX);
+ case 2: addr = ((field_id < 6) ? _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX : _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX);
break;
- case 3: addr = ((field_id<6)?_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX:_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX);
+ case 3: addr = ((field_id < 6) ? _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX : _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX);
break;
default:
/* should not happen */
return;
}
- reg = ((field_id < 6)?(val << (field_id * 5)):(val << ((field_id - 6) * 5)));
+ reg = ((field_id < 6) ? (val << (field_id * 5)) : (val << ((field_id - 6) * 5)));
receiver_reg_store(ID, addr, reg);
return;
capture_unit_state_t *state)
{
assert(/*(sub_id >= CAPTURE_UNIT0_ID) &&*/ (sub_id <= CAPTURE_UNIT2_ID));
- assert(state != NULL);
+ assert(state);
state->StartMode = input_system_sub_system_reg_load(ID,
sub_id,
acquisition_unit_state_t *state)
{
assert(sub_id == ACQUISITION_UNIT0_ID);
- assert(state != NULL);
+ assert(state);
state->Start_Addr = input_system_sub_system_reg_load(ID,
sub_id,
ctrl_unit_state_t *state)
{
assert(sub_id == CTRL_UNIT0_ID);
- assert(state != NULL);
+ assert(state);
state->captA_start_addr = input_system_sub_system_reg_load(ID,
sub_id,
assert(ID < N_RX_ID);
assert(port_ID < N_MIPI_PORT_ID);
- assert(state != NULL);
+ assert(state);
state->device_ready = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX);
port_ID, _HRT_CSS_RECEIVER_RX_COUNT_REG_IDX);
for (i = 0; i < MIPI_4LANE_CFG ; i++) {
- state->lane_sync_count[i] = (uint8_t)((state->sync_count)>>(i*8));
- state->lane_rx_count[i] = (uint8_t)((state->rx_count)>>(i*8));
+ state->lane_sync_count[i] = (uint8_t)((state->sync_count) >> (i * 8));
+ state->lane_rx_count[i] = (uint8_t)((state->rx_count) >> (i * 8));
}
return;
assert(ID < N_RX_ID);
assert(ch_id < N_RX_CHANNEL_ID);
- assert(state != NULL);
+ assert(state);
switch (ch_id) {
case 0:
/* See Table 7.1.17,..., 7.1.24 */
for (i = 0; i < 6; i++) {
- uint8_t val = (uint8_t)((state->comp_scheme0)>>(i*5)) & 0x1f;
+ u8 val = (uint8_t)((state->comp_scheme0) >> (i * 5)) & 0x1f;
+
state->comp[i] = (mipi_compressor_t)(val & 0x07);
state->pred[i] = (mipi_predictor_t)((val & 0x18) >> 3);
}
for (i = 6; i < N_MIPI_FORMAT_CUSTOM; i++) {
- uint8_t val = (uint8_t)((state->comp_scheme0)>>((i-6)*5)) & 0x1f;
+ u8 val = (uint8_t)((state->comp_scheme0) >> ((i - 6) * 5)) & 0x1f;
+
state->comp[i] = (mipi_compressor_t)(val & 0x07);
state->pred[i] = (mipi_predictor_t)((val & 0x18) >> 3);
}
// Initialize the data&hsync LUT.
for (addr = _REG_GP_IFMT_input_switch_lut_reg0;
addr <= _REG_GP_IFMT_input_switch_lut_reg7; addr += SIZEOF_HRT_REG) {
-
gp_device_reg_store(ID, addr, ZERO);
}
static void input_switch_cfg(
const gp_device_ID_t ID,
- const input_switch_cfg_t * const cfg)
+ const input_switch_cfg_t * const cfg)
{
int addr_offset;
assert(ID < N_GP_DEVICE_ID);
- assert(cfg != NULL);
+ assert(cfg);
// Initialize the data&hsync LUT.
for (addr_offset = 0; addr_offset < N_RX_CHANNEL_ID * 2; addr_offset++) {
return;
}
-
static void input_system_network_rst(const input_system_ID_t ID)
{
unsigned int sub_id;
// Reset IRQ_CTRLs.
// Reset configuration data structures.
- for (i = 0; i < N_CHANNELS; i++ ) {
+ for (i = 0; i < N_CHANNELS; i++) {
config.ch_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET;
config.target_isp_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET;
config.target_sp_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET;
config.target_strm2mem_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET;
}
- for (i = 0; i < N_CSI_PORTS; i++ ) {
+ for (i = 0; i < N_CSI_PORTS; i++) {
config.csi_buffer_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET;
config.multicast[i] = INPUT_SYSTEM_CFG_FLAG_RESET;
}
{
input_system_error_t error = INPUT_SYSTEM_ERR_NO_ERROR;
// Check if channel is not already configured.
- if (config.ch_flags[channel.ch_id] & INPUT_SYSTEM_CFG_FLAG_SET){
+ if (config.ch_flags[channel.ch_id] & INPUT_SYSTEM_CFG_FLAG_SET) {
return INPUT_SYSTEM_ERR_CHANNEL_ALREADY_SET;
} else {
- switch (channel.source_type){
- case INPUT_SYSTEM_SOURCE_SENSOR :
+ switch (channel.source_type) {
+ case INPUT_SYSTEM_SOURCE_SENSOR:
error = input_system_configure_channel_sensor(channel);
break;
- case INPUT_SYSTEM_SOURCE_TPG :
+ case INPUT_SYSTEM_SOURCE_TPG:
return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
break;
- case INPUT_SYSTEM_SOURCE_PRBS :
+ case INPUT_SYSTEM_SOURCE_PRBS:
return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
break;
- case INPUT_SYSTEM_SOURCE_FIFO :
+ case INPUT_SYSTEM_SOURCE_FIFO:
return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
break;
- default :
+ default:
return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
break;
}
// Function that partitions input buffer space with determining addresses.
static input_system_error_t input_buffer_configuration(void)
{
- uint32_t current_address = 0;
- uint32_t unallocated_memory = IB_CAPACITY_IN_WORDS;
+ u32 current_address = 0;
+ u32 unallocated_memory = IB_CAPACITY_IN_WORDS;
- ib_buffer_t candidate_buffer_acq = IB_BUFFER_NULL;
- uint32_t size_requested;
- input_system_config_flags_t acq_already_specified = INPUT_SYSTEM_CFG_FLAG_RESET;
+ ib_buffer_t candidate_buffer_acq = IB_BUFFER_NULL;
+ u32 size_requested;
+ input_system_config_flags_t acq_already_specified = INPUT_SYSTEM_CFG_FLAG_RESET;
input_system_csi_port_t port;
- for (port = INPUT_SYSTEM_PORT_A; port < N_INPUT_SYSTEM_PORTS; port++) {
+ for (port = INPUT_SYSTEM_PORT_A; port < N_INPUT_SYSTEM_PORTS; port++) {
csi_cfg_t source = config.csi_value[port];//.csi_cfg;
- if ( config.csi_flags[port] & INPUT_SYSTEM_CFG_FLAG_SET) {
-
+ if (config.csi_flags[port] & INPUT_SYSTEM_CFG_FLAG_SET) {
// Check and set csi buffer in input buffer.
switch (source.buffering_mode) {
- case INPUT_SYSTEM_FIFO_CAPTURE :
- case INPUT_SYSTEM_XMEM_ACQUIRE :
+ case INPUT_SYSTEM_FIFO_CAPTURE:
+ case INPUT_SYSTEM_XMEM_ACQUIRE:
config.csi_buffer_flags[port] = INPUT_SYSTEM_CFG_FLAG_BLOCKED; // Well, not used.
break;
- case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING :
- case INPUT_SYSTEM_SRAM_BUFFERING :
- case INPUT_SYSTEM_XMEM_BUFFERING :
- case INPUT_SYSTEM_XMEM_CAPTURE :
+ case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING:
+ case INPUT_SYSTEM_SRAM_BUFFERING:
+ case INPUT_SYSTEM_XMEM_BUFFERING:
+ case INPUT_SYSTEM_XMEM_CAPTURE:
size_requested = source.csi_buffer.mem_reg_size * source.csi_buffer.nof_mem_regs;
if (source.csi_buffer.mem_reg_size > 0
- && source.csi_buffer.nof_mem_regs >0
+ && source.csi_buffer.nof_mem_regs > 0
&& size_requested <= unallocated_memory
) {
config.csi_buffer[port].mem_reg_addr = current_address;
config.csi_buffer[port].mem_reg_size = source.csi_buffer.mem_reg_size;
config.csi_buffer[port].nof_mem_regs = source.csi_buffer.nof_mem_regs;
current_address += size_requested;
- unallocated_memory -= size_requested;
+ unallocated_memory -= size_requested;
config.csi_buffer_flags[port] = INPUT_SYSTEM_CFG_FLAG_SET;
} else {
config.csi_buffer_flags[port] |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
}
break;
- default :
+ default:
config.csi_buffer_flags[port] |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
break;
// Check acquisition buffer specified but set it later since it has to be unique.
switch (source.buffering_mode) {
- case INPUT_SYSTEM_FIFO_CAPTURE :
- case INPUT_SYSTEM_SRAM_BUFFERING :
- case INPUT_SYSTEM_XMEM_CAPTURE :
+ case INPUT_SYSTEM_FIFO_CAPTURE:
+ case INPUT_SYSTEM_SRAM_BUFFERING:
+ case INPUT_SYSTEM_XMEM_CAPTURE:
// Nothing to do.
break;
- case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING :
- case INPUT_SYSTEM_XMEM_BUFFERING :
- case INPUT_SYSTEM_XMEM_ACQUIRE :
+ case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING:
+ case INPUT_SYSTEM_XMEM_BUFFERING:
+ case INPUT_SYSTEM_XMEM_ACQUIRE:
if (acq_already_specified == INPUT_SYSTEM_CFG_FLAG_RESET) {
size_requested = source.acquisition_buffer.mem_reg_size
* source.acquisition_buffer.nof_mem_regs;
if (source.acquisition_buffer.mem_reg_size > 0
- && source.acquisition_buffer.nof_mem_regs >0
+ && source.acquisition_buffer.nof_mem_regs > 0
&& size_requested <= unallocated_memory
) {
candidate_buffer_acq = source.acquisition_buffer;
}
break;
- default :
+ default:
return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
break;
}
config.acquisition_buffer_unique.mem_reg_size = candidate_buffer_acq.mem_reg_size;
config.acquisition_buffer_unique.nof_mem_regs = candidate_buffer_acq.nof_mem_regs;
current_address += size_requested;
- unallocated_memory -= size_requested;
+ unallocated_memory -= size_requested;
config.acquisition_buffer_unique_flags = INPUT_SYSTEM_CFG_FLAG_SET;
assert(current_address <= IB_CAPACITY_IN_WORDS);
static void capture_unit_configure(
const input_system_ID_t ID,
const sub_system_ID_t sub_id,
- const ib_buffer_t* const cfg)
+ const ib_buffer_t * const cfg)
{
assert(ID < N_INPUT_SYSTEM_ID);
assert(/*(sub_id >= CAPTURE_UNIT0_ID) &&*/ (sub_id <= CAPTURE_UNIT2_ID)); // Commented part is always true.
- assert(cfg != NULL);
+ assert(cfg);
input_system_sub_system_reg_store(ID,
sub_id,
return;
}
-
static void acquisition_unit_configure(
const input_system_ID_t ID,
const sub_system_ID_t sub_id,
- const ib_buffer_t* const cfg)
+ const ib_buffer_t * const cfg)
{
assert(ID < N_INPUT_SYSTEM_ID);
assert(sub_id == ACQUISITION_UNIT0_ID);
- assert(cfg != NULL);
+ assert(cfg);
input_system_sub_system_reg_store(ID,
sub_id,
return;
}
-
static void ctrl_unit_configure(
const input_system_ID_t ID,
const sub_system_ID_t sub_id,
- const ctrl_unit_cfg_t* const cfg)
+ const ctrl_unit_cfg_t * const cfg)
{
assert(ID < N_INPUT_SYSTEM_ID);
assert(sub_id == CTRL_UNIT0_ID);
- assert(cfg != NULL);
+ assert(cfg);
input_system_sub_system_reg_store(ID,
sub_id,
ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID,
cfg->buffer_acquire[ACQUISITION_UNIT0_ID - ACQUISITION_UNIT0_ID].nof_mem_regs);
input_system_sub_system_reg_store(ID,
- sub_id,
- ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID,
+ sub_id,
+ ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID,
0);
return;
}
static void input_system_network_configure(
const input_system_ID_t ID,
- const input_system_network_cfg_t * const cfg)
+ const input_system_network_cfg_t * const cfg)
{
- uint32_t sub_id;
+ u32 sub_id;
assert(ID < N_INPUT_SYSTEM_ID);
- assert(cfg != NULL);
+ assert(cfg);
// Set all 3 multicasts.
input_system_sub_system_reg_store(ID,
for (sub_id = CAPTURE_UNIT0_ID; sub_id < CAPTURE_UNIT0_ID + N_CAPTURE_UNIT_ID; sub_id++) {
capture_unit_configure(ID,
sub_id,
- &(cfg->ctrl_unit_cfg[ID].buffer_mipi[sub_id - CAPTURE_UNIT0_ID]));
+ &cfg->ctrl_unit_cfg[ID].buffer_mipi[sub_id - CAPTURE_UNIT0_ID]);
}
// Set acquisition units.
for (sub_id = ACQUISITION_UNIT0_ID; sub_id < ACQUISITION_UNIT0_ID + N_ACQUISITION_UNIT_ID; sub_id++) {
acquisition_unit_configure(ID,
sub_id,
- &(cfg->ctrl_unit_cfg[sub_id - ACQUISITION_UNIT0_ID].buffer_acquire[sub_id - ACQUISITION_UNIT0_ID]));
+ &cfg->ctrl_unit_cfg[sub_id - ACQUISITION_UNIT0_ID].buffer_acquire[sub_id - ACQUISITION_UNIT0_ID]);
}
// No DMA configuration needed. Ctrl_unit will fully control it.
for (sub_id = CTRL_UNIT0_ID; sub_id < CTRL_UNIT0_ID + N_CTRL_UNIT_ID; sub_id++) {
ctrl_unit_configure(ID,
sub_id,
- &(cfg->ctrl_unit_cfg[sub_id - CTRL_UNIT0_ID]));
+ &cfg->ctrl_unit_cfg[sub_id - CTRL_UNIT0_ID]);
}
return;
assert(config.source_type_flags & INPUT_SYSTEM_CFG_FLAG_SET);
switch (config.source_type) {
- case INPUT_SYSTEM_SOURCE_SENSOR :
+ case INPUT_SYSTEM_SOURCE_SENSOR:
// Determine stream multicasts setting based on the mode of csi_cfg_t.
// AM: This should be moved towards earlier function call, e.g. in
// the commit function.
for (i = MIPI_PORT0_ID; i < N_MIPI_PORT_ID; i++) {
if (config.csi_flags[i] & INPUT_SYSTEM_CFG_FLAG_SET) {
-
switch (config.csi_value[i].buffering_mode) {
-
case INPUT_SYSTEM_FIFO_CAPTURE:
config.multicast[i] = INPUT_SYSTEM_CSI_BACKEND;
break;
//break;
}
} else {
- config.multicast[i]= INPUT_SYSTEM_DISCARD_ALL;
+ config.multicast[i] = INPUT_SYSTEM_DISCARD_ALL;
}
input_system_network_cfg.multicast_cfg[i] = config.multicast[i];
//...
break;
- case INPUT_SYSTEM_SOURCE_TPG :
+ case INPUT_SYSTEM_SOURCE_TPG:
break;
- case INPUT_SYSTEM_SOURCE_PRBS :
+ case INPUT_SYSTEM_SOURCE_PRBS:
break;
- case INPUT_SYSTEM_SOURCE_FIFO :
+ case INPUT_SYSTEM_SOURCE_FIFO:
break;
- default :
+ default:
return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
break;
return INPUT_SYSTEM_ERR_NO_ERROR;
}
-
// Function that applies the whole configuration.
input_system_error_t input_system_configuration_commit(void)
{
// The last configuration step is to configure the input buffer.
input_system_error_t error = input_buffer_configuration();
+
if (error != INPUT_SYSTEM_ERR_NO_ERROR) {
return error;
}
return INPUT_SYSTEM_ERR_NO_ERROR;
}
-
-
// FIFO
input_system_error_t input_system_csi_fifo_channel_cfg(
- uint32_t ch_id,
+ u32 ch_id,
input_system_csi_port_t port,
backend_channel_cfg_t backend_ch,
target_cfg2400_t target
{
channel_cfg_t channel;
- channel.ch_id = ch_id;
- channel.backend_ch = backend_ch;
+ channel.ch_id = ch_id;
+ channel.backend_ch = backend_ch;
channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR;
//channel.source
channel.source_cfg.csi_cfg.csi_port = port;
channel.source_cfg.csi_cfg.buffering_mode = INPUT_SYSTEM_FIFO_CAPTURE;
- channel.source_cfg.csi_cfg.csi_buffer = IB_BUFFER_NULL;
+ channel.source_cfg.csi_cfg.csi_buffer = IB_BUFFER_NULL;
channel.source_cfg.csi_cfg.acquisition_buffer = IB_BUFFER_NULL;
channel.source_cfg.csi_cfg.nof_xmem_buffers = 0;
return input_system_configure_channel(channel);
}
-
input_system_error_t input_system_csi_fifo_channel_with_counting_cfg(
- uint32_t ch_id,
- uint32_t nof_frames,
+ u32 ch_id,
+ u32 nof_frames,
input_system_csi_port_t port,
backend_channel_cfg_t backend_ch,
- uint32_t csi_mem_reg_size,
- uint32_t csi_nof_mem_regs,
+ u32 csi_mem_reg_size,
+ u32 csi_nof_mem_regs,
target_cfg2400_t target
)
{
channel_cfg_t channel;
- channel.ch_id = ch_id;
- channel.backend_ch = backend_ch;
+ channel.ch_id = ch_id;
+ channel.backend_ch = backend_ch;
channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR;
//channel.source
channel.source_cfg.csi_cfg.csi_port = port;
channel.source_cfg.csi_cfg.buffering_mode = INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING;
channel.source_cfg.csi_cfg.csi_buffer.mem_reg_size = csi_mem_reg_size;
- channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs = csi_nof_mem_regs;
+ channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs = csi_nof_mem_regs;
channel.source_cfg.csi_cfg.csi_buffer.mem_reg_addr = 0;
channel.source_cfg.csi_cfg.acquisition_buffer = IB_BUFFER_NULL;
channel.source_cfg.csi_cfg.nof_xmem_buffers = nof_frames;
return input_system_configure_channel(channel);
}
-
// SRAM
input_system_error_t input_system_csi_sram_channel_cfg(
- uint32_t ch_id,
+ u32 ch_id,
input_system_csi_port_t port,
backend_channel_cfg_t backend_ch,
- uint32_t csi_mem_reg_size,
- uint32_t csi_nof_mem_regs,
+ u32 csi_mem_reg_size,
+ u32 csi_nof_mem_regs,
// uint32_t acq_mem_reg_size,
// uint32_t acq_nof_mem_regs,
- target_cfg2400_t target
+ target_cfg2400_t target
)
{
channel_cfg_t channel;
- channel.ch_id = ch_id;
- channel.backend_ch = backend_ch;
+ channel.ch_id = ch_id;
+ channel.backend_ch = backend_ch;
channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR;
//channel.source
channel.source_cfg.csi_cfg.csi_port = port;
channel.source_cfg.csi_cfg.buffering_mode = INPUT_SYSTEM_SRAM_BUFFERING;
channel.source_cfg.csi_cfg.csi_buffer.mem_reg_size = csi_mem_reg_size;
- channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs = csi_nof_mem_regs;
+ channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs = csi_nof_mem_regs;
channel.source_cfg.csi_cfg.csi_buffer.mem_reg_addr = 0;
channel.source_cfg.csi_cfg.acquisition_buffer = IB_BUFFER_NULL;
channel.source_cfg.csi_cfg.nof_xmem_buffers = 0;
return input_system_configure_channel(channel);
}
-
//XMEM
// Collects all parameters and puts them in channel_cfg_t.
input_system_error_t input_system_csi_xmem_channel_cfg(
- uint32_t ch_id,
+ u32 ch_id,
input_system_csi_port_t port,
backend_channel_cfg_t backend_ch,
- uint32_t csi_mem_reg_size,
- uint32_t csi_nof_mem_regs,
- uint32_t acq_mem_reg_size,
- uint32_t acq_nof_mem_regs,
- target_cfg2400_t target,
- uint32_t nof_xmem_buffers
+ u32 csi_mem_reg_size,
+ u32 csi_nof_mem_regs,
+ u32 acq_mem_reg_size,
+ u32 acq_nof_mem_regs,
+ target_cfg2400_t target,
+ uint32_t nof_xmem_buffers
)
{
channel_cfg_t channel;
- channel.ch_id = ch_id;
- channel.backend_ch = backend_ch;
+ channel.ch_id = ch_id;
+ channel.backend_ch = backend_ch;
channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR;
//channel.source
channel.source_cfg.csi_cfg.csi_port = port;
channel.source_cfg.csi_cfg.buffering_mode = INPUT_SYSTEM_XMEM_BUFFERING;
channel.source_cfg.csi_cfg.csi_buffer.mem_reg_size = csi_mem_reg_size;
- channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs = csi_nof_mem_regs;
+ channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs = csi_nof_mem_regs;
channel.source_cfg.csi_cfg.csi_buffer.mem_reg_addr = 0;
channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_size = acq_mem_reg_size;
- channel.source_cfg.csi_cfg.acquisition_buffer.nof_mem_regs = acq_nof_mem_regs;
+ channel.source_cfg.csi_cfg.acquisition_buffer.nof_mem_regs = acq_nof_mem_regs;
channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_addr = 0;
channel.source_cfg.csi_cfg.nof_xmem_buffers = nof_xmem_buffers;
return input_system_configure_channel(channel);
}
-
-
-
input_system_error_t input_system_csi_xmem_acquire_only_channel_cfg(
- uint32_t ch_id,
- uint32_t nof_frames,
+ u32 ch_id,
+ u32 nof_frames,
input_system_csi_port_t port,
backend_channel_cfg_t backend_ch,
- uint32_t acq_mem_reg_size,
- uint32_t acq_nof_mem_regs,
- target_cfg2400_t target)
+ u32 acq_mem_reg_size,
+ u32 acq_nof_mem_regs,
+ target_cfg2400_t target)
{
channel_cfg_t channel;
- channel.ch_id = ch_id;
- channel.backend_ch = backend_ch;
+ channel.ch_id = ch_id;
+ channel.backend_ch = backend_ch;
channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR;
//channel.source
channel.source_cfg.csi_cfg.csi_port = port;
channel.source_cfg.csi_cfg.buffering_mode = INPUT_SYSTEM_XMEM_ACQUIRE;
channel.source_cfg.csi_cfg.csi_buffer = IB_BUFFER_NULL;
channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_size = acq_mem_reg_size;
- channel.source_cfg.csi_cfg.acquisition_buffer.nof_mem_regs = acq_nof_mem_regs;
+ channel.source_cfg.csi_cfg.acquisition_buffer.nof_mem_regs = acq_nof_mem_regs;
channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_addr = 0;
channel.source_cfg.csi_cfg.nof_xmem_buffers = nof_frames;
return input_system_configure_channel(channel);
}
-
input_system_error_t input_system_csi_xmem_capture_only_channel_cfg(
- uint32_t ch_id,
- uint32_t nof_frames,
+ u32 ch_id,
+ u32 nof_frames,
input_system_csi_port_t port,
- uint32_t csi_mem_reg_size,
- uint32_t csi_nof_mem_regs,
- uint32_t acq_mem_reg_size,
- uint32_t acq_nof_mem_regs,
- target_cfg2400_t target)
+ u32 csi_mem_reg_size,
+ u32 csi_nof_mem_regs,
+ u32 acq_mem_reg_size,
+ u32 acq_nof_mem_regs,
+ target_cfg2400_t target)
{
channel_cfg_t channel;
- channel.ch_id = ch_id;
- //channel.backend_ch = backend_ch;
+ channel.ch_id = ch_id;
+ //channel.backend_ch = backend_ch;
channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR;
//channel.source
channel.source_cfg.csi_cfg.csi_port = port;
- //channel.source_cfg.csi_cfg.backend_ch = backend_ch;
+ //channel.source_cfg.csi_cfg.backend_ch = backend_ch;
channel.source_cfg.csi_cfg.buffering_mode = INPUT_SYSTEM_XMEM_CAPTURE;
channel.source_cfg.csi_cfg.csi_buffer.mem_reg_size = csi_mem_reg_size;
- channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs = csi_nof_mem_regs;
+ channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs = csi_nof_mem_regs;
channel.source_cfg.csi_cfg.csi_buffer.mem_reg_addr = 0;
channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_size = acq_mem_reg_size;
- channel.source_cfg.csi_cfg.acquisition_buffer.nof_mem_regs = acq_nof_mem_regs;
+ channel.source_cfg.csi_cfg.acquisition_buffer.nof_mem_regs = acq_nof_mem_regs;
channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_addr = 0;
channel.source_cfg.csi_cfg.nof_xmem_buffers = nof_frames;
return input_system_configure_channel(channel);
}
-
-
// Non - CSI
input_system_error_t input_system_prbs_channel_cfg(
- uint32_t ch_id,
- uint32_t nof_frames,//not used yet
- uint32_t seed,
- uint32_t sync_gen_width,
- uint32_t sync_gen_height,
- uint32_t sync_gen_hblank_cycles,
- uint32_t sync_gen_vblank_cycles,
+ u32 ch_id,
+ u32 nof_frames,//not used yet
+ u32 seed,
+ u32 sync_gen_width,
+ u32 sync_gen_height,
+ u32 sync_gen_hblank_cycles,
+ u32 sync_gen_vblank_cycles,
target_cfg2400_t target
)
{
(void)nof_frames;
- channel.ch_id = ch_id;
- channel.source_type= INPUT_SYSTEM_SOURCE_PRBS;
+ channel.ch_id = ch_id;
+ channel.source_type = INPUT_SYSTEM_SOURCE_PRBS;
channel.source_cfg.prbs_cfg.seed = seed;
- channel.source_cfg.prbs_cfg.sync_gen_cfg.width = sync_gen_width;
- channel.source_cfg.prbs_cfg.sync_gen_cfg.height = sync_gen_height;
+ channel.source_cfg.prbs_cfg.sync_gen_cfg.width = sync_gen_width;
+ channel.source_cfg.prbs_cfg.sync_gen_cfg.height = sync_gen_height;
channel.source_cfg.prbs_cfg.sync_gen_cfg.hblank_cycles = sync_gen_hblank_cycles;
- channel.source_cfg.prbs_cfg.sync_gen_cfg.vblank_cycles = sync_gen_vblank_cycles;
+ channel.source_cfg.prbs_cfg.sync_gen_cfg.vblank_cycles = sync_gen_vblank_cycles;
channel.target_cfg = target;
return input_system_configure_channel(channel);
}
-
-
input_system_error_t input_system_tpg_channel_cfg(
- uint32_t ch_id,
- uint32_t nof_frames,//not used yet
- uint32_t x_mask,
- uint32_t y_mask,
- uint32_t x_delta,
- uint32_t y_delta,
- uint32_t xy_mask,
- uint32_t sync_gen_width,
- uint32_t sync_gen_height,
- uint32_t sync_gen_hblank_cycles,
- uint32_t sync_gen_vblank_cycles,
+ u32 ch_id,
+ u32 nof_frames,//not used yet
+ u32 x_mask,
+ u32 y_mask,
+ u32 x_delta,
+ u32 y_delta,
+ u32 xy_mask,
+ u32 sync_gen_width,
+ u32 sync_gen_height,
+ u32 sync_gen_hblank_cycles,
+ u32 sync_gen_vblank_cycles,
target_cfg2400_t target
)
{
(void)nof_frames;
- channel.ch_id = ch_id;
+ channel.ch_id = ch_id;
channel.source_type = INPUT_SYSTEM_SOURCE_TPG;
channel.source_cfg.tpg_cfg.x_mask = x_mask;
channel.source_cfg.tpg_cfg.x_delta = x_delta;
channel.source_cfg.tpg_cfg.y_delta = y_delta;
channel.source_cfg.tpg_cfg.xy_mask = xy_mask;
- channel.source_cfg.tpg_cfg.sync_gen_cfg.width = sync_gen_width;
- channel.source_cfg.tpg_cfg.sync_gen_cfg.height = sync_gen_height;
+ channel.source_cfg.tpg_cfg.sync_gen_cfg.width = sync_gen_width;
+ channel.source_cfg.tpg_cfg.sync_gen_cfg.height = sync_gen_height;
channel.source_cfg.tpg_cfg.sync_gen_cfg.hblank_cycles = sync_gen_hblank_cycles;
- channel.source_cfg.tpg_cfg.sync_gen_cfg.vblank_cycles = sync_gen_vblank_cycles;
+ channel.source_cfg.tpg_cfg.sync_gen_cfg.vblank_cycles = sync_gen_vblank_cycles;
channel.target_cfg = target;
return input_system_configure_channel(channel);
// MW: Don't use system specific names, (even in system specific files) "cfg2400" -> cfg
input_system_error_t input_system_gpfifo_channel_cfg(
- uint32_t ch_id,
- uint32_t nof_frames, //not used yet
+ u32 ch_id,
+ u32 nof_frames, //not used yet
+
target_cfg2400_t target)
{
channel_cfg_t channel;
(void)nof_frames;
- channel.ch_id = ch_id;
+ channel.ch_id = ch_id;
channel.source_type = INPUT_SYSTEM_SOURCE_FIFO;
channel.target_cfg = target;
static input_system_error_t input_system_configure_channel_sensor(
const channel_cfg_t channel)
{
- const uint32_t port = channel.source_cfg.csi_cfg.csi_port;
+ const u32 port = channel.source_cfg.csi_cfg.csi_port;
input_system_error_t status = INPUT_SYSTEM_ERR_NO_ERROR;
input_system_multiplex_t mux;
//check if port > N_INPUT_SYSTEM_MULTIPLEX
- status = set_source_type(&(config.source_type), channel.source_type, &config.source_type_flags);
+ status = set_source_type(&config.source_type, channel.source_type, &config.source_type_flags);
if (status != INPUT_SYSTEM_ERR_NO_ERROR) return status;
// Check for conflicts on source (implicitly on multicast, capture unit and input buffer).
- status = set_csi_cfg(&(config.csi_value[port]), &channel.source_cfg.csi_cfg, &(config.csi_flags[port]));
+ status = set_csi_cfg(&config.csi_value[port], &channel.source_cfg.csi_cfg, &config.csi_flags[port]);
if (status != INPUT_SYSTEM_ERR_NO_ERROR) return status;
-
- switch (channel.source_cfg.csi_cfg.buffering_mode){
+ switch (channel.source_cfg.csi_cfg.buffering_mode) {
case INPUT_SYSTEM_FIFO_CAPTURE:
// Check for conflicts on mux.
//config.acquisition_buffer_unique_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED;
break;
- case INPUT_SYSTEM_SRAM_BUFFERING :
+ case INPUT_SYSTEM_SRAM_BUFFERING:
// Check for conflicts on mux.
mux = INPUT_SYSTEM_ACQUISITION_UNIT;
//config.acquisition_buffer_unique_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED;
break;
- case INPUT_SYSTEM_XMEM_BUFFERING :
+ case INPUT_SYSTEM_XMEM_BUFFERING:
// Check for conflicts on mux.
mux = INPUT_SYSTEM_ACQUISITION_UNIT;
//config.acquisition_buffer_unique_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED;
break;
- case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING :
+ case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING:
return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
break;
- case INPUT_SYSTEM_XMEM_CAPTURE :
+ case INPUT_SYSTEM_XMEM_CAPTURE:
return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
break;
- case INPUT_SYSTEM_XMEM_ACQUIRE :
+ case INPUT_SYSTEM_XMEM_ACQUIRE:
return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
break;
- default :
+ default:
return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED;
break;
}
// Test flags and set structure.
static input_system_error_t set_source_type(
- input_system_source_t * const lhs,
- const input_system_source_t rhs,
- input_system_config_flags_t * const flags)
+ input_system_source_t * const lhs,
+ const input_system_source_t rhs,
+ input_system_config_flags_t * const flags)
{
// MW: Not enough asserts
- assert(lhs != NULL);
- assert(flags != NULL);
+ assert(lhs);
+ assert(flags);
if ((*flags) & INPUT_SYSTEM_CFG_FLAG_BLOCKED) {
*flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
// Check for consistency with already set value.
if ((*lhs) == (rhs)) {
return INPUT_SYSTEM_ERR_NO_ERROR;
- }
- else {
+ } else {
*flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE;
}
return INPUT_SYSTEM_ERR_NO_ERROR;
}
-
// Test flags and set structure.
static input_system_error_t set_csi_cfg(
- csi_cfg_t* const lhs,
- const csi_cfg_t* const rhs,
- input_system_config_flags_t * const flags)
+ csi_cfg_t * const lhs,
+ const csi_cfg_t * const rhs,
+ input_system_config_flags_t * const flags)
{
- uint32_t memory_required;
- uint32_t acq_memory_required;
+ u32 memory_required;
+ u32 acq_memory_required;
- assert(lhs != NULL);
- assert(flags != NULL);
+ assert(lhs);
+ assert(flags);
if ((*flags) & INPUT_SYSTEM_CFG_FLAG_BLOCKED) {
*flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
&& lhs->nof_xmem_buffers == rhs->nof_xmem_buffers
) {
return INPUT_SYSTEM_ERR_NO_ERROR;
- }
- else {
+ } else {
*flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE;
}
if (rhs->buffering_mode >= N_INPUT_SYSTEM_BUFFERING_MODE
||
// Check if required memory is available in input buffer (SRAM).
- (memory_required + acq_memory_required )> config.unallocated_ib_mem_words
+ (memory_required + acq_memory_required) > config.unallocated_ib_mem_words
) {
*flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE;
}
// Set the value.
- //lhs[port]->backend_ch = rhs.backend_ch;
- lhs->buffering_mode = rhs->buffering_mode;
+ //lhs[port]->backend_ch = rhs.backend_ch;
+ lhs->buffering_mode = rhs->buffering_mode;
lhs->nof_xmem_buffers = rhs->nof_xmem_buffers;
lhs->csi_buffer.mem_reg_size = rhs->csi_buffer.mem_reg_size;
return INPUT_SYSTEM_ERR_NO_ERROR;
}
-
// Test flags and set structure.
static input_system_error_t input_system_multiplexer_cfg(
- input_system_multiplex_t* const lhs,
+ input_system_multiplex_t * const lhs,
const input_system_multiplex_t rhs,
- input_system_config_flags_t* const flags)
+ input_system_config_flags_t * const flags)
{
- assert(lhs != NULL);
- assert(flags != NULL);
+ assert(lhs);
+ assert(flags);
if ((*flags) & INPUT_SYSTEM_CFG_FLAG_BLOCKED) {
*flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
// Check for consistency with already set value.
if ((*lhs) == (rhs)) {
return INPUT_SYSTEM_ERR_NO_ERROR;
- }
- else {
+ } else {
*flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT;
return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE;
}
#include "isp_acquisition_defs.h"
#include "input_system_ctrl_defs.h"
-
typedef enum {
INPUT_SYSTEM_ERR_NO_ERROR = 0,
INPUT_SYSTEM_ERR_GENERIC,
typedef struct ctrl_unit_cfg_s ctrl_unit_cfg_t;
typedef struct input_system_network_cfg_s input_system_network_cfg_t;
-typedef struct target_cfg2400_s target_cfg2400_t;
-typedef struct channel_cfg_s channel_cfg_t;
-typedef struct backend_channel_cfg_s backend_channel_cfg_t;
-typedef struct input_system_cfg2400_s input_system_cfg2400_t;
+typedef struct target_cfg2400_s target_cfg2400_t;
+typedef struct channel_cfg_s channel_cfg_t;
+typedef struct backend_channel_cfg_s backend_channel_cfg_t;
+typedef struct input_system_cfg2400_s input_system_cfg2400_t;
typedef struct mipi_port_state_s mipi_port_state_t;
typedef struct rx_channel_state_s rx_channel_state_t;
-typedef struct input_switch_cfg_channel_s input_switch_cfg_channel_t;
-typedef struct input_switch_cfg_s input_switch_cfg_t;
+typedef struct input_switch_cfg_channel_s input_switch_cfg_channel_t;
+typedef struct input_switch_cfg_s input_switch_cfg_t;
struct ctrl_unit_cfg_s {
ib_buffer_t buffer_mipi[N_CAPTURE_UNIT_ID];
typedef struct {
// TBD.
- uint32_t dummy_parameter;
+ u32 dummy_parameter;
} target_isp_cfg_t;
-
typedef struct {
// TBD.
- uint32_t dummy_parameter;
+ u32 dummy_parameter;
} target_sp_cfg_t;
-
typedef struct {
// TBD.
- uint32_t dummy_parameter;
+ u32 dummy_parameter;
} target_strm2mem_cfg_t;
struct input_switch_cfg_channel_s {
- uint32_t hsync_data_reg[2];
- uint32_t vsync_data_reg;
+ u32 hsync_data_reg[2];
+ u32 vsync_data_reg;
};
struct target_cfg2400_s {
- input_switch_cfg_channel_t input_switch_channel_cfg;
+ input_switch_cfg_channel_t input_switch_channel_cfg;
target_isp_cfg_t target_isp_cfg;
target_sp_cfg_t target_sp_cfg;
target_strm2mem_cfg_t target_strm2mem_cfg;
};
struct backend_channel_cfg_s {
- uint32_t fmt_control_word_1; // Format config.
- uint32_t fmt_control_word_2;
- uint32_t no_side_band;
+ u32 fmt_control_word_1; // Format config.
+ u32 fmt_control_word_2;
+ u32 no_side_band;
};
typedef union {
gpfifo_cfg_t gpfifo_cfg;
} source_cfg_t;
-
struct input_switch_cfg_s {
- uint32_t hsync_data_reg[N_RX_CHANNEL_ID * 2];
- uint32_t vsync_data_reg;
+ u32 hsync_data_reg[N_RX_CHANNEL_ID * 2];
+ u32 vsync_data_reg;
};
// Configuration of a channel.
struct channel_cfg_s {
- uint32_t ch_id;
+ u32 ch_id;
backend_channel_cfg_t backend_ch;
input_system_source_t source_type;
source_cfg_t source_cfg;
target_cfg2400_t target_cfg;
};
-
// Complete configuration for input system.
struct input_system_cfg2400_s {
-
input_system_source_t source_type; input_system_config_flags_t source_type_flags;
//channel_cfg_t channel[N_CHANNELS];
input_system_config_flags_t ch_flags[N_CHANNELS];
// This buffers set at the end, based on the all configurations.
ib_buffer_t csi_buffer[N_CSI_PORTS]; input_system_config_flags_t csi_buffer_flags[N_CSI_PORTS];
ib_buffer_t acquisition_buffer_unique; input_system_config_flags_t acquisition_buffer_unique_flags;
- uint32_t unallocated_ib_mem_words; // Used for check.DEFAULT = IB_CAPACITY_IN_WORDS.
+ u32 unallocated_ib_mem_words; // Used for check.DEFAULT = IB_CAPACITY_IN_WORDS.
//uint32_t acq_allocated_ib_mem_words;
input_system_connection_t multicast[N_CSI_PORTS];
- input_system_multiplex_t multiplexer; input_system_config_flags_t multiplexer_flags;
-
+ input_system_multiplex_t multiplexer; input_system_config_flags_t multiplexer_flags;
tpg_cfg_t tpg_value; input_system_config_flags_t tpg_flags;
prbs_cfg_t prbs_value; input_system_config_flags_t prbs_flags;
gpfifo_cfg_t gpfifo_value; input_system_config_flags_t gpfifo_flags;
-
input_switch_cfg_t input_switch_cfg;
-
- target_isp_cfg_t target_isp [N_CHANNELS]; input_system_config_flags_t target_isp_flags [N_CHANNELS];
- target_sp_cfg_t target_sp [N_CHANNELS]; input_system_config_flags_t target_sp_flags [N_CHANNELS];
- target_strm2mem_cfg_t target_strm2mem [N_CHANNELS]; input_system_config_flags_t target_strm2mem_flags [N_CHANNELS];
+ target_isp_cfg_t target_isp[N_CHANNELS]; input_system_config_flags_t target_isp_flags[N_CHANNELS];
+ target_sp_cfg_t target_sp[N_CHANNELS]; input_system_config_flags_t target_sp_flags[N_CHANNELS];
+ target_strm2mem_cfg_t target_strm2mem[N_CHANNELS]; input_system_config_flags_t target_strm2mem_flags[N_CHANNELS];
input_system_config_flags_t session_flags;
#define _HRT_CSS_RECEIVER_BE_IRQ_STATUS_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX + _HRT_CSS_BE_OFFSET)
#define _HRT_CSS_RECEIVER_BE_IRQ_CLEAR_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX + _HRT_CSS_BE_OFFSET)
-
#define _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT
#define _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT
#define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT
int device_ready;
int irq_status;
int irq_enable;
- uint32_t timeout_count;
- uint16_t init_count;
- uint16_t raw16_18;
- uint32_t sync_count; /*4 x uint8_t */
- uint32_t rx_count; /*4 x uint8_t */
- uint8_t lane_sync_count[MIPI_4LANE_CFG];
- uint8_t lane_rx_count[MIPI_4LANE_CFG];
+ u32 timeout_count;
+ u16 init_count;
+ u16 raw16_18;
+ u32 sync_count; /*4 x uint8_t */
+ u32 rx_count; /*4 x uint8_t */
+ u8 lane_sync_count[MIPI_4LANE_CFG];
+ u8 lane_rx_count[MIPI_4LANE_CFG];
};
struct rx_channel_state_s {
- uint32_t comp_scheme0;
- uint32_t comp_scheme1;
+ u32 comp_scheme0;
+ u32 comp_scheme1;
mipi_predictor_t pred[N_MIPI_FORMAT_CUSTOM];
mipi_compressor_t comp[N_MIPI_FORMAT_CUSTOM];
};
struct receiver_state_s {
- uint8_t fs_to_ls_delay;
- uint8_t ls_to_data_delay;
- uint8_t data_to_le_delay;
- uint8_t le_to_fe_delay;
- uint8_t fe_to_fs_delay;
- uint8_t le_to_fs_delay;
+ u8 fs_to_ls_delay;
+ u8 ls_to_data_delay;
+ u8 data_to_le_delay;
+ u8 le_to_fe_delay;
+ u8 fe_to_fs_delay;
+ u8 le_to_fs_delay;
bool is_two_ppc;
int backend_rst;
- uint16_t raw18;
+ u16 raw18;
bool force_raw8;
- uint16_t raw16;
+ u16 raw16;
struct mipi_port_state_s mipi_port_state[N_MIPI_PORT_ID];
struct rx_channel_state_s rx_channel_state[N_RX_CHANNEL_ID];
int be_gsp_acc_ovl;
{
assert(ID < N_INPUT_SYSTEM_ID);
assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1);
- ia_css_device_store_uint32(INPUT_SYSTEM_BASE[ID] + reg*sizeof(hrt_data), value);
+ ia_css_device_store_uint32(INPUT_SYSTEM_BASE[ID] + reg * sizeof(hrt_data), value);
return;
}
{
assert(ID < N_INPUT_SYSTEM_ID);
assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1);
- return ia_css_device_load_uint32(INPUT_SYSTEM_BASE[ID] + reg*sizeof(hrt_data));
+ return ia_css_device_load_uint32(INPUT_SYSTEM_BASE[ID] + reg * sizeof(hrt_data));
}
STORAGE_CLASS_INPUT_SYSTEM_C void receiver_reg_store(
{
assert(ID < N_RX_ID);
assert(RX_BASE[ID] != (hrt_address)-1);
- ia_css_device_store_uint32(RX_BASE[ID] + reg*sizeof(hrt_data), value);
+ ia_css_device_store_uint32(RX_BASE[ID] + reg * sizeof(hrt_data), value);
return;
}
{
assert(ID < N_RX_ID);
assert(RX_BASE[ID] != (hrt_address)-1);
- return ia_css_device_load_uint32(RX_BASE[ID] + reg*sizeof(hrt_data));
+ return ia_css_device_load_uint32(RX_BASE[ID] + reg * sizeof(hrt_data));
}
STORAGE_CLASS_INPUT_SYSTEM_C void receiver_port_reg_store(
assert(port_ID < N_MIPI_PORT_ID);
assert(RX_BASE[ID] != (hrt_address)-1);
assert(MIPI_PORT_OFFSET[port_ID] != (hrt_address)-1);
- ia_css_device_store_uint32(RX_BASE[ID] + MIPI_PORT_OFFSET[port_ID] + reg*sizeof(hrt_data), value);
+ ia_css_device_store_uint32(RX_BASE[ID] + MIPI_PORT_OFFSET[port_ID] + reg * sizeof(hrt_data), value);
return;
}
assert(port_ID < N_MIPI_PORT_ID);
assert(RX_BASE[ID] != (hrt_address)-1);
assert(MIPI_PORT_OFFSET[port_ID] != (hrt_address)-1);
- return ia_css_device_load_uint32(RX_BASE[ID] + MIPI_PORT_OFFSET[port_ID] + reg*sizeof(hrt_data));
+ return ia_css_device_load_uint32(RX_BASE[ID] + MIPI_PORT_OFFSET[port_ID] + reg * sizeof(hrt_data));
}
STORAGE_CLASS_INPUT_SYSTEM_C void input_system_sub_system_reg_store(
assert(sub_ID < N_SUB_SYSTEM_ID);
assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1);
assert(SUB_SYSTEM_OFFSET[sub_ID] != (hrt_address)-1);
- ia_css_device_store_uint32(INPUT_SYSTEM_BASE[ID] + SUB_SYSTEM_OFFSET[sub_ID] + reg*sizeof(hrt_data), value);
+ ia_css_device_store_uint32(INPUT_SYSTEM_BASE[ID] + SUB_SYSTEM_OFFSET[sub_ID] + reg * sizeof(hrt_data), value);
return;
}
assert(sub_ID < N_SUB_SYSTEM_ID);
assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1);
assert(SUB_SYSTEM_OFFSET[sub_ID] != (hrt_address)-1);
- return ia_css_device_load_uint32(INPUT_SYSTEM_BASE[ID] + SUB_SYSTEM_OFFSET[sub_ID] + reg*sizeof(hrt_data));
+ return ia_css_device_load_uint32(INPUT_SYSTEM_BASE[ID] + SUB_SYSTEM_OFFSET[sub_ID] + reg * sizeof(hrt_data));
}
#endif /* __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ */
assert(IRQ_N_CHANNEL[ID] <= HRT_DATA_WIDTH);
if (IRQ_N_CHANNEL[ID] < HRT_DATA_WIDTH) {
- mask = ~((~(hrt_data)0)>>IRQ_N_CHANNEL[ID]);
+ mask = ~((~(hrt_data)0) >> IRQ_N_CHANNEL[ID]);
}
irq_reg_store(ID,
void irq_enable_pulse(
const irq_ID_t ID,
- bool pulse)
+ bool pulse)
{
unsigned int edge_out = 0x0;
enum hrt_isp_css_irq_status status = hrt_isp_css_irq_status_success;
assert(ID < N_IRQ_ID);
- assert(irq_id != NULL);
+ assert(irq_id);
/* find the first irq bit */
for (idx = 0; idx < IRQ_N_CHANNEL[ID]; idx++) {
irq_wait_for_write_complete(ID);
- if (irq_id != NULL)
+ if (irq_id)
*irq_id = (unsigned int)idx;
return status;
irq_controller_state_t *state)
{
assert(ID < N_IRQ_ID);
- assert(state != NULL);
+ assert(state);
state->irq_edge = irq_reg_load(ID,
_HRT_IRQ_CONTROLLER_EDGE_REG_IDX);
irq_ID_t i;
unsigned int channel_ID;
irq_ID_t ID = virq_get_irq_id(irq_ID, &channel_ID);
-
+
assert(ID < N_IRQ_ID);
- for (i=IRQ1_ID;i<N_IRQ_ID;i++) {
+ for (i = IRQ1_ID; i < N_IRQ_ID; i++) {
/* It is not allowed to enable the pin of a nested IRQ directly */
assert(irq_ID != IRQ_NESTING_ID[i]);
}
return;
}
-
void virq_clear_all(void)
{
irq_ID_t irq_id;
enum hrt_isp_css_irq_status irq_status = hrt_isp_css_irq_status_error;
irq_ID_t ID;
- assert(irq_info != NULL);
+ assert(irq_info);
for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) {
if (any_irq_channel_enabled(ID)) {
{
irq_ID_t ID;
- assert(irq_info != NULL);
+ assert(irq_info);
for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) {
irq_info->irq_status_reg[ID] = 0;
enum hrt_isp_css_irq_status status = hrt_isp_css_irq_status_success;
irq_ID_t ID;
- assert(irq_id != NULL);
+ assert(irq_id);
/* find the first irq bit on device 0 */
for (idx = 0; idx < IRQ_N_CHANNEL[IRQ0_ID]; idx++) {
}
/* Check whether we have an IRQ on one of the nested devices */
- for (ID = N_IRQ_ID-1 ; ID > (irq_ID_t)0; ID--) {
+ for (ID = N_IRQ_ID - 1 ; ID > (irq_ID_t)0; ID--) {
if (IRQ_NESTING_ID[ID] == (virq_id_t)idx) {
break;
}
irq_wait_for_write_complete(ID);
idx += IRQ_N_ID_OFFSET[ID];
- if (irq_id != NULL)
+ if (irq_id)
*irq_id = (virq_id_t)idx;
return status;
assert(ID < N_IRQ_ID);
assert(IRQ_BASE[ID] != (hrt_address)-1);
(void)ia_css_device_load_uint32(IRQ_BASE[ID] +
- _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX*sizeof(hrt_data));
+ _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX * sizeof(hrt_data));
}
static inline bool any_irq_channel_enabled(
{
irq_ID_t ID;
- assert(channel_ID != NULL);
+ assert(channel_ID);
for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) {
if (irq_ID < IRQ_N_ID_OFFSET[ID + 1]) {
/* IRQ3_ID */
#include "input_selector_defs.h"
-
#define IRQ_ID_OFFSET 32
#define IRQ0_ID_OFFSET 0
#define IRQ1_ID_OFFSET IRQ_ID_OFFSET
-#define IRQ2_ID_OFFSET (2*IRQ_ID_OFFSET)
-#define IRQ3_ID_OFFSET (3*IRQ_ID_OFFSET)
-#define IRQ_END_OFFSET (4*IRQ_ID_OFFSET)
+#define IRQ2_ID_OFFSET (2 * IRQ_ID_OFFSET)
+#define IRQ3_ID_OFFSET (3 * IRQ_ID_OFFSET)
+#define IRQ_END_OFFSET (4 * IRQ_ID_OFFSET)
#define IRQ0_ID_N_CHANNEL HIVE_GP_DEV_IRQ_NUM_IRQS
#define IRQ1_ID_N_CHANNEL HIVE_IFMT_IRQ_NUM_IRQS
typedef struct virq_info_s virq_info_t;
typedef struct irq_controller_state_s irq_controller_state_t;
-
typedef enum {
virq_gpio_pin_0 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID,
virq_gpio_pin_1 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID,
virq_sp_dmem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID,
virq_mmu_cache_mem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID,
virq_gp_timer_0 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID,
- virq_gp_timer_1 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID,
+ virq_gp_timer_1 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID,
virq_sw_pin_0 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID,
virq_sw_pin_1 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID,
virq_dma = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_DMA_BIT_ID,
virq_isys_csi = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID,
virq_isys_csi_be = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID,
virq_isys_capt0_id_no_sop = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP,
- virq_isys_capt0_id_late_sop= IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP,
+ virq_isys_capt0_id_late_sop = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP,
virq_isys_capt1_id_no_sop = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP,
- virq_isys_capt1_id_late_sop= IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP,
+ virq_isys_capt1_id_late_sop = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP,
virq_isys_capt2_id_no_sop = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP,
- virq_isys_capt2_id_late_sop= IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP,
+ virq_isys_capt2_id_late_sop = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP,
virq_isys_acq_sop_mismatch = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH,
virq_isys_ctrl_capt0 = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_INP_CTRL_CAPA,
virq_isys_ctrl_capt1 = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_INP_CTRL_CAPB,
const hrt_data value)
{
assert(ID < N_IRQ_ID);
- assert(IRQ_BASE[ID] != (hrt_address)-1);
- ia_css_device_store_uint32(IRQ_BASE[ID] + reg*sizeof(hrt_data), value);
+ assert(IRQ_BASE[ID] != (hrt_address) - 1);
+ ia_css_device_store_uint32(IRQ_BASE[ID] + reg * sizeof(hrt_data), value);
return;
}
const unsigned int reg)
{
assert(ID < N_IRQ_ID);
- assert(IRQ_BASE[ID] != (hrt_address)-1);
- return ia_css_device_load_uint32(IRQ_BASE[ID] + reg*sizeof(hrt_data));
+ assert(IRQ_BASE[ID] != (hrt_address) - 1);
+ return ia_css_device_load_uint32(IRQ_BASE[ID] + reg * sizeof(hrt_data));
}
#endif /* __IRQ_PRIVATE_H_INCLUDED__ */
{
hrt_data sc = isp_ctrl_load(ID, ISP_SC_REG);
- assert(state != NULL);
- assert(stall != NULL);
+ assert(state);
+ assert(stall);
#if defined(_hrt_sysmem_ident_address)
/* Patch to avoid compiler unused symbol warning in C_RUN build */
/* ISP functions to control the ISP state from the host, even in crun. */
/* Inspect readiness of an ISP indexed by ID */
-unsigned isp_is_ready(isp_ID_t ID)
+unsigned int isp_is_ready(isp_ID_t ID)
{
- assert (ID < N_ISP_ID);
+ assert(ID < N_ISP_ID);
return isp_ctrl_getbit(ID, ISP_SC_REG, ISP_IDLE_BIT);
}
/* Inspect sleeping of an ISP indexed by ID */
-unsigned isp_is_sleeping(isp_ID_t ID)
+unsigned int isp_is_sleeping(isp_ID_t ID)
{
- assert (ID < N_ISP_ID);
+ assert(ID < N_ISP_ID);
return isp_ctrl_getbit(ID, ISP_SC_REG, ISP_SLEEPING_BIT);
}
/* To be called by the host immediately before starting ISP ID. */
void isp_start(isp_ID_t ID)
{
- assert (ID < N_ISP_ID);
+ assert(ID < N_ISP_ID);
}
/* Wake up ISP ID. */
void isp_wake(isp_ID_t ID)
{
- assert (ID < N_ISP_ID);
+ assert(ID < N_ISP_ID);
isp_ctrl_setbit(ID, ISP_SC_REG, ISP_START_BIT);
hrt_sleep();
}
-
#include <isp2400_support.h>
-#define HIVE_ISP_VMEM_MASK ((1U<<ISP_VMEM_ELEMBITS)-1)
+#define HIVE_ISP_VMEM_MASK ((1U << ISP_VMEM_ELEMBITS) - 1)
typedef struct isp_state_s isp_state_t;
typedef struct isp_stall_s isp_stall_t;
const hrt_data value)
{
assert(ID < N_ISP_ID);
- assert(ISP_CTRL_BASE[ID] != (hrt_address)-1);
+ assert(ISP_CTRL_BASE[ID] != (hrt_address) - 1);
#if !defined(HRT_MEMORY_ACCESS)
- ia_css_device_store_uint32(ISP_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
+ ia_css_device_store_uint32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
#else
- hrt_master_port_store_32(ISP_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
+ hrt_master_port_store_32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
#endif
return;
}
const unsigned int reg)
{
assert(ID < N_ISP_ID);
- assert(ISP_CTRL_BASE[ID] != (hrt_address)-1);
+ assert(ISP_CTRL_BASE[ID] != (hrt_address) - 1);
#if !defined(HRT_MEMORY_ACCESS)
- return ia_css_device_load_uint32(ISP_CTRL_BASE[ID] + reg*sizeof(hrt_data));
+ return ia_css_device_load_uint32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data));
#else
- return hrt_master_port_uload_32(ISP_CTRL_BASE[ID] + reg*sizeof(hrt_data));
+ return hrt_master_port_uload_32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data));
#endif
}
const unsigned int bit)
{
hrt_data val = isp_ctrl_load(ID, reg);
+
return (val & (1UL << bit)) != 0;
}
const unsigned int bit)
{
hrt_data data = isp_ctrl_load(ID, reg);
+
isp_ctrl_store(ID, reg, (data | (1UL << bit)));
return;
}
const unsigned int bit)
{
hrt_data data = isp_ctrl_load(ID, reg);
+
isp_ctrl_store(ID, reg, (data & ~(1UL << bit)));
return;
}
const size_t size)
{
assert(ID < N_ISP_ID);
- assert(ISP_DMEM_BASE[ID] != (hrt_address)-1);
+ assert(ISP_DMEM_BASE[ID] != (hrt_address) - 1);
#if !defined(HRT_MEMORY_ACCESS)
ia_css_device_store(ISP_DMEM_BASE[ID] + addr, data, size);
#else
const size_t size)
{
assert(ID < N_ISP_ID);
- assert(ISP_DMEM_BASE[ID] != (hrt_address)-1);
+ assert(ISP_DMEM_BASE[ID] != (hrt_address) - 1);
#if !defined(HRT_MEMORY_ACCESS)
ia_css_device_load(ISP_DMEM_BASE[ID] + addr, data, size);
#else
const uint32_t data)
{
assert(ID < N_ISP_ID);
- assert(ISP_DMEM_BASE[ID] != (hrt_address)-1);
+ assert(ISP_DMEM_BASE[ID] != (hrt_address) - 1);
(void)ID;
#if !defined(HRT_MEMORY_ACCESS)
ia_css_device_store_uint32(ISP_DMEM_BASE[ID] + addr, data);
const unsigned int addr)
{
assert(ID < N_ISP_ID);
- assert(ISP_DMEM_BASE[ID] != (hrt_address)-1);
+ assert(ISP_DMEM_BASE[ID] != (hrt_address) - 1);
(void)ID;
#if !defined(HRT_MEMORY_ACCESS)
return ia_css_device_load_uint32(ISP_DMEM_BASE[ID] + addr);
}
STORAGE_CLASS_ISP_C uint32_t isp_2w_cat_1w(
- const uint16_t x0,
+ const u16 x0,
const uint16_t x1)
{
- uint32_t out = ((uint32_t)(x1 & HIVE_ISP_VMEM_MASK) << ISP_VMEM_ELEMBITS)
+ u32 out = ((uint32_t)(x1 & HIVE_ISP_VMEM_MASK) << ISP_VMEM_ELEMBITS)
| (x0 & HIVE_ISP_VMEM_MASK);
return out;
}
void mmu_invalidate_cache_all(void)
{
mmu_ID_t mmu_id;
- for (mmu_id = (mmu_ID_t)0;mmu_id < N_MMU_ID; mmu_id++) {
+
+ for (mmu_id = (mmu_ID_t)0; mmu_id < N_MMU_ID; mmu_id++) {
mmu_invalidate_cache(mmu_id);
}
}
-
{
hrt_data sc = sp_ctrl_load(ID, SP_SC_REG);
- assert(state != NULL);
- assert(stall != NULL);
+ assert(state);
+ assert(stall);
state->pc = sp_ctrl_load(ID, SP_PC_REG);
state->status_register = sc;
* deprecated
*/
#define store_sp_int(var, value) \
- sp_dmem_store_uint32(SP0_ID, (unsigned)sp_address_of(var), \
+ sp_dmem_store_uint32(SP0_ID, (unsigned int)sp_address_of(var), \
(uint32_t)(value))
#define store_sp_ptr(var, value) \
- sp_dmem_store_uint32(SP0_ID, (unsigned)sp_address_of(var), \
+ sp_dmem_store_uint32(SP0_ID, (unsigned int)sp_address_of(var), \
(uint32_t)(value))
#define load_sp_uint(var) \
- sp_dmem_load_uint32(SP0_ID, (unsigned)sp_address_of(var))
+ sp_dmem_load_uint32(SP0_ID, (unsigned int)sp_address_of(var))
#define load_sp_array_uint8(array_name, index) \
- sp_dmem_load_uint8(SP0_ID, (unsigned)sp_address_of(array_name) + \
- (index)*sizeof(uint8_t))
+ sp_dmem_load_uint8(SP0_ID, (unsigned int)sp_address_of(array_name) + \
+ (index) * sizeof(uint8_t))
#define load_sp_array_uint16(array_name, index) \
- sp_dmem_load_uint16(SP0_ID, (unsigned)sp_address_of(array_name) + \
- (index)*sizeof(uint16_t))
+ sp_dmem_load_uint16(SP0_ID, (unsigned int)sp_address_of(array_name) + \
+ (index) * sizeof(uint16_t))
#define load_sp_array_uint(array_name, index) \
- sp_dmem_load_uint32(SP0_ID, (unsigned)sp_address_of(array_name) + \
- (index)*sizeof(uint32_t))
+ sp_dmem_load_uint32(SP0_ID, (unsigned int)sp_address_of(array_name) + \
+ (index) * sizeof(uint32_t))
#define store_sp_var(var, data, bytes) \
- sp_dmem_store(SP0_ID, (unsigned)sp_address_of(var), data, bytes)
+ sp_dmem_store(SP0_ID, (unsigned int)sp_address_of(var), data, bytes)
#define store_sp_array_uint8(array_name, index, value) \
- sp_dmem_store_uint8(SP0_ID, (unsigned)sp_address_of(array_name) + \
- (index)*sizeof(uint8_t), value)
+ sp_dmem_store_uint8(SP0_ID, (unsigned int)sp_address_of(array_name) + \
+ (index) * sizeof(uint8_t), value)
#define store_sp_array_uint16(array_name, index, value) \
- sp_dmem_store_uint16(SP0_ID, (unsigned)sp_address_of(array_name) + \
- (index)*sizeof(uint16_t), value)
+ sp_dmem_store_uint16(SP0_ID, (unsigned int)sp_address_of(array_name) + \
+ (index) * sizeof(uint16_t), value)
#define store_sp_array_uint(array_name, index, value) \
- sp_dmem_store_uint32(SP0_ID, (unsigned)sp_address_of(array_name) + \
- (index)*sizeof(uint32_t), value)
+ sp_dmem_store_uint32(SP0_ID, (unsigned int)sp_address_of(array_name) + \
+ (index) * sizeof(uint32_t), value)
#define store_sp_var_with_offset(var, offset, data, bytes) \
- sp_dmem_store(SP0_ID, (unsigned)sp_address_of(var) + \
+ sp_dmem_store(SP0_ID, (unsigned int)sp_address_of(var) + \
offset, data, bytes)
#define load_sp_var(var, data, bytes) \
- sp_dmem_load(SP0_ID, (unsigned)sp_address_of(var), data, bytes)
+ sp_dmem_load(SP0_ID, (unsigned int)sp_address_of(var), data, bytes)
#define load_sp_var_with_offset(var, offset, data, bytes) \
- sp_dmem_load(SP0_ID, (unsigned)sp_address_of(var) + offset, \
+ sp_dmem_load(SP0_ID, (unsigned int)sp_address_of(var) + offset, \
data, bytes)
#endif /* __SP_LOCAL_H_INCLUDED__ */
{
assert(ID < N_SP_ID);
assert(SP_CTRL_BASE[ID] != (hrt_address)-1);
- ia_css_device_store_uint32(SP_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
+ ia_css_device_store_uint32(SP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
return;
}
{
assert(ID < N_SP_ID);
assert(SP_CTRL_BASE[ID] != (hrt_address)-1);
- return ia_css_device_load_uint32(SP_CTRL_BASE[ID] + reg*sizeof(hrt_data));
+ return ia_css_device_load_uint32(SP_CTRL_BASE[ID] + reg * sizeof(hrt_data));
}
STORAGE_CLASS_SP_C bool sp_ctrl_getbit(
const unsigned int bit)
{
hrt_data val = sp_ctrl_load(ID, reg);
+
return (val & (1UL << bit)) != 0;
}
const unsigned int bit)
{
hrt_data data = sp_ctrl_load(ID, reg);
+
sp_ctrl_store(ID, reg, (data | (1UL << bit)));
return;
}
const unsigned int bit)
{
hrt_data data = sp_ctrl_load(ID, reg);
+
sp_ctrl_store(ID, reg, (data & ~(1UL << bit)));
return;
}
/*
* Cell specific address maps
*/
-#if HRT_ADDRESS_WIDTH==64
+#if HRT_ADDRESS_WIDTH == 64
#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
(hrt_address)0x00000000000B0000ULL};
/* MMU */
-#if defined (IS_ISP_2400_MAMOIADA_SYSTEM) || defined (IS_ISP_2401_MAMOIADA_SYSTEM)
+#if defined(IS_ISP_2400_MAMOIADA_SYSTEM) || defined(IS_ISP_2401_MAMOIADA_SYSTEM)
/*
* MMU0_ID: The data MMU
* MMU1_ID: The icache MMU
static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
(hrt_address)0x0000000000000100ULL};
-
/* INPUT_FORMATTER */
static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
(hrt_address)0x0000000000030000ULL,
static const hrt_address RX_BASE[N_RX_ID] = {
(hrt_address)0x0000000000080100ULL};
-#elif HRT_ADDRESS_WIDTH==32
+#elif HRT_ADDRESS_WIDTH == 32
#define GP_FIFO_BASE ((hrt_address)0x00090104) /* This is NOT a base address */
(hrt_address)0x000B0000UL};
/* MMU */
-#if defined (IS_ISP_2400_MAMOIADA_SYSTEM) || defined (IS_ISP_2401_MAMOIADA_SYSTEM)
+#if defined(IS_ISP_2400_MAMOIADA_SYSTEM) || defined(IS_ISP_2401_MAMOIADA_SYSTEM)
/*
* MMU0_ID: The data MMU
* MMU1_ID: The icache MMU
static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
(hrt_address)0x00000100UL};
-
/* INPUT_FORMATTER */
static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
(hrt_address)0x00030000UL,
OP___assert(SP_DMEM_BASE[SP_ID] != (hrt_address)-1);
timed_ctrl_snd_commnd(ID, mask, condition, counter,
- SP_DMEM_BASE[SP_ID]+offset, value);
+ SP_DMEM_BASE[SP_ID] + offset, value);
}
void timed_ctrl_snd_gpio_commnd(
OP___assert(GPIO_BASE[GPIO_ID] != (hrt_address)-1);
timed_ctrl_snd_commnd(ID, mask, condition, counter,
- GPIO_BASE[GPIO_ID]+offset, value);
+ GPIO_BASE[GPIO_ID] + offset, value);
}
const hrt_data value)
{
OP___assert(ID < N_TIMED_CTRL_ID);
-OP___assert(TIMED_CTRL_BASE[ID] != (hrt_address)-1);
- ia_css_device_store_uint32(TIMED_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
+OP___assert(TIMED_CTRL_BASE[ID] != (hrt_address) - 1);
+ ia_css_device_store_uint32(TIMED_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
}
#endif /* __GP_DEVICE_PRIVATE_H_INCLUDED__ */
#include "assert_support.h"
-
STORAGE_CLASS_ISP_C void isp_vamem_store(
const vamem_ID_t ID,
vamem_data_t *addr,
const size_t size) /* in vamem_data_t */
{
assert(ID < N_VAMEM_ID);
- assert(ISP_VAMEM_BASE[ID] != (hrt_address)-1);
- hrt_master_port_store(ISP_VAMEM_BASE[ID] + (unsigned)addr, data, size * sizeof(vamem_data_t));
+ assert(ISP_VAMEM_BASE[ID] != (hrt_address) - 1);
+ hrt_master_port_store(ISP_VAMEM_BASE[ID] + (unsigned int)addr, data, size * sizeof(vamem_data_t));
}
-
#endif /* __VAMEM_PRIVATE_H_INCLUDED__ */
#include "platform_support.h" /* hrt_sleep() */
typedef unsigned long long hive_uedge;
-typedef hive_uedge *hive_wide;
+typedef hive_uedge * hive_wide;
/* Copied from SDK: sim_semantics.c */
/* subword bits move like this: MSB[____xxxx____]LSB -> MSB[00000000xxxx]LSB */
-#define SUBWORD(w, start, end) (((w) & (((1ULL << ((end)-1))-1) << 1 | 1)) >> (start))
+#define SUBWORD(w, start, end) (((w) & (((1ULL << ((end) - 1)) - 1) << 1 | 1)) >> (start))
/* inverse subword bits move like this: MSB[xxxx____xxxx]LSB -> MSB[xxxx0000xxxx]LSB */
-#define INV_SUBWORD(w, start, end) ((w) & (~(((1ULL << ((end)-1))-1) << 1 | 1) | ((1ULL << (start))-1)) )
+#define INV_SUBWORD(w, start, end) ((w) & (~(((1ULL << ((end) - 1)) - 1) << 1 | 1) | ((1ULL << (start)) - 1)))
-#define uedge_bits (8*sizeof(hive_uedge))
+#define uedge_bits (8 * sizeof(hive_uedge))
#define move_lower_bits(target, target_bit, src, src_bit) move_subword(target, target_bit, src, 0, src_bit)
#define move_upper_bits(target, target_bit, src, src_bit) move_subword(target, target_bit, src, src_bit, uedge_bits)
#define move_word(target, target_bit, src) move_subword(target, target_bit, src, 0, uedge_bits)
static void
-move_subword (
+move_subword(
hive_uedge *target,
- unsigned target_bit,
+ unsigned int target_bit,
hive_uedge src,
- unsigned src_start,
- unsigned src_end)
+ unsigned int src_start,
+ unsigned int src_end)
{
unsigned int start_elem = target_bit / uedge_bits;
unsigned int start_bit = target_bit % uedge_bits;
- unsigned subword_width = src_end - src_start;
+ unsigned int subword_width = src_end - src_start;
hive_uedge src_subword = SUBWORD(src, src_start, src_end);
if (subword_width + start_bit > uedge_bits) { /* overlap */
hive_uedge old_val1;
hive_uedge old_val0 = INV_SUBWORD(target[start_elem], start_bit, uedge_bits);
+
target[start_elem] = old_val0 | (src_subword << start_bit);
- old_val1 = INV_SUBWORD(target[start_elem+1], 0, subword_width + start_bit - uedge_bits);
- target[start_elem+1] = old_val1 | (src_subword >> ( uedge_bits - start_bit));
+ old_val1 = INV_SUBWORD(target[start_elem + 1], 0, subword_width + start_bit - uedge_bits);
+ target[start_elem + 1] = old_val1 | (src_subword >> (uedge_bits - start_bit));
} else {
hive_uedge old_val = INV_SUBWORD(target[start_elem], start_bit, start_bit + subword_width);
+
target[start_elem] = old_val | (src_subword << start_bit);
}
}
/* general case: handles edge spanning cases (includes >64bit elements) */
unsigned int bits_written = 0;
unsigned int i;
+
move_upper_bits(elem, bits_written, vector[start_elem], start_bit);
bits_written += (64 - start_bit);
- for(i = start_elem+1; i < end_elem; i++) {
+ for (i = start_elem + 1; i < end_elem; i++) {
move_word(elem, bits_written, vector[i]);
bits_written += uedge_bits;
}
- move_lower_bits(elem, bits_written , vector[end_elem], end_bit);
+ move_lower_bits(elem, bits_written, vector[end_elem], end_bit);
}
}
if (elem_bits == uedge_bits) {
vector[start_elem] = elem[0];
} else if (elem_bits > uedge_bits) {
- unsigned bits_to_write = elem_bits;
- unsigned start_bit = elem_bits * index;
- unsigned i = 0;
- for(; bits_to_write > uedge_bits; bits_to_write -= uedge_bits, i++, start_bit += uedge_bits) {
+ unsigned int bits_to_write = elem_bits;
+ unsigned int start_bit = elem_bits * index;
+ unsigned int i = 0;
+
+ for (; bits_to_write > uedge_bits; bits_to_write -= uedge_bits, i++, start_bit += uedge_bits) {
move_word(vector, start_bit, elem[i]);
}
move_lower_bits(vector, start_bit, elem[i], bits_to_write);
}
}
-static void load_vector (
+static void load_vector(
const isp_ID_t ID,
t_vmem_elem *to,
const t_vmem_elem *from)
{
- unsigned i;
+ unsigned int i;
hive_uedge *data;
- unsigned size = sizeof(short)*ISP_NWAY;
- VMEM_ARRAY(v, 2*ISP_NWAY); /* Need 2 vectors to work around vmem hss bug */
- assert(ISP_BAMEM_BASE[ID] != (hrt_address)-1);
+ unsigned int size = sizeof(short) * ISP_NWAY;
+
+ VMEM_ARRAY(v, 2 * ISP_NWAY); /* Need 2 vectors to work around vmem hss bug */
+ assert(ISP_BAMEM_BASE[ID] != (hrt_address) - 1);
#if !defined(HRT_MEMORY_ACCESS)
ia_css_device_load(ISP_BAMEM_BASE[ID] + (unsigned long)from, &v[0][0], size);
#else
data = (hive_uedge *)v;
for (i = 0; i < ISP_NWAY; i++) {
hive_uedge elem = 0;
+
hive_sim_wide_unpack(data, &elem, ISP_VEC_ELEMBITS, i);
to[i] = elem;
}
hrt_sleep(); /* Spend at least 1 cycles per vector */
}
-static void store_vector (
+static void store_vector(
const isp_ID_t ID,
t_vmem_elem *to,
const t_vmem_elem *from)
{
- unsigned i;
- unsigned size = sizeof(short)*ISP_NWAY;
- VMEM_ARRAY(v, 2*ISP_NWAY); /* Need 2 vectors to work around vmem hss bug */
+ unsigned int i;
+ unsigned int size = sizeof(short) * ISP_NWAY;
+
+ VMEM_ARRAY(v, 2 * ISP_NWAY); /* Need 2 vectors to work around vmem hss bug */
//load_vector (&v[1][0], &to[ISP_NWAY]); /* Fetch the next vector, since it will be overwritten. */
hive_uedge *data = (hive_uedge *)v;
+
for (i = 0; i < ISP_NWAY; i++) {
hive_sim_wide_pack(data, (hive_wide)&from[i], ISP_VEC_ELEMBITS, i);
}
- assert(ISP_BAMEM_BASE[ID] != (hrt_address)-1);
+ assert(ISP_BAMEM_BASE[ID] != (hrt_address) - 1);
#if !defined(HRT_MEMORY_ACCESS)
ia_css_device_store(ISP_BAMEM_BASE[ID] + (unsigned long)to, &v, size);
#else
const isp_ID_t ID,
const t_vmem_elem *from,
t_vmem_elem *to,
- unsigned elems) /* In t_vmem_elem */
+ unsigned int elems) /* In t_vmem_elem */
{
- unsigned c;
+ unsigned int c;
const t_vmem_elem *vp = from;
+
assert(ID < N_ISP_ID);
assert((unsigned long)from % ISP_VEC_ALIGN == 0);
assert(elems % ISP_NWAY == 0);
for (c = 0; c < elems; c += ISP_NWAY) {
load_vector(ID, &to[c], vp);
- vp = (t_vmem_elem *)((char*)vp + ISP_VEC_ALIGN);
+ vp = (t_vmem_elem *)((char *)vp + ISP_VEC_ALIGN);
}
}
const isp_ID_t ID,
t_vmem_elem *to,
const t_vmem_elem *from,
- unsigned elems) /* In t_vmem_elem */
+ unsigned int elems) /* In t_vmem_elem */
{
- unsigned c;
+ unsigned int c;
t_vmem_elem *vp = to;
+
assert(ID < N_ISP_ID);
assert((unsigned long)to % ISP_VEC_ALIGN == 0);
assert(elems % ISP_NWAY == 0);
for (c = 0; c < elems; c += ISP_NWAY) {
- store_vector (ID, vp, &from[c]);
- vp = (t_vmem_elem *)((char*)vp + ISP_VEC_ALIGN);
+ store_vector(ID, vp, &from[c]);
+ vp = (t_vmem_elem *)((char *)vp + ISP_VEC_ALIGN);
}
}
-void isp_vmem_2d_load (
+void isp_vmem_2d_load(
const isp_ID_t ID,
const t_vmem_elem *from,
t_vmem_elem *to,
- unsigned height,
- unsigned width,
- unsigned stride_to, /* In t_vmem_elem */
+ unsigned int height,
+ unsigned int width,
+ unsigned int stride_to, /* In t_vmem_elem */
+
unsigned stride_from /* In t_vmem_elem */)
{
- unsigned h;
+ unsigned int h;
assert(ID < N_ISP_ID);
assert((unsigned long)from % ISP_VEC_ALIGN == 0);
assert(width % ISP_NWAY == 0);
assert(stride_from % ISP_NWAY == 0);
for (h = 0; h < height; h++) {
- unsigned c;
+ unsigned int c;
const t_vmem_elem *vp = from;
+
for (c = 0; c < width; c += ISP_NWAY) {
- load_vector(ID, &to[stride_to*h + c], vp);
- vp = (t_vmem_elem *)((char*)vp + ISP_VEC_ALIGN);
+ load_vector(ID, &to[stride_to * h + c], vp);
+ vp = (t_vmem_elem *)((char *)vp + ISP_VEC_ALIGN);
}
- from = (const t_vmem_elem *)((const char *)from + stride_from/ISP_NWAY*ISP_VEC_ALIGN);
+ from = (const t_vmem_elem *)((const char *)from + stride_from / ISP_NWAY * ISP_VEC_ALIGN);
}
}
-void isp_vmem_2d_store (
+void isp_vmem_2d_store(
const isp_ID_t ID,
t_vmem_elem *to,
const t_vmem_elem *from,
- unsigned height,
- unsigned width,
- unsigned stride_to, /* In t_vmem_elem */
+ unsigned int height,
+ unsigned int width,
+ unsigned int stride_to, /* In t_vmem_elem */
+
unsigned stride_from /* In t_vmem_elem */)
{
- unsigned h;
+ unsigned int h;
assert(ID < N_ISP_ID);
assert((unsigned long)to % ISP_VEC_ALIGN == 0);
assert(width % ISP_NWAY == 0);
assert(stride_to % ISP_NWAY == 0);
for (h = 0; h < height; h++) {
- unsigned c;
+ unsigned int c;
t_vmem_elem *vp = to;
+
for (c = 0; c < width; c += ISP_NWAY) {
- store_vector (ID, vp, &from[stride_from*h + c]);
- vp = (t_vmem_elem *)((char*)vp + ISP_VEC_ALIGN);
+ store_vector(ID, vp, &from[stride_from * h + c]);
+ vp = (t_vmem_elem *)((char *)vp + ISP_VEC_ALIGN);
}
- to = (t_vmem_elem *)((char *)to + stride_to/ISP_NWAY*ISP_VEC_ALIGN);
+ to = (t_vmem_elem *)((char *)to + stride_to / ISP_NWAY * ISP_VEC_ALIGN);
}
}
#include "type_support.h"
#include "vmem_global.h"
-typedef uint16_t t_vmem_elem;
+typedef u16 t_vmem_elem;
-#define VMEM_ARRAY(x,s) t_vmem_elem x[s/ISP_NWAY][ISP_NWAY]
+#define VMEM_ARRAY(x, s) t_vmem_elem x[s / ISP_NWAY][ISP_NWAY]
void isp_vmem_load(
const isp_ID_t ID,
const t_vmem_elem *from,
t_vmem_elem *to,
- unsigned elems); /* In t_vmem_elem */
+ unsigned int elems); /* In t_vmem_elem */
void isp_vmem_store(
const isp_ID_t ID,
t_vmem_elem *to,
const t_vmem_elem *from,
- unsigned elems); /* In t_vmem_elem */
+ unsigned int elems); /* In t_vmem_elem */
-void isp_vmem_2d_load (
+void isp_vmem_2d_load(
const isp_ID_t ID,
const t_vmem_elem *from,
t_vmem_elem *to,
- unsigned height,
- unsigned width,
- unsigned stride_to, /* In t_vmem_elem */
+ unsigned int height,
+ unsigned int width,
+ unsigned int stride_to, /* In t_vmem_elem */
+
unsigned stride_from /* In t_vmem_elem */);
-void isp_vmem_2d_store (
+void isp_vmem_2d_store(
const isp_ID_t ID,
t_vmem_elem *to,
const t_vmem_elem *from,
- unsigned height,
- unsigned width,
- unsigned stride_to, /* In t_vmem_elem */
+ unsigned int height,
+ unsigned int width,
+ unsigned int stride_to, /* In t_vmem_elem */
+
unsigned stride_from /* In t_vmem_elem */);
#endif /* __VMEM_LOCAL_H_INCLUDED__ */
#define HIVE_SWITCH_M_FSYNC 0x00000007
#define HIVE_SWITCH_ENCODE_FSYNC(x) \
- (1U<<(((x)-1)&HIVE_SWITCH_M_CHANNELS))
+ (1U << (((x) - 1) & HIVE_SWITCH_M_CHANNELS))
#define _HIVE_INPUT_SWITCH_GET_LUT_FIELD(reg, bit_index) \
(((reg) >> (bit_index)) & HIVE_SWITCH_M_SWITCH_CODE)
#define _HIVE_INPUT_SWITCH_SET_LUT_FIELD(reg, bit_index, val) \
- (((reg) & ~(HIVE_SWITCH_M_SWITCH_CODE<<(bit_index))) | (((hrt_data)(val)&HIVE_SWITCH_M_SWITCH_CODE)<<(bit_index)))
+ (((reg) & ~(HIVE_SWITCH_M_SWITCH_CODE << (bit_index))) | (((hrt_data)(val) & HIVE_SWITCH_M_SWITCH_CODE) << (bit_index)))
#define _HIVE_INPUT_SWITCH_GET_FSYNC_FIELD(reg, bit_index) \
(((reg) >> (bit_index)) & HIVE_SWITCH_M_FSYNC)
#define _HIVE_INPUT_SWITCH_SET_FSYNC_FIELD(reg, bit_index, val) \
- (((reg) & ~(HIVE_SWITCH_M_FSYNC<<(bit_index))) | (((hrt_data)(val)&HIVE_SWITCH_M_FSYNC)<<(bit_index)))
+ (((reg) & ~(HIVE_SWITCH_M_FSYNC << (bit_index))) | (((hrt_data)(val) & HIVE_SWITCH_M_FSYNC) << (bit_index)))
typedef struct input_formatter_cfg_s input_formatter_cfg_t;
* This data structure is shared between host and SP
*/
struct input_formatter_cfg_s {
- uint32_t start_line;
- uint32_t start_column;
- uint32_t left_padding;
- uint32_t cropped_height;
- uint32_t cropped_width;
- uint32_t deinterleaving;
- uint32_t buf_vecs;
- uint32_t buf_start_index;
- uint32_t buf_increment;
- uint32_t buf_eol_offset;
- uint32_t is_yuv420_format;
- uint32_t block_no_reqs;
+ u32 start_line;
+ u32 start_column;
+ u32 left_padding;
+ u32 cropped_height;
+ u32 cropped_width;
+ u32 deinterleaving;
+ u32 buf_vecs;
+ u32 buf_start_index;
+ u32 buf_increment;
+ u32 buf_eol_offset;
+ u32 is_yuv420_format;
+ u32 block_no_reqs;
};
extern const hrt_address HIVE_IF_SRST_ADDRESS[N_INPUT_FORMATTER_ID];
extern const hrt_data HIVE_IF_SRST_MASK[N_INPUT_FORMATTER_ID];
-extern const uint8_t HIVE_IF_SWITCH_CODE[N_INPUT_FORMATTER_ID];
+extern const u8 HIVE_IF_SWITCH_CODE[N_INPUT_FORMATTER_ID];
#endif /* __INPUT_FORMATTER_GLOBAL_H_INCLUDED__ */
//AM: Use previous define for this.
//MIPI allows upto 4 channels.
-#define N_CHANNELS (4)
+#define N_CHANNELS (4)
// 12KB = 256bit x 384 words
#define IB_CAPACITY_IN_WORDS (384)
typedef enum {
INPUT_SYSTEM_DISCARD_ALL = 0,
INPUT_SYSTEM_CSI_BACKEND = 1,
- INPUT_SYSTEM_INPUT_BUFFER = 2,
+ INPUT_SYSTEM_INPUT_BUFFER = 2,
INPUT_SYSTEM_MULTICAST = 3,
N_INPUT_SYSTEM_CONNECTION
} input_system_connection_t;
/* MW: uint16_t should be sufficient */
struct input_system_cfg_s {
- uint32_t no_side_band;
- uint32_t fmt_type;
- uint32_t ch_id;
- uint32_t input_mode;
+ u32 no_side_band;
+ u32 fmt_type;
+ u32 ch_id;
+ u32 input_mode;
};
struct sync_generator_cfg_s {
- uint32_t width;
- uint32_t height;
- uint32_t hblank_cycles;
- uint32_t vblank_cycles;
+ u32 width;
+ u32 height;
+ u32 hblank_cycles;
+ u32 vblank_cycles;
};
/* MW: tpg & prbs are exclusive */
struct tpg_cfg_s {
- uint32_t x_mask;
- uint32_t y_mask;
- uint32_t x_delta;
- uint32_t y_delta;
- uint32_t xy_mask;
+ u32 x_mask;
+ u32 y_mask;
+ u32 x_delta;
+ u32 y_delta;
+ u32 xy_mask;
sync_generator_cfg_t sync_gen_cfg;
};
struct prbs_cfg_s {
- uint32_t seed;
+ u32 seed;
sync_generator_cfg_t sync_gen_cfg;
};
//typedef struct input_system_cfg_s input_system_cfg_t;
struct ib_buffer_s {
- uint32_t mem_reg_size;
- uint32_t nof_mem_regs;
- uint32_t mem_reg_addr;
+ u32 mem_reg_size;
+ u32 nof_mem_regs;
+ u32 mem_reg_addr;
};
typedef struct ib_buffer_s ib_buffer_t;
struct csi_cfg_s {
- uint32_t csi_port;
+ u32 csi_port;
buffering_mode_t buffering_mode;
ib_buffer_t csi_buffer;
ib_buffer_t acquisition_buffer;
- uint32_t nof_xmem_buffers;
+ u32 nof_xmem_buffers;
};
typedef struct csi_cfg_s csi_cfg_t;
INPUT_SYSTEM_CFG_FLAG_CONFLICT = 1U << 3 // To mark a conflicting configuration.
} input_system_cfg_flag_t;
-typedef uint32_t input_system_config_flags_t;
+typedef u32 input_system_config_flags_t;
#endif /* __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ */
#include <system_types.h>
-#if defined (HAS_ISP_2401_MAMOIADA)
+#if defined(HAS_ISP_2401_MAMOIADA)
#define IS_ISP_2401_MAMOIADA
#include "isp2401_mamoiada_params.h"
-#elif defined (HAS_ISP_2400_MAMOIADA)
+#elif defined(HAS_ISP_2400_MAMOIADA)
#define IS_ISP_2400_MAMOIADA
#include "isp2400_mamoiada_params.h"
#ifdef ISP2401
#ifdef PIPE_GENERATION
#define PIPEMEM(x) MEM(x)
-#define ISP_NWAY (1<<ISP_NWAY_LOG2)
+#define ISP_NWAY BIT(ISP_NWAY_LOG2)
#else
#define PIPEMEM(x)
#endif
#endif
/* The number of data bytes in a vector disregarding the reduced precision */
-#define ISP_VEC_BYTES (ISP_VEC_NELEMS*sizeof(uint16_t))
+#define ISP_VEC_BYTES (ISP_VEC_NELEMS * sizeof(uint16_t))
/* ISP SC Registers */
#define ISP_SC_REG 0x00
//#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property*/
#define HRT_DATA_WIDTH 32
-#define SIZEOF_HRT_REG (HRT_DATA_WIDTH>>3)
-#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH/8)
+#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
+#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8)
/* The main bus connecting all devices */
#define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH
/* per-frame parameter handling support */
#define SH_CSS_ENABLE_PER_FRAME_PARAMS
-typedef uint32_t hrt_bus_align_t;
+typedef u32 hrt_bus_align_t;
/*
* Enumerate the devices, device access through the API is by ID, through the DLI by address
N_SP_ID
} sp_ID_t;
-#if defined (IS_ISP_2401_MAMOIADA_SYSTEM)
+#if defined(IS_ISP_2401_MAMOIADA_SYSTEM)
typedef enum {
MMU0_ID = 0,
MMU1_ID,
N_MMU_ID
} mmu_ID_t;
-#elif defined (IS_ISP_2400_MAMOIADA_SYSTEM)
+#elif defined(IS_ISP_2400_MAMOIADA_SYSTEM)
typedef enum {
MMU0_ID = 0,
MMU1_ID,
IA_CSS_DDR,
N_IA_CSS_MEMORIES
};
+
#define IA_CSS_NUM_MEMORIES 9
/* For driver compatibility */
#define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES
#define HIVE_TIMED_CTRL_CSI_EOF_BIT_ID 22
#define HIVE_TIMED_CTRL_IRQ_IS_STREAMING_MONITOR_BIT_ID 23
-
-
#endif /* __TIMED_CTRL_GLOBAL_H_INCLUDED__ */
/* (log) stepsize of linear interpolation */
#define VAMEM_INTERP_STEP_LOG2 4
-#define VAMEM_INTERP_STEP (1<<VAMEM_INTERP_STEP_LOG2)
+#define VAMEM_INTERP_STEP BIT(VAMEM_INTERP_STEP_LOG2)
/* (physical) size of the tables */
-#define VAMEM_TABLE_UNIT_SIZE ((1<<(ISP_VAMEM_ADDRESS_BITS-VAMEM_INTERP_STEP_LOG2)) + 1)
+#define VAMEM_TABLE_UNIT_SIZE ((1 << (ISP_VAMEM_ADDRESS_BITS - VAMEM_INTERP_STEP_LOG2)) + 1)
/* (logical) size of the tables */
-#define VAMEM_TABLE_UNIT_STEP ((VAMEM_TABLE_UNIT_SIZE-1)<<1)
+#define VAMEM_TABLE_UNIT_STEP ((VAMEM_TABLE_UNIT_SIZE - 1) << 1)
/* Number of tables */
-#define VAMEM_TABLE_UNIT_COUNT (ISP_VAMEM_DEPTH/VAMEM_TABLE_UNIT_STEP)
+#define VAMEM_TABLE_UNIT_COUNT (ISP_VAMEM_DEPTH / VAMEM_TABLE_UNIT_STEP)
-typedef uint16_t vamem_data_t;
+typedef u16 vamem_data_t;
#endif /* __VAMEM_GLOBAL_H_INCLUDED__ */
#define VMEM_ALIGN ISP_VMEM_ALIGN
#ifndef PIPE_GENERATION
-typedef tvector *pvector;
+typedef tvector * pvector;
#endif
#endif /* __VMEM_GLOBAL_H_INCLUDED__ */
#ifndef __ASSERT_SUPPORT_H_INCLUDED__
#define __ASSERT_SUPPORT_H_INCLUDED__
-
/**
* The following macro can help to test the size of a struct at compile
* time rather than at run-time. It does not work for all compilers; see
* Not all compilers will trigger an error with this macro; use a search engine to search for
* BUILD_BUG_ON to find other methods.
*/
-#define COMPILATION_ERROR_IF(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
+#define COMPILATION_ERROR_IF(condition) ((void)sizeof(char[1 - 2 * !!(condition)]))
/* Compile time assertion */
#ifndef CT_ASSERT
-#define CT_ASSERT(cnd) ((void)sizeof(char[(cnd)?1:-1]))
+#define CT_ASSERT(cnd) ((void)sizeof(char[(cnd) ? 1 : -1]))
#endif /* CT_ASSERT */
#ifdef NDEBUG
* The implementation for the pipe generation tool is in see support.isp.h */
#define OP___assert(cnd) assert(cnd)
-static inline void compile_time_assert (unsigned cond)
+static inline void compile_time_assert(unsigned int cond)
{
/* Call undefined function if cond is false */
- extern void _compile_time_assert (void);
+ void _compile_time_assert(void);
if (!cond) _compile_time_assert();
}
#endif /* PIPE_GENERATION */
#define bitop_clearbit(a, b) ((a) &= ~(1UL << (b)))
#endif /* __BITOP_SUPPORT_H_INCLUDED__ */
-
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "csi_rx_local.h"
*
*/
-
#include "system_local.h"
#include "debug_local.h"
#ifndef __INLINE_DEBUG__
#define STORAGE_CLASS_DEBUG_H extern
-#define STORAGE_CLASS_DEBUG_C
+#define STORAGE_CLASS_DEBUG_C
#include "debug_public.h"
#else /* __INLINE_DEBUG__ */
#define STORAGE_CLASS_DEBUG_H static inline
\return none,
*/
-extern void device_set_base_address(
+void device_set_base_address(
const sys_address base_addr);
-
/*! Get the (sub)system base address
\return base_address,
*/
-extern sys_address device_get_base_address(void);
+sys_address device_get_base_address(void);
/*! Read an 8-bit value from a device register or memory in the device
\return device[addr]
*/
-extern uint8_t ia_css_device_load_uint8(
+uint8_t ia_css_device_load_uint8(
const hrt_address addr);
/*! Read a 16-bit value from a device register or memory in the device
\return device[addr]
*/
-extern uint16_t ia_css_device_load_uint16(
+uint16_t ia_css_device_load_uint16(
const hrt_address addr);
/*! Read a 32-bit value from a device register or memory in the device
\return device[addr]
*/
-extern uint32_t ia_css_device_load_uint32(
+uint32_t ia_css_device_load_uint32(
const hrt_address addr);
/*! Read a 64-bit value from a device register or memory in the device
\return device[addr]
*/
-extern uint64_t ia_css_device_load_uint64(
+uint64_t ia_css_device_load_uint64(
const hrt_address addr);
/*! Write an 8-bit value to a device register or memory in the device
\return none, device[addr] = value
*/
-extern void ia_css_device_store_uint8(
+void ia_css_device_store_uint8(
const hrt_address addr,
const uint8_t data);
\return none, device[addr] = value
*/
-extern void ia_css_device_store_uint16(
+void ia_css_device_store_uint16(
const hrt_address addr,
const uint16_t data);
\return none, device[addr] = value
*/
-extern void ia_css_device_store_uint32(
+void ia_css_device_store_uint32(
const hrt_address addr,
const uint32_t data);
\return none, device[addr] = value
*/
-extern void ia_css_device_store_uint64(
+void ia_css_device_store_uint64(
const hrt_address addr,
const uint64_t data);
\return none
*/
-extern void ia_css_device_load(
+void ia_css_device_load(
const hrt_address addr,
void *data,
const size_t size);
\return none
*/
-extern void ia_css_device_store(
+void ia_css_device_store(
const hrt_address addr,
const void *data,
const size_t size);
*
*/
-
#include "system_local.h"
#include "dma_local.h"
#ifndef __INLINE_DMA__
#define STORAGE_CLASS_DMA_H extern
-#define STORAGE_CLASS_DMA_C
+#define STORAGE_CLASS_DMA_C
#include "dma_public.h"
#else /* __INLINE_DMA__ */
#define STORAGE_CLASS_DMA_H static inline
#define ENOTSUP 252
#define ENOBUFS 233
-
#elif defined(__KERNEL__)
#include <linux/errno.h>
/*
#endif
-#define verifexit(cond,error_tag) \
+#define verifexit(cond, error_tag) \
do { \
- if (!(cond)){ \
+ if (!(cond)) { \
goto EXIT; \
} \
-} while(0)
+} while (0)
#define verifjmpexit(cond) \
do { \
- if (!(cond)){ \
+ if (!(cond)) { \
goto EXIT; \
} \
-} while(0)
+} while (0)
#endif /* __ERROR_SUPPORT_H_INCLUDED__ */
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "event_fifo_local.h"
#ifndef __INLINE_EVENT__
#define STORAGE_CLASS_EVENT_H extern
-#define STORAGE_CLASS_EVENT_C
+#define STORAGE_CLASS_EVENT_C
#include "event_fifo_public.h"
#else /* __INLINE_EVENT__ */
#define STORAGE_CLASS_EVENT_H static inline
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "fifo_monitor_local.h"
#ifndef __INLINE_FIFO_MONITOR__
#define STORAGE_CLASS_FIFO_MONITOR_H extern
-#define STORAGE_CLASS_FIFO_MONITOR_C
+#define STORAGE_CLASS_FIFO_MONITOR_C
#include "fifo_monitor_public.h"
#else /* __INLINE_FIFO_MONITOR__ */
#define STORAGE_CLASS_FIFO_MONITOR_H static inline
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "gdc_local.h"
#ifndef __INLINE_GDC__
#define STORAGE_CLASS_GDC_H extern
-#define STORAGE_CLASS_GDC_C
+#define STORAGE_CLASS_GDC_C
#include "gdc_public.h"
#else /* __INLINE_GDC__ */
#define STORAGE_CLASS_GDC_H static inline
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "gp_device_local.h"
#ifndef __INLINE_GP_DEVICE__
#define STORAGE_CLASS_GP_DEVICE_H extern
-#define STORAGE_CLASS_GP_DEVICE_C
+#define STORAGE_CLASS_GP_DEVICE_C
#include "gp_device_public.h"
#else /* __INLINE_GP_DEVICE__ */
#define STORAGE_CLASS_GP_DEVICE_H static inline
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h" /*GP_TIMER_BASE address */
#include "gp_timer_local.h" /*GP_TIMER register offsets */
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "gpio_local.h"
#ifndef __INLINE_GPIO__
#define STORAGE_CLASS_GPIO_H extern
-#define STORAGE_CLASS_GPIO_C
+#define STORAGE_CLASS_GPIO_C
#include "gpio_public.h"
#else /* __INLINE_GPIO__ */
#define STORAGE_CLASS_GPIO_H static inline
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "hmem_local.h"
#ifndef __INLINE_HMEM__
#define STORAGE_CLASS_HMEM_H extern
-#define STORAGE_CLASS_HMEM_C
+#define STORAGE_CLASS_HMEM_C
#include "hmem_public.h"
#else /* __INLINE_HMEM__ */
#define STORAGE_CLASS_HMEM_H static inline
* @param[in] id The global unique ID of the csi rx fe controller.
* @param[out] state Point to the register-state.
*/
-extern void csi_rx_fe_ctrl_get_state(
+void csi_rx_fe_ctrl_get_state(
const csi_rx_frontend_ID_t ID,
csi_rx_fe_ctrl_state_t *state);
/**
* @param[in] id The global unique ID of the csi rx fe controller.
* @param[in] state Point to the register-state.
*/
-extern void csi_rx_fe_ctrl_dump_state(
+void csi_rx_fe_ctrl_dump_state(
const csi_rx_frontend_ID_t ID,
csi_rx_fe_ctrl_state_t *state);
/**
* @param[in] lane The lane ID.
* @param[out] state Point to the dlane state.
*/
-extern void csi_rx_fe_ctrl_get_dlane_state(
+void csi_rx_fe_ctrl_get_dlane_state(
const csi_rx_frontend_ID_t ID,
- const uint32_t lane,
+ const u32 lane,
csi_rx_fe_ctrl_lane_t *dlane_state);
/**
* @brief Get the csi rx backend state.
* @param[in] id The global unique ID of the csi rx be controller.
* @param[out] state Point to the register-state.
*/
-extern void csi_rx_be_ctrl_get_state(
+void csi_rx_be_ctrl_get_state(
const csi_rx_backend_ID_t ID,
csi_rx_be_ctrl_state_t *state);
/**
* @param[in] id The global unique ID of the csi rx be controller.
* @param[in] state Point to the register-state.
*/
-extern void csi_rx_be_ctrl_dump_state(
+void csi_rx_be_ctrl_dump_state(
const csi_rx_backend_ID_t ID,
csi_rx_be_ctrl_state_t *state);
/* end of NCI */
*
* @return the value of the register.
*/
-extern hrt_data csi_rx_fe_ctrl_reg_load(
+hrt_data csi_rx_fe_ctrl_reg_load(
const csi_rx_frontend_ID_t ID,
const hrt_address reg);
/**
* @param[in] value The value to be stored.
*
*/
-extern void csi_rx_fe_ctrl_reg_store(
+void csi_rx_fe_ctrl_reg_store(
const csi_rx_frontend_ID_t ID,
const hrt_address reg,
const hrt_data value);
*
* @return the value of the register.
*/
-extern hrt_data csi_rx_be_ctrl_reg_load(
+hrt_data csi_rx_be_ctrl_reg_load(
const csi_rx_backend_ID_t ID,
const hrt_address reg);
/**
* @param[in] value The value to be stored.
*
*/
-extern void csi_rx_be_ctrl_reg_store(
+void csi_rx_be_ctrl_reg_store(
const csi_rx_backend_ID_t ID,
const hrt_address reg,
const hrt_data value);
extern hrt_vaddress debug_buffer_ddr_address;
/*! Check the empty state of the local debug data buffer
-
+
\return isEmpty(buffer)
*/
STORAGE_CLASS_DEBUG_H bool is_debug_buffer_empty(void);
/*! Dequeue a token from the debug data buffer
-
+
\return isEmpty(buffer)?0:buffer[head]
*/
STORAGE_CLASS_DEBUG_H hrt_data debug_dequeue(void);
/*! Synchronise the remote buffer to the local buffer
-
+
\return none
*/
STORAGE_CLASS_DEBUG_H void debug_synch_queue(void);
/*! Synchronise the remote buffer to the local buffer
-
+
\return none
*/
STORAGE_CLASS_DEBUG_H void debug_synch_queue_isp(void);
-
/*! Synchronise the remote buffer to the local buffer
-
+
\return none
*/
STORAGE_CLASS_DEBUG_H void debug_synch_queue_ddr(void);
/*! Set the offset/address of the (remote) debug buffer
-
+
\return none
*/
-extern void debug_buffer_init(
+void debug_buffer_init(
const hrt_address addr);
/*! Set the offset/address of the (remote) debug buffer
-
+
\return none
*/
-extern void debug_buffer_ddr_init(
+void debug_buffer_ddr_init(
const hrt_vaddress addr);
/*! Set the (remote) operating mode of the debug buffer
-
+
\return none
*/
-extern void debug_buffer_setmode(
+void debug_buffer_setmode(
const debug_buf_mode_t mode);
#endif /* __DEBUG_PUBLIC_H_INCLUDED__ */
\return none, state = DMA[ID].state
*/
-extern void dma_get_state(
+void dma_get_state(
const dma_ID_t ID,
dma_state_t *state);
const dma_ID_t ID,
const unsigned int reg);
-
/*! Set maximum burst size of DMA[ID]
\param ID[in] DMA identifier
#include "system_types.h"
/*! Blocking read from an event source EVENT[ID]
-
+
\param ID[in] EVENT identifier
\return none, dequeue(event_queue[ID])
const event_ID_t ID);
/*! Conditional blocking wait for an event source EVENT[ID]
-
+
\param ID[in] EVENT identifier
\param cnd[in] predicate
const bool cnd);
/*! Blocking read from an event source EVENT[ID]
-
+
\param ID[in] EVENT identifier
\return dequeue(event_queue[ID])
const event_ID_t ID);
/*! Blocking write to an event sink EVENT[ID]
-
+
\param ID[in] EVENT identifier
\param token[in] token to be written on the event
const hrt_data token);
/*! Query an event source EVENT[ID]
-
+
\param ID[in] EVENT identifier
\return !isempty(event_queue[ID])
const event_ID_t ID);
/*! Query an event sink EVENT[ID]
-
+
\param ID[in] EVENT identifier
\return !isfull(event_queue[ID])
typedef struct fifo_monitor_state_s fifo_monitor_state_t;
/*! Set a fifo switch multiplex
-
+
\param ID[in] FIFO_MONITOR identifier
\param switch_id[in] fifo switch identifier
\param sel[in] fifo switch selector
const hrt_data sel);
/*! Get a fifo switch multiplex
-
+
\param ID[in] FIFO_MONITOR identifier
\param switch_id[in] fifo switch identifier
const fifo_switch_t switch_id);
/*! Read the state of FIFO_MONITOR[ID]
-
+
\param ID[in] FIFO_MONITOR identifier
\param state[out] fifo monitor state structure
\return none, state = FIFO_MONITOR[ID].state
*/
-extern void fifo_monitor_get_state(
+void fifo_monitor_get_state(
const fifo_monitor_ID_t ID,
fifo_monitor_state_t *state);
/*! Read the state of a fifo channel
-
+
\param ID[in] FIFO_MONITOR identifier
\param channel_id[in] fifo channel identifier
\param state[out] fifo channel state structure
\return none, state = fifo_channel[channel_id].state
*/
-extern void fifo_channel_get_state(
+void fifo_channel_get_state(
const fifo_monitor_ID_t ID,
const fifo_channel_t channel_id,
fifo_channel_state_t *state);
/*! Read the state of a fifo switch
-
+
\param ID[in] FIFO_MONITOR identifier
\param switch_id[in] fifo switch identifier
\param state[out] fifo switch state structure
\return none, state = fifo_switch[switch_id].state
*/
-extern void fifo_switch_get_state(
+void fifo_switch_get_state(
const fifo_monitor_ID_t ID,
const fifo_switch_t switch_id,
fifo_switch_state_t *state);
/*! Write to a control register of FIFO_MONITOR[ID]
-
+
\param ID[in] FIFO_MONITOR identifier
\param reg[in] register index
\param value[in] The data to be written
const hrt_data value);
/*! Read from a control register of FIFO_MONITOR[ID]
-
+
\param ID[in] FIFO_MONITOR identifier
\param reg[in] register index
\param value[in] The data to be written
\return none, GDC[ID].lut[0...3][0...HRT_GDC_N-1] = data
*/
-extern void gdc_lut_store(
+void gdc_lut_store(
const gdc_ID_t ID,
const int data[4][HRT_GDC_N]);
\param in_lut[in] The data matrix to be converted
\param out_lut[out] The data matrix as the output of conversion
*/
-extern void gdc_lut_convert_to_isp_format(
+void gdc_lut_convert_to_isp_format(
const int in_lut[4][HRT_GDC_N],
int out_lut[4][HRT_GDC_N]);
/*! Return the integer representation of 1.0 of GDC[ID]
-
+
\param ID[in] GDC identifier
\return unity
*/
-extern int gdc_get_unity(
+int gdc_get_unity(
const gdc_ID_t ID);
#endif /* __GDC_PUBLIC_H_INCLUDED__ */
typedef struct gp_device_state_s gp_device_state_t;
/*! Read the state of GP_DEVICE[ID]
-
+
\param ID[in] GP_DEVICE identifier
\param state[out] gp device state structure
\return none, state = GP_DEVICE[ID].state
*/
-extern void gp_device_get_state(
+void gp_device_get_state(
const gp_device_ID_t ID,
gp_device_state_t *state);
const hrt_data value);
/*! Read from a control register of GP_DEVICE[ID]
-
+
\param ID[in] GP_DEVICE identifier
\param reg_addr[in] register byte address
\param value[in] The data to be written
extern void
gp_timer_init(gp_timer_ID_t ID);
-
/*! read timer value for (platform selected)selected timer.
param ID timer_id
\return uint32_t 32 bit timer value
const hrt_data value);
/*! Read from a control register of GPIO[ID]
-
+
\param ID[in] GPIO identifier
\param reg_addr[in] register byte address
\param value[in] The data to be written
*/
STORAGE_CLASS_IBUF_CTRL_H void ibuf_ctrl_get_proc_state(
const ibuf_ctrl_ID_t ID,
- const uint32_t proc_id,
+ const u32 proc_id,
ibuf_ctrl_proc_state_t *state);
/**
* @brief Dump the ibuf-controller state.
#include "system_types.h"
/*! Reset INPUT_FORMATTER[ID]
-
+
\param ID[in] INPUT_FORMATTER identifier
\return none, reset(INPUT_FORMATTER[ID])
*/
-extern void input_formatter_rst(
+void input_formatter_rst(
const input_formatter_ID_t ID);
/*! Set the blocking mode of INPUT_FORMATTER[ID]
-
+
\param ID[in] INPUT_FORMATTER identifier
\param enable[in] blocking enable flag
\return none, INPUT_FORMATTER[ID].blocking_mode = enable
*/
-extern void input_formatter_set_fifo_blocking_mode(
+void input_formatter_set_fifo_blocking_mode(
const input_formatter_ID_t ID,
const bool enable);
/*! Return the data alignment of INPUT_FORMATTER[ID]
-
+
\param ID[in] INPUT_FORMATTER identifier
\return alignment(INPUT_FORMATTER[ID].data)
*/
-extern unsigned int input_formatter_get_alignment(
+unsigned int input_formatter_get_alignment(
const input_formatter_ID_t ID);
/*! Read the source switch state into INPUT_FORMATTER[ID]
-
+
\param ID[in] INPUT_FORMATTER identifier
\param state[out] input formatter switch state structure
\return none, state = INPUT_FORMATTER[ID].switch_state
*/
-extern void input_formatter_get_switch_state(
+void input_formatter_get_switch_state(
const input_formatter_ID_t ID,
input_formatter_switch_state_t *state);
/*! Read the control registers of INPUT_FORMATTER[ID]
-
+
\param ID[in] INPUT_FORMATTER identifier
\param state[out] input formatter state structure
\return none, state = INPUT_FORMATTER[ID].state
*/
-extern void input_formatter_get_state(
+void input_formatter_get_state(
const input_formatter_ID_t ID,
input_formatter_state_t *state);
/*! Read the control registers of bin copy INPUT_FORMATTER[ID]
-
+
\param ID[in] INPUT_FORMATTER identifier
\param state[out] input formatter state structure
\return none, state = INPUT_FORMATTER[ID].state
*/
-extern void input_formatter_bin_get_state(
+void input_formatter_bin_get_state(
const input_formatter_ID_t ID,
input_formatter_bin_state_t *state);
/*! Write to a control register of INPUT_FORMATTER[ID]
-
+
\param ID[in] INPUT_FORMATTER identifier
\param reg_addr[in] register byte address
\param value[in] The data to be written
const hrt_data value);
/*! Read from a control register of INPUT_FORMATTER[ID]
-
+
\param ID[in] INPUT_FORMATTER identifier
\param reg_addr[in] register byte address
\param value[in] The data to be written
\return none, state = INPUT_SYSTEM[ID].state
*/
-extern void input_system_get_state(
+void input_system_get_state(
const input_system_ID_t ID,
input_system_state_t *state);
\return none, state = RECEIVER[ID].state
*/
-extern void receiver_get_state(
+void receiver_get_state(
const rx_ID_t ID,
receiver_state_t *state);
\return mipi_format == YUV420
*/
-extern bool is_mipi_format_yuv420(
+bool is_mipi_format_yuv420(
const mipi_format_t mipi_format);
/*! Set compression parameters for cfg[cfg_ID] of RECEIVER[ID]
\param pred[in] Predictor method
\NOTE: the storage of compression configuration is
- implementation specific. The config can be
- carried either on MIPI ports or on MIPI channels
+ implementation specific. The config can be
+ carried either on MIPI ports or on MIPI channels
\return none, RECEIVER[ID].cfg[cfg_ID] = {comp, pred}
*/
-extern void receiver_set_compression(
+void receiver_set_compression(
const rx_ID_t ID,
const unsigned int cfg_ID,
const mipi_compressor_t comp,
\return None, enable(RECEIVER[ID].PORT[port_ID])
*/
-extern void receiver_port_enable(
+void receiver_port_enable(
const rx_ID_t ID,
const enum mipi_port_id port_ID,
const bool cnd);
\return enable(RECEIVER[ID].PORT[port_ID]) == true
*/
-extern bool is_receiver_port_enabled(
+bool is_receiver_port_enabled(
const rx_ID_t ID,
const enum mipi_port_id port_ID);
\return None, enable(RECEIVER[ID].PORT[port_ID].irq_info)
*/
-extern void receiver_irq_enable(
+void receiver_irq_enable(
const rx_ID_t ID,
const enum mipi_port_id port_ID,
const rx_irq_info_t irq_info);
\return RECEIVER[ID].PORT[port_ID].irq_info
*/
-extern rx_irq_info_t receiver_get_irq_info(
+rx_irq_info_t receiver_get_irq_info(
const rx_ID_t ID,
const enum mipi_port_id port_ID);
\return None, clear(RECEIVER[ID].PORT[port_ID].irq_info)
*/
-extern void receiver_irq_clear(
+void receiver_irq_clear(
const rx_ID_t ID,
const enum mipi_port_id port_ID,
const rx_irq_info_t irq_info);
const sub_system_ID_t sub_ID,
const hrt_address reg);
-
-
///////////////////////////////////////////////////////////////////////////
//
// Functions for configuration phase on input system.
//
///////////////////////////////////////////////////////////////////////////
-
// FIFO channel config function user
input_system_error_t input_system_csi_fifo_channel_cfg(
- uint32_t ch_id,
+ u32 ch_id,
input_system_csi_port_t port,
backend_channel_cfg_t backend_ch,
target_cfg2400_t target
);
input_system_error_t input_system_csi_fifo_channel_with_counting_cfg(
- uint32_t ch_id,
- uint32_t nof_frame,
+ u32 ch_id,
+ u32 nof_frame,
input_system_csi_port_t port,
backend_channel_cfg_t backend_ch,
- uint32_t mem_region_size,
- uint32_t nof_mem_regions,
+ u32 mem_region_size,
+ u32 nof_mem_regions,
target_cfg2400_t target
);
-
// SRAM channel config function user
input_system_error_t input_system_csi_sram_channel_cfg(
- uint32_t ch_id,
+ u32 ch_id,
input_system_csi_port_t port,
backend_channel_cfg_t backend_ch,
- uint32_t csi_mem_region_size,
- uint32_t csi_nof_mem_regions,
- target_cfg2400_t target
+ u32 csi_mem_region_size,
+ u32 csi_nof_mem_regions,
+ target_cfg2400_t target
);
-
//XMEM channel config function user
input_system_error_t input_system_csi_xmem_channel_cfg(
- uint32_t ch_id,
+ u32 ch_id,
input_system_csi_port_t port,
backend_channel_cfg_t backend_ch,
- uint32_t mem_region_size,
- uint32_t nof_mem_regions,
- uint32_t acq_mem_region_size,
- uint32_t acq_nof_mem_regions,
- target_cfg2400_t target,
- uint32_t nof_xmem_buffers
+ u32 mem_region_size,
+ u32 nof_mem_regions,
+ u32 acq_mem_region_size,
+ u32 acq_nof_mem_regions,
+ target_cfg2400_t target,
+ uint32_t nof_xmem_buffers
);
input_system_error_t input_system_csi_xmem_capture_only_channel_cfg(
- uint32_t ch_id,
- uint32_t nof_frames,
+ u32 ch_id,
+ u32 nof_frames,
input_system_csi_port_t port,
- uint32_t csi_mem_region_size,
- uint32_t csi_nof_mem_regions,
- uint32_t acq_mem_region_size,
- uint32_t acq_nof_mem_regions,
- target_cfg2400_t target
+ u32 csi_mem_region_size,
+ u32 csi_nof_mem_regions,
+ u32 acq_mem_region_size,
+ u32 acq_nof_mem_regions,
+ target_cfg2400_t target
);
input_system_error_t input_system_csi_xmem_acquire_only_channel_cfg(
- uint32_t ch_id,
- uint32_t nof_frames,
+ u32 ch_id,
+ u32 nof_frames,
input_system_csi_port_t port,
backend_channel_cfg_t backend_ch,
- uint32_t acq_mem_region_size,
- uint32_t acq_nof_mem_regions,
- target_cfg2400_t target
+ u32 acq_mem_region_size,
+ u32 acq_nof_mem_regions,
+ target_cfg2400_t target
);
// Non - CSI channel config function user
input_system_error_t input_system_prbs_channel_cfg(
- uint32_t ch_id,
- uint32_t nof_frames,
- uint32_t seed,
- uint32_t sync_gen_width,
- uint32_t sync_gen_height,
- uint32_t sync_gen_hblank_cycles,
- uint32_t sync_gen_vblank_cycles,
+ u32 ch_id,
+ u32 nof_frames,
+ u32 seed,
+ u32 sync_gen_width,
+ u32 sync_gen_height,
+ u32 sync_gen_hblank_cycles,
+ u32 sync_gen_vblank_cycles,
target_cfg2400_t target
);
-
input_system_error_t input_system_tpg_channel_cfg(
- uint32_t ch_id,
- uint32_t nof_frames,//not used yet
- uint32_t x_mask,
- uint32_t y_mask,
- uint32_t x_delta,
- uint32_t y_delta,
- uint32_t xy_mask,
- uint32_t sync_gen_width,
- uint32_t sync_gen_height,
- uint32_t sync_gen_hblank_cycles,
- uint32_t sync_gen_vblank_cycles,
+ u32 ch_id,
+ u32 nof_frames,//not used yet
+ u32 x_mask,
+ u32 y_mask,
+ u32 x_delta,
+ u32 y_delta,
+ u32 xy_mask,
+ u32 sync_gen_width,
+ u32 sync_gen_height,
+ u32 sync_gen_hblank_cycles,
+ u32 sync_gen_vblank_cycles,
target_cfg2400_t target
);
-
input_system_error_t input_system_gpfifo_channel_cfg(
- uint32_t ch_id,
- uint32_t nof_frames,
+ u32 ch_id,
+ u32 nof_frames,
target_cfg2400_t target
);
#endif /* #ifdef USE_INPUT_SYSTEM_VERSION_2401 */
\return none, state = IRQ[ID].state
*/
-extern void irq_controller_get_state(
+void irq_controller_get_state(
const irq_ID_t ID,
irq_controller_state_t *state);
\return none, enable(IRQ[ID].channel[irq_ID])
*/
-extern void irq_enable_channel(
+void irq_enable_channel(
const irq_ID_t ID,
const unsigned int irq_ID);
\return none
*/
-extern void irq_enable_pulse(
+void irq_enable_pulse(
const irq_ID_t ID,
- bool pulse);
+ bool pulse);
/*! Disable an IRQ channel of IRQ[ID]
\return none, disable(IRQ[ID].channel[irq_ID])
*/
-extern void irq_disable_channel(
+void irq_disable_channel(
const irq_ID_t ID,
const unsigned int irq);
\return none, clear(IRQ[ID].channel[])
*/
-extern void irq_clear_all(
+void irq_clear_all(
const irq_ID_t ID);
/*! Return the ID of a signalling IRQ channel of IRQ[ID]
\return state(IRQ[ID])
*/
-extern enum hrt_isp_css_irq_status irq_get_channel_id(
+enum hrt_isp_css_irq_status irq_get_channel_id(
const irq_ID_t ID,
unsigned int *irq_id);
\return none, signal(IRQ[ID].channel[irq_id])
*/
-extern void irq_raise(
+void irq_raise(
const irq_ID_t ID,
const irq_sw_channel_id_t irq_id);
\return any(VIRQ.channel[irq_ID] != 0)
*/
-extern bool any_virq_signal(void);
+bool any_virq_signal(void);
/*! Enable an IRQ channel of the virtual super IRQ
\return none, VIRQ.channel[irq_ID].enable = en
*/
-extern void cnd_virq_enable_channel(
+void cnd_virq_enable_channel(
const virq_id_t irq_ID,
const bool en);
\return none, clear(VIRQ.channel[])
*/
-extern void virq_clear_all(void);
+void virq_clear_all(void);
/*! Clear the IRQ info state of the virtual super IRQ
\return none
*/
-extern void virq_clear_info(
+void virq_clear_info(
virq_info_t *irq_info);
/*! Return the ID of a signalling IRQ channel of the virtual super IRQ
\return state(IRQ[...])
*/
-extern enum hrt_isp_css_irq_status virq_get_channel_id(
+enum hrt_isp_css_irq_status virq_get_channel_id(
virq_id_t *irq_id);
/*! Return the IDs of all signaling IRQ channels of the virtual super IRQ
\return (error(state(IRQ[...]))
*/
-extern enum hrt_isp_css_irq_status virq_get_channel_signals(
+enum hrt_isp_css_irq_status virq_get_channel_signals(
virq_info_t *irq_info);
#endif /* __IRQ_PUBLIC_H_INCLUDED__ */
\return none, if(cnd) enable(ISP[ID].irq) else disable(ISP[ID].irq)
*/
-extern void cnd_isp_irq_enable(
+void cnd_isp_irq_enable(
const isp_ID_t ID,
const bool cnd);
\return none, state = ISP[ID].state, stall = ISP[ID].stall
*/
-extern void isp_get_state(
+void isp_get_state(
const isp_ID_t ID,
isp_state_t *state,
isp_stall_t *stall);
-
/*! Write to the status and control register of ISP[ID]
\param ID[in] ISP identifier
\return x0 | (x1 << bits_per_vector_element)
*/
STORAGE_CLASS_ISP_H uint32_t isp_2w_cat_1w(
- const uint16_t x0,
+ const u16 x0,
const uint16_t x1);
-unsigned isp_is_ready(isp_ID_t ID);
+unsigned int isp_is_ready(isp_ID_t ID);
-unsigned isp_is_sleeping(isp_ID_t ID);
+unsigned int isp_is_sleeping(isp_ID_t ID);
void isp_start(isp_ID_t ID);
const isys2401_dma_ID_t dma_id,
const unsigned int reg);
-extern void isys2401_dma_set_max_burst_size(
+void isys2401_dma_set_max_burst_size(
const isys2401_dma_ID_t dma_id,
uint32_t max_burst_size);
\return none, MMU[ID].page_table_base_index = base_index
*/
-extern void mmu_set_page_table_base_index(
+void mmu_set_page_table_base_index(
const mmu_ID_t ID,
const hrt_data base_index);
\return MMU[ID].page_table_base_index
*/
-extern hrt_data mmu_get_page_table_base_index(
+hrt_data mmu_get_page_table_base_index(
const mmu_ID_t ID);
/*! Invalidate the page table cache of MMU[ID]
\return none
*/
-extern void mmu_invalidate_cache(
+void mmu_invalidate_cache(
const mmu_ID_t ID);
-
/*! Invalidate the page table cache of all MMUs
\return none
*/
-extern void mmu_invalidate_cache_all(void);
+void mmu_invalidate_cache_all(void);
/*! Write to a control register of MMU[ID]
const hrt_data value)
{
assert(ID < N_MMU_ID);
- assert(MMU_BASE[ID] != (hrt_address)-1);
- ia_css_device_store_uint32(MMU_BASE[ID] + reg*sizeof(hrt_data), value);
+ assert(MMU_BASE[ID] != (hrt_address) - 1);
+ ia_css_device_store_uint32(MMU_BASE[ID] + reg * sizeof(hrt_data), value);
return;
}
-
/*! Read from a control register of MMU[ID]
\param ID[in] MMU identifier
const unsigned int reg)
{
assert(ID < N_MMU_ID);
- assert(MMU_BASE[ID] != (hrt_address)-1);
- return ia_css_device_load_uint32(MMU_BASE[ID] + reg*sizeof(hrt_data));
+ assert(MMU_BASE[ID] != (hrt_address) - 1);
+ return ia_css_device_load_uint32(MMU_BASE[ID] + reg * sizeof(hrt_data));
}
#endif /* __MMU_PUBLIC_H_INCLUDED__ */
typedef struct sp_stall_s sp_stall_t;
/*! Enable or disable the program complete irq signal of SP[ID]
-
+
\param ID[in] SP identifier
\param cnd[in] predicate
\return none, if(cnd) enable(SP[ID].irq) else disable(SP[ID].irq)
*/
-extern void cnd_sp_irq_enable(
+void cnd_sp_irq_enable(
const sp_ID_t ID,
const bool cnd);
/*! Read the state of cell SP[ID]
-
+
\param ID[in] SP identifier
\param state[out] sp state structure
\param stall[out] isp stall conditions
\return none, state = SP[ID].state, stall = SP[ID].stall
*/
-extern void sp_get_state(
+void sp_get_state(
const sp_ID_t ID,
sp_state_t *state,
sp_stall_t *stall);
sh_css_encode_tag_descr(struct sh_css_tag_descr *tag);
#endif /* __TAG_PUBLIC_H_INCLUDED__ */
-
const unsigned int reg_addr,
const hrt_data value);
-extern void timed_ctrl_snd_commnd(
+void timed_ctrl_snd_commnd(
const timed_ctrl_ID_t ID,
hrt_data mask,
hrt_data condition,
hrt_address addr,
hrt_data value);
-extern void timed_ctrl_snd_sp_commnd(
+void timed_ctrl_snd_sp_commnd(
const timed_ctrl_ID_t ID,
hrt_data mask,
hrt_data condition,
hrt_address offset,
hrt_data value);
-extern void timed_ctrl_snd_gpio_commnd(
+void timed_ctrl_snd_gpio_commnd(
const timed_ctrl_ID_t ID,
hrt_data mask,
hrt_data condition,
#ifndef __VAMEM_PUBLIC_H_INCLUDED__
#define __VAMEM_PUBLIC_H_INCLUDED__
-
-
#endif /* __VAMEM_PUBLIC_H_INCLUDED__ */
#ifndef __IBUF_CTRL_H_INCLUDED__
#define __IBUF_CTRL_H_INCLUDED__
-
/*
* This file is included on every cell {SP,ISP,host} and on every system
* that uses the input system device(s). It defines the API to DLI bridge
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "ibuf_ctrl_local.h"
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "input_formatter_local.h"
#ifndef __INLINE_INPUT_FORMATTER__
#define STORAGE_CLASS_INPUT_FORMATTER_H extern
-#define STORAGE_CLASS_INPUT_FORMATTER_C
+#define STORAGE_CLASS_INPUT_FORMATTER_C
#include "input_formatter_public.h"
#else /* __INLINE_INPUT_FORMATTER__ */
#define STORAGE_CLASS_INPUT_FORMATTER_H static inline
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "input_system_local.h"
#ifndef __INLINE_INPUT_SYSTEM__
#define STORAGE_CLASS_INPUT_SYSTEM_H extern
-#define STORAGE_CLASS_INPUT_SYSTEM_C
+#define STORAGE_CLASS_INPUT_SYSTEM_C
#include "input_system_public.h"
#else /* __INLINE_INPUT_SYSTEM__ */
#define STORAGE_CLASS_INPUT_SYSTEM_H static inline
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "irq_local.h"
#ifndef __INLINE_IRQ__
#define STORAGE_CLASS_IRQ_H extern
-#define STORAGE_CLASS_IRQ_C
+#define STORAGE_CLASS_IRQ_C
#include "irq_public.h"
#else /* __INLINE_IRQ__ */
#define STORAGE_CLASS_IRQ_H static inline
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "isp_local.h"
#ifndef __INLINE_ISP__
#define STORAGE_CLASS_ISP_H extern
-#define STORAGE_CLASS_ISP_C
+#define STORAGE_CLASS_ISP_C
#include "isp_public.h"
#else /* __INLINE_iSP__ */
#define STORAGE_CLASS_ISP_H static inline
#ifndef __ISYS_DMA_H_INCLUDED__
#define __ISYS_DMA_H_INCLUDED__
-
/*
* This file is included on every cell {SP,ISP,host} and on every system
* that uses the input system device(s). It defines the API to DLI bridge
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "isys_dma_local.h"
#ifndef __ISYS_STREAM2MMIO_H_INCLUDED__
#define __ISYS_STREAM2MMIO_H_INCLUDED__
-
/*
* This file is included on every cell {SP,ISP,host} and on every system
* that uses the input system device(s). It defines the API to DLI bridge
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "isys_stream2mmio_local.h"
#define CEIL_DIV(a, b) (((b) != 0) ? ((a) + (b) - 1) / (b) : 0)
#define CEIL_MUL(a, b) (CEIL_DIV(a, b) * (b))
#define CEIL_MUL2(a, b) (((a) + (b) - 1) & ~((b) - 1))
-#define CEIL_SHIFT(a, b) (((a) + (1 << (b)) - 1)>>(b))
+#define CEIL_SHIFT(a, b) (((a) + (1 << (b)) - 1) >> (b))
#define CEIL_SHIFT_MUL(a, b) (CEIL_SHIFT(a, b) << (b))
#ifdef ISP2401
#define ROUND_HALF_DOWN_DIV(a, b) (((b) != 0) ? ((a) + (b / 2) - 1) / (b) : 0)
#define ROUND_HALF_DOWN_MUL(a, b) (ROUND_HALF_DOWN_DIV(a, b) * (b))
#endif
-
/*To Find next power of 2 number from x */
#define bit2(x) ((x) | ((x) >> 1))
#define bit4(x) (bit2(x) | (bit2(x) >> 2))
#define bit8(x) (bit4(x) | (bit4(x) >> 4))
#define bit16(x) (bit8(x) | (bit8(x) >> 8))
#define bit32(x) (bit16(x) | (bit16(x) >> 16))
-#define NEXT_POWER_OF_2(x) (bit32(x-1) + 1)
-
+#define NEXT_POWER_OF_2(x) (bit32(x - 1) + 1)
/* min and max should not be macros as they will evaluate their arguments twice.
if you really need a macro (e.g. for CPP or for initializing an array)
use MIN() and MAX(), otherwise use min() and max().
-
*/
#if !defined(PIPE_GENERATION)
return MIN(a, b);
}
-
static inline unsigned int ceil_mul(unsigned int a, unsigned int b)
{
return CEIL_MUL(a, b);
return 1;
}
/* IF input is already a power of two*/
- else if ((!((a)&((a)-1)))) {
+ else if ((!((a) & ((a) - 1)))) {
return a;
- }
- else {
+ } else {
unsigned int v = a;
- v |= v>>1;
- v |= v>>2;
- v |= v>>4;
- v |= v>>8;
- v |= v>>16;
- return (v+1);
+
+ v |= v >> 1;
+ v |= v >> 2;
+ v |= v >> 4;
+ v |= v >> 8;
+ v |= v >> 16;
+ return (v + 1);
}
}
* For SP and ISP, SDK provides the definition of OP_std_modadd.
* We need it only for host
*/
-#define OP_std_modadd(base, offset, size) ((base+offset)%(size))
+#define OP_std_modadd(base, offset, size) ((base + offset) % (size))
#endif /* !defined(__ISP) */
-
#endif /* __MATH_SUPPORT_H */
\return vaddress
*/
-extern hrt_vaddress mmgr_malloc(const size_t size);
+hrt_vaddress mmgr_malloc(const size_t size);
/*! Return the address of a zero initialised allocation in memory
\return vaddress
*/
-extern hrt_vaddress mmgr_calloc(const size_t N, const size_t size);
+hrt_vaddress mmgr_calloc(const size_t N, const size_t size);
/*! Return the address of an allocation in memory
\return vaddress
*/
-extern hrt_vaddress mmgr_alloc_attr(const size_t size, const uint16_t attribute);
+hrt_vaddress mmgr_alloc_attr(const size_t size, const uint16_t attribute);
/*! Return the address of a mapped existing allocation in memory
\return vaddress
*/
-extern hrt_vaddress mmgr_mmap(
+hrt_vaddress mmgr_mmap(
const void __user *ptr,
const size_t size,
- uint16_t attribute,
+ u16 attribute,
void *context);
/*! Zero initialise an allocation in memory
\return none
*/
-extern void mmgr_clear(hrt_vaddress vaddr, const size_t size);
+void mmgr_clear(hrt_vaddress vaddr, const size_t size);
/*! Read an array of bytes from a virtual memory address
\return none
*/
-extern void mmgr_load(const hrt_vaddress vaddr, void *data, const size_t size);
+void mmgr_load(const hrt_vaddress vaddr, void *data, const size_t size);
/*! Write an array of bytes to device registers or memory in the device
\return none
*/
-extern void mmgr_store(const hrt_vaddress vaddr, const void *data, const size_t size);
+void mmgr_store(const hrt_vaddress vaddr, const void *data, const size_t size);
#endif /* __MEMORY_ACCESS_H_INCLUDED__ */
#include "ia_css_err.h"
bool reallocate_buffer(
- hrt_vaddress *curr_buf,
+ hrt_vaddress * curr_buf,
size_t *curr_size,
size_t needed_size,
bool force,
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "mmu_local.h"
#ifndef __PIXELGEN_H_INCLUDED__
#define __PIXELGEN_H_INCLUDED__
-
/*
* This file is included on every cell {SP,ISP,host} and on every system
* that uses the input system device(s). It defines the API to DLI bridge
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "pixelgen_local.h"
#ifndef __PRINT_SUPPORT_H_INCLUDED__
#define __PRINT_SUPPORT_H_INCLUDED__
-
#include <stdarg.h>
-extern int (*sh_css_printf) (const char *fmt, va_list args);
+extern int (*sh_css_printf)(const char *fmt, va_list args);
/* depends on host supplied print function in ia_css_init() */
static inline void ia_css_print(const char *fmt, ...)
{
va_list ap;
+
if (sh_css_printf) {
va_start(ap, fmt);
sh_css_printf(fmt, ap);
*
*/
-
#include "queue_local.h"
#ifndef __INLINE_QUEUE__
#define STORAGE_CLASS_QUEUE_H extern
-#define STORAGE_CLASS_QUEUE_C
+#define STORAGE_CLASS_QUEUE_C
/* #include "queue_public.h" */
#include "ia_css_queue.h"
#else /* __INLINE_QUEUE__ */
*
*/
-
#include "system_local.h"
#include "resource_local.h"
#ifndef __INLINE_RESOURCE__
#define STORAGE_CLASS_RESOURCE_H extern
-#define STORAGE_CLASS_RESOURCE_C
+#define STORAGE_CLASS_RESOURCE_C
#include "resource_public.h"
#else /* __INLINE_RESOURCE__ */
#define STORAGE_CLASS_RESOURCE_H static inline
*
*/
-
#include "system_local.h"
#include "socket_local.h"
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "sp_local.h"
#ifndef __INLINE_SP__
#define STORAGE_CLASS_SP_H extern
-#define STORAGE_CLASS_SP_C
+#define STORAGE_CLASS_SP_C
#include "sp_public.h"
#else /* __INLINE_SP__ */
#define STORAGE_CLASS_SP_H static inline
* For all non microsoft cases, we need the following functions
*/
-
/* @brief Copy from src_buf to dest_buf.
*
* @param[out] dest_buf. Destination buffer to copy to
* @return ERANGE on Destination size too small
*/
static inline int memcpy_s(
- void* dest_buf,
+ void *dest_buf,
size_t dest_size,
- const void* src_buf,
+ const void *src_buf,
size_t src_size)
{
- if ((src_buf == NULL) || (dest_buf == NULL)) {
+ if ((!src_buf) || (!dest_buf)) {
/* Invalid arguments*/
return EINVAL;
}
* @return Returns 0 if src_str is NULL
*/
static size_t strnlen_s(
- const char* src_str,
+ const char *src_str,
size_t max_len)
{
size_t ix;
- if (src_str == NULL) {
+
+ if (!src_str) {
/* Invalid arguments*/
return 0;
}
* @return Returns ERANGE on destination size too small
*/
static inline int strncpy_s(
- char* dest_str,
+ char *dest_str,
size_t dest_size,
- const char* src_str,
+ const char *src_str,
size_t src_size)
{
size_t len;
- if (dest_str == NULL) {
+
+ if (!dest_str) {
/* Invalid arguments*/
return EINVAL;
}
- if ((src_str == NULL) || (dest_size == 0)) {
+ if ((!src_str) || (dest_size == 0)) {
/* Invalid arguments*/
dest_str[0] = '\0';
return EINVAL;
* @return Returns ERANGE on destination size too small
*/
static inline int strcpy_s(
- char* dest_str,
+ char *dest_str,
size_t dest_size,
- const char* src_str)
+ const char *src_str)
{
size_t len;
- if (dest_str == NULL) {
+
+ if (!dest_str) {
/* Invalid arguments*/
return EINVAL;
}
- if ((src_str == NULL) || (dest_size == 0)) {
+ if ((!src_str) || (dest_size == 0)) {
/* Invalid arguments*/
dest_str[0] = '\0';
return EINVAL;
* Platform specific types.
*/
-
#include "system_local.h"
#endif /* __SYSTEM_TYPES_H_INCLUDED__ */
*
*/
-
#include "tag_local.h"
#ifndef __INLINE_TAG__
#define STORAGE_CLASS_TAG_H extern
-#define STORAGE_CLASS_TAG_C
+#define STORAGE_CLASS_TAG_C
#include "tag_public.h"
#else /* __INLINE_TAG__ */
#define STORAGE_CLASS_TAG_H static inline
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "timed_ctrl_local.h"
#ifndef __INLINE_TIMED_CTRL__
#define STORAGE_CLASS_TIMED_CTRL_H extern
-#define STORAGE_CLASS_TIMED_CTRL_C
+#define STORAGE_CLASS_TIMED_CTRL_C
#include "timed_ctrl_public.h"
#else /* __INLINE_TIMED_CTRL__ */
#define STORAGE_CLASS_TIMED_CTRL_H static inline
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "vamem_local.h"
#ifndef __INLINE_VAMEM__
#define STORAGE_CLASS_VAMEM_H extern
-#define STORAGE_CLASS_VAMEM_C
+#define STORAGE_CLASS_VAMEM_C
#include "vamem_public.h"
#else /* __INLINE_VAMEM__ */
#define STORAGE_CLASS_VAMEM_H static inline
* - local: system and cell specific constants and identifiers
*/
-
#include "system_local.h"
#include "vmem_local.h"
#ifndef __INLINE_VMEM__
#define STORAGE_CLASS_VMEM_H extern
-#define STORAGE_CLASS_VMEM_C
+#define STORAGE_CLASS_VMEM_C
#include "vmem_public.h"
#else /* __INLINE_VMEM__ */
#define STORAGE_CLASS_VMEM_H static inline
unsigned int exp_id,
struct sh_css_tag_descr *tag_descr)
{
- assert(tag_descr != NULL);
+ assert(tag_descr);
tag_descr->num_captures = num_captures;
tag_descr->skip = skip;
unsigned int exp_id;
unsigned int encoded_tag;
- assert(tag != NULL);
+ assert(tag);
if (tag->num_captures < 0) {
num_captures = -tag->num_captures;
assert((num_captures == 0) && (skip == 0) && (offset == 0));
encoded_tag = TAG_EXP | (exp_id & 0xFF) << TAG_EXP_ID_SHIFT;
- }
- else
+ } else
{
- encoded_tag = TAG_CAP
+ encoded_tag = TAG_CAP
| ((num_captures_sign & 0x00000001) << TAG_NUM_CAPTURES_SIGN_SHIFT)
| ((offset_sign & 0x00000001) << TAG_OFFSET_SIGN_SHIFT)
| ((num_captures & 0x000000FF) << TAG_NUM_CAPTURES_SHIFT)
| ((skip & 0x000000FF) << TAG_OFFSET_SHIFT)
| ((offset & 0x000000FF) << TAG_SKIP_SHIFT);
-
}
return encoded_tag;
}
#define __QUEUE_GLOBAL_H_INCLUDED__
#endif /* __QUEUE_GLOBAL_H_INCLUDED__ */
-
};
#endif /* __SW_EVENT_GLOBAL_H_INCLUDED__ */
-
#define TAG_EXP 2
#define TAG_NUM_CAPTURES_SIGN_SHIFT 6
-#define TAG_OFFSET_SIGN_SHIFT 7
-#define TAG_NUM_CAPTURES_SHIFT 8
-#define TAG_OFFSET_SHIFT 16
-#define TAG_SKIP_SHIFT 24
+#define TAG_OFFSET_SIGN_SHIFT 7
+#define TAG_NUM_CAPTURES_SHIFT 8
+#define TAG_OFFSET_SHIFT 16
+#define TAG_SKIP_SHIFT 24
-#define TAG_EXP_ID_SHIFT 8
+#define TAG_EXP_ID_SHIFT 8
/* Data structure containing the tagging information which is used in
* continuous mode to specify which frames should be captured.
struct {
ia_css_ptr rgby_tbl;
} data_hmem;
- uint32_t exp_id; /** exposure id, to match statistics to a frame,
- see ia_css_event_public.h for more detail. */
- uint32_t isp_config_id;/** Unique ID to track which config was actually applied to a particular frame */
+ u32 exp_id; /** exposure id, to match statistics to a frame,
+ see ia_css_event_public.h for more detail. */
+ u32 isp_config_id;/** Unique ID to track which config was actually applied to a particular frame */
ia_css_ptr data_ptr; /** pointer to base of all data */
- uint32_t size; /** total size of all data */
- uint32_t dmem_size;
- uint32_t vmem_size; /** both lo and hi have this size */
- uint32_t hmem_size;
+ u32 size; /** total size of all data */
+ u32 dmem_size;
+ u32 vmem_size; /** both lo and hi have this size */
+ u32 hmem_size;
};
+
#define SIZE_OF_DMEM_STRUCT \
(SIZE_OF_IA_CSS_PTR)
struct ia_css_isp_3a_statistics_map {
void *data_ptr; /** Pointer to start of memory */
struct ia_css_3a_output *dmem_stats;
- uint16_t *vmem_stats_hi;
- uint16_t *vmem_stats_lo;
+ u16 *vmem_stats_hi;
+ u16 *vmem_stats_lo;
struct ia_css_bh_table *hmem_stats;
- uint32_t size; /** total size in bytes of data_ptr */
- uint32_t data_allocated; /** indicate whether data_ptr
+ u32 size; /** total size in bytes of data_ptr */
+ u32 data_allocated; /** indicate whether data_ptr
was allocated or not. */
};
*/
struct ia_css_blob_info {
/** Static blob data */
- uint32_t offset; /** Blob offset in fw file */
+ u32 offset; /** Blob offset in fw file */
struct ia_css_isp_param_memory_offsets memory_offsets; /** offset wrt hdr in bytes */
- uint32_t prog_name_offset; /** offset wrt hdr in bytes */
- uint32_t size; /** Size of blob */
- uint32_t padding_size; /** total cummulative of bytes added due to section alignment */
- uint32_t icache_source; /** Position of icache in blob */
- uint32_t icache_size; /** Size of icache section */
- uint32_t icache_padding;/** bytes added due to icache section alignment */
- uint32_t text_source; /** Position of text in blob */
- uint32_t text_size; /** Size of text section */
- uint32_t text_padding; /** bytes added due to text section alignment */
- uint32_t data_source; /** Position of data in blob */
- uint32_t data_target; /** Start of data in SP dmem */
- uint32_t data_size; /** Size of text section */
- uint32_t data_padding; /** bytes added due to data section alignment */
- uint32_t bss_target; /** Start position of bss in SP dmem */
- uint32_t bss_size; /** Size of bss section */
+ u32 prog_name_offset; /** offset wrt hdr in bytes */
+ u32 size; /** Size of blob */
+ u32 padding_size; /** total cummulative of bytes added due to section alignment */
+ u32 icache_source; /** Position of icache in blob */
+ u32 icache_size; /** Size of icache section */
+ u32 icache_padding;/** bytes added due to icache section alignment */
+ u32 text_source; /** Position of text in blob */
+ u32 text_size; /** Size of text section */
+ u32 text_padding; /** bytes added due to text section alignment */
+ u32 data_source; /** Position of data in blob */
+ u32 data_target; /** Start of data in SP dmem */
+ u32 data_size; /** Size of text section */
+ u32 data_padding; /** bytes added due to data section alignment */
+ u32 bss_target; /** Start position of bss in SP dmem */
+ u32 bss_size; /** Size of bss section */
/** Dynamic data filled by loader */
CSS_ALIGN(const void *code, 8); /** Code section absolute pointer within fw, code = icache + text */
CSS_ALIGN(const void *data, 8); /** Data section absolute pointer within fw, data = data + bss */
};
struct ia_css_binary_input_info {
- uint32_t min_width;
- uint32_t min_height;
- uint32_t max_width;
- uint32_t max_height;
- uint32_t source; /* memory, sensor, variable */
+ u32 min_width;
+ u32 min_height;
+ u32 max_width;
+ u32 max_height;
+ u32 source; /* memory, sensor, variable */
};
struct ia_css_binary_output_info {
- uint32_t min_width;
- uint32_t min_height;
- uint32_t max_width;
- uint32_t max_height;
- uint32_t num_chunks;
- uint32_t variable_format;
+ u32 min_width;
+ u32 min_height;
+ u32 max_width;
+ u32 max_height;
+ u32 num_chunks;
+ u32 variable_format;
};
struct ia_css_binary_internal_info {
- uint32_t max_width;
- uint32_t max_height;
+ u32 max_width;
+ u32 max_height;
};
struct ia_css_binary_bds_info {
- uint32_t supported_bds_factors;
+ u32 supported_bds_factors;
};
struct ia_css_binary_dvs_info {
- uint32_t max_envelope_width;
- uint32_t max_envelope_height;
+ u32 max_envelope_width;
+ u32 max_envelope_height;
};
struct ia_css_binary_vf_dec_info {
- uint32_t is_variable;
- uint32_t max_log_downscale;
+ u32 is_variable;
+ u32 max_log_downscale;
};
struct ia_css_binary_s3a_info {
- uint32_t s3atbl_use_dmem;
- uint32_t fixed_s3a_deci_log;
+ u32 s3atbl_use_dmem;
+ u32 fixed_s3a_deci_log;
};
/* DPC related binary info */
struct ia_css_binary_dpc_info {
- uint32_t bnr_lite; /** bnr lite enable flag */
+ u32 bnr_lite; /** bnr lite enable flag */
};
struct ia_css_binary_iterator_info {
- uint32_t num_stripes;
- uint32_t row_stripes_height;
- uint32_t row_stripes_overlap_lines;
+ u32 num_stripes;
+ u32 row_stripes_height;
+ u32 row_stripes_overlap_lines;
};
struct ia_css_binary_address_info {
- uint32_t isp_addresses; /* Address in ISP dmem */
- uint32_t main_entry; /* Address of entry fct */
- uint32_t in_frame; /* Address in ISP dmem */
- uint32_t out_frame; /* Address in ISP dmem */
- uint32_t in_data; /* Address in ISP dmem */
- uint32_t out_data; /* Address in ISP dmem */
- uint32_t sh_dma_cmd_ptr; /* In ISP dmem */
+ u32 isp_addresses; /* Address in ISP dmem */
+ u32 main_entry; /* Address of entry fct */
+ u32 in_frame; /* Address in ISP dmem */
+ u32 out_frame; /* Address in ISP dmem */
+ u32 in_data; /* Address in ISP dmem */
+ u32 out_data; /* Address in ISP dmem */
+ u32 sh_dma_cmd_ptr; /* In ISP dmem */
};
struct ia_css_binary_uds_info {
- uint16_t bpp;
- uint16_t use_bci;
- uint16_t use_str;
- uint16_t woix;
- uint16_t woiy;
- uint16_t extra_out_vecs;
- uint16_t vectors_per_line_in;
- uint16_t vectors_per_line_out;
- uint16_t vectors_c_per_line_in;
- uint16_t vectors_c_per_line_out;
- uint16_t vmem_gdc_in_block_height_y;
- uint16_t vmem_gdc_in_block_height_c;
+ u16 bpp;
+ u16 use_bci;
+ u16 use_str;
+ u16 woix;
+ u16 woiy;
+ u16 extra_out_vecs;
+ u16 vectors_per_line_in;
+ u16 vectors_per_line_out;
+ u16 vectors_c_per_line_in;
+ u16 vectors_c_per_line_out;
+ u16 vmem_gdc_in_block_height_y;
+ u16 vmem_gdc_in_block_height_c;
/* uint16_t padding; */
};
struct ia_css_binary_pipeline_info {
- uint32_t mode;
- uint32_t isp_pipe_version;
- uint32_t pipelining;
- uint32_t c_subsampling;
- uint32_t top_cropping;
- uint32_t left_cropping;
- uint32_t variable_resolution;
+ u32 mode;
+ u32 isp_pipe_version;
+ u32 pipelining;
+ u32 c_subsampling;
+ u32 top_cropping;
+ u32 left_cropping;
+ u32 variable_resolution;
};
struct ia_css_binary_block_info {
- uint32_t block_width;
- uint32_t block_height;
- uint32_t output_block_height;
+ u32 block_width;
+ u32 block_height;
+ u32 output_block_height;
};
/* Structure describing an ISP binary.
* thereby making the SP code more binary independent.
*/
struct ia_css_binary_info {
- CSS_ALIGN(uint32_t id, 8); /* IA_CSS_BINARY_ID_* */
+ CSS_ALIGN(u32 id, 8); /* IA_CSS_BINARY_ID_* */
struct ia_css_binary_pipeline_info pipeline;
struct ia_css_binary_input_info input;
struct ia_css_binary_output_info output;
/* MW: Packing (related) bools in an integer ?? */
struct {
#ifdef ISP2401
- uint8_t luma_only;
- uint8_t input_yuv;
- uint8_t input_raw;
+ u8 luma_only;
+ u8 input_yuv;
+ u8 input_raw;
#endif
- uint8_t reduced_pipe;
- uint8_t vf_veceven;
- uint8_t dis;
- uint8_t dvs_envelope;
- uint8_t uds;
- uint8_t dvs_6axis;
- uint8_t block_output;
- uint8_t streaming_dma;
- uint8_t ds;
- uint8_t bayer_fir_6db;
- uint8_t raw_binning;
- uint8_t continuous;
- uint8_t s3a;
- uint8_t fpnr;
- uint8_t sc;
- uint8_t macc;
- uint8_t output;
- uint8_t ref_frame;
- uint8_t tnr;
- uint8_t xnr;
- uint8_t params;
- uint8_t ca_gdc;
- uint8_t isp_addresses;
- uint8_t in_frame;
- uint8_t out_frame;
- uint8_t high_speed;
- uint8_t dpc;
- uint8_t padding[2];
+ u8 reduced_pipe;
+ u8 vf_veceven;
+ u8 dis;
+ u8 dvs_envelope;
+ u8 uds;
+ u8 dvs_6axis;
+ u8 block_output;
+ u8 streaming_dma;
+ u8 ds;
+ u8 bayer_fir_6db;
+ u8 raw_binning;
+ u8 continuous;
+ u8 s3a;
+ u8 fpnr;
+ u8 sc;
+ u8 macc;
+ u8 output;
+ u8 ref_frame;
+ u8 tnr;
+ u8 xnr;
+ u8 params;
+ u8 ca_gdc;
+ u8 isp_addresses;
+ u8 in_frame;
+ u8 out_frame;
+ u8 high_speed;
+ u8 dpc;
+ u8 padding[2];
} enable;
struct {
/* DMA channel ID: [0,...,HIVE_ISP_NUM_DMA_CHANNELS> */
- uint8_t ref_y_channel;
- uint8_t ref_c_channel;
- uint8_t tnr_channel;
- uint8_t tnr_out_channel;
- uint8_t dvs_coords_channel;
- uint8_t output_channel;
- uint8_t c_channel;
- uint8_t vfout_channel;
- uint8_t vfout_c_channel;
- uint8_t vfdec_bits_per_pixel;
- uint8_t claimed_by_isp;
- uint8_t padding[2];
+ u8 ref_y_channel;
+ u8 ref_c_channel;
+ u8 tnr_channel;
+ u8 tnr_out_channel;
+ u8 dvs_coords_channel;
+ u8 output_channel;
+ u8 c_channel;
+ u8 vfout_channel;
+ u8 vfout_c_channel;
+ u8 vfdec_bits_per_pixel;
+ u8 claimed_by_isp;
+ u8 padding[2];
} dma;
};
/* Rest of the binary info, only interesting to the host. */
enum ia_css_acc_type type;
- CSS_ALIGN(int32_t num_output_formats, 8);
+
+ CSS_ALIGN(s32 num_output_formats, 8);
enum ia_css_frame_format output_formats[IA_CSS_FRAME_FORMAT_NUM];
- CSS_ALIGN(int32_t num_vf_formats, 8); /** number of supported vf formats */
+
+ CSS_ALIGN(s32 num_vf_formats, 8); /** number of supported vf formats */
enum ia_css_frame_format vf_formats[IA_CSS_FRAME_FORMAT_NUM]; /** types of supported vf formats */
- uint8_t num_output_pins;
+ u8 num_output_pins;
ia_css_ptr xmem_addr;
+
CSS_ALIGN(const struct ia_css_blob_descr *blob, 8);
- CSS_ALIGN(uint32_t blob_index, 8);
+ CSS_ALIGN(u32 blob_index, 8);
CSS_ALIGN(union ia_css_all_memory_offsets mem_offsets, 8);
CSS_ALIGN(struct ia_css_binary_xinfo *next, 8);
};
* the entry function in icache.
*/
struct ia_css_bl_info {
- uint32_t num_dma_cmds; /** Number of cmds sent by CSS */
- uint32_t dma_cmd_list; /** Dma command list sent by CSS */
- uint32_t sw_state; /** Polled from css */
+ u32 num_dma_cmds; /** Number of cmds sent by CSS */
+ u32 dma_cmd_list; /** Dma command list sent by CSS */
+ u32 sw_state; /** Polled from css */
/* Entry functions */
- uint32_t bl_entry; /** The SP entry function */
+ u32 bl_entry; /** The SP entry function */
};
/* Structure describing the SP binary.
* the entry function in pmem.
*/
struct ia_css_sp_info {
- uint32_t init_dmem_data; /** data sect config, stored to dmem */
- uint32_t per_frame_data; /** Per frame data, stored to dmem */
- uint32_t group; /** Per pipeline data, loaded by dma */
- uint32_t output; /** SP output data, loaded by dmem */
- uint32_t host_sp_queue; /** Host <-> SP queues */
- uint32_t host_sp_com;/** Host <-> SP commands */
- uint32_t isp_started; /** Polled from sensor thread, csim only */
- uint32_t sw_state; /** Polled from css */
- uint32_t host_sp_queues_initialized; /** Polled from the SP */
- uint32_t sleep_mode; /** different mode to halt SP */
- uint32_t invalidate_tlb; /** inform SP to invalidate mmu TLB */
+ u32 init_dmem_data; /** data sect config, stored to dmem */
+ u32 per_frame_data; /** Per frame data, stored to dmem */
+ u32 group; /** Per pipeline data, loaded by dma */
+ u32 output; /** SP output data, loaded by dmem */
+ u32 host_sp_queue; /** Host <-> SP queues */
+ u32 host_sp_com;/** Host <-> SP commands */
+ u32 isp_started; /** Polled from sensor thread, csim only */
+ u32 sw_state; /** Polled from css */
+ u32 host_sp_queues_initialized; /** Polled from the SP */
+ u32 sleep_mode; /** different mode to halt SP */
+ u32 invalidate_tlb; /** inform SP to invalidate mmu TLB */
#ifndef ISP2401
- uint32_t stop_copy_preview; /** suspend copy and preview pipe when capture */
+ u32 stop_copy_preview; /** suspend copy and preview pipe when capture */
#endif
- uint32_t debug_buffer_ddr_address; /** inform SP the address
+ u32 debug_buffer_ddr_address; /** inform SP the address
of DDR debug queue */
- uint32_t perf_counter_input_system_error; /** input system perf
+ u32 perf_counter_input_system_error; /** input system perf
counter array */
#ifdef HAS_WATCHDOG_SP_THREAD_DEBUG
- uint32_t debug_wait; /** thread/pipe post mortem debug */
- uint32_t debug_stage; /** thread/pipe post mortem debug */
- uint32_t debug_stripe; /** thread/pipe post mortem debug */
+ u32 debug_wait; /** thread/pipe post mortem debug */
+ u32 debug_stage; /** thread/pipe post mortem debug */
+ u32 debug_stripe; /** thread/pipe post mortem debug */
#endif
- uint32_t threads_stack; /** sp thread's stack pointers */
- uint32_t threads_stack_size; /** sp thread's stack sizes */
- uint32_t curr_binary_id; /** current binary id */
- uint32_t raw_copy_line_count; /** raw copy line counter */
- uint32_t ddr_parameter_address; /** acc param ddrptr, sp dmem */
- uint32_t ddr_parameter_size; /** acc param size, sp dmem */
+ u32 threads_stack; /** sp thread's stack pointers */
+ u32 threads_stack_size; /** sp thread's stack sizes */
+ u32 curr_binary_id; /** current binary id */
+ u32 raw_copy_line_count; /** raw copy line counter */
+ u32 ddr_parameter_address; /** acc param ddrptr, sp dmem */
+ u32 ddr_parameter_size; /** acc param size, sp dmem */
/* Entry functions */
- uint32_t sp_entry; /** The SP entry function */
- uint32_t tagger_frames_addr; /** Base address of tagger state */
+ u32 sp_entry; /** The SP entry function */
+ u32 tagger_frames_addr; /** Base address of tagger state */
};
/* The following #if is there because this header file is also included
/* Accelerator firmware information.
*/
struct ia_css_acc_info {
- uint32_t per_frame_data; /** Dummy for now */
+ u32 per_frame_data; /** Dummy for now */
};
/* Firmware information.
*/
struct ia_css_fw_info {
size_t header_size; /** size of fw header */
- CSS_ALIGN(uint32_t type, 8);
+
+ CSS_ALIGN(u32 type, 8);
union ia_css_fw_union info; /** Binary info */
struct ia_css_blob_info blob; /** Blob info */
/* Dynamic part */
struct ia_css_fw_info *next;
- CSS_ALIGN(uint32_t loaded, 8); /** Firmware has been loaded */
- CSS_ALIGN(const uint8_t *isp_code, 8); /** ISP pointer to code */
+
+ CSS_ALIGN(u32 loaded, 8); /** Firmware has been loaded */
+ CSS_ALIGN(const u8 *isp_code, 8); /** ISP pointer to code */
/** Firmware handle between user space and kernel */
- CSS_ALIGN(uint32_t handle, 8);
+ CSS_ALIGN(u32 handle, 8);
/** Sections to copy from/to ISP */
struct ia_css_isp_param_css_segments mem_initializers;
/** Initializer for local ISP memories */
*/
struct ia_css_acc_sp {
void (*init)(struct ia_css_acc_fw *); /** init for crun */
- uint32_t sp_prog_name_offset; /** program name offset wrt hdr in bytes */
- uint32_t sp_blob_offset; /** blob offset wrt hdr in bytes */
+ u32 sp_prog_name_offset; /** program name offset wrt hdr in bytes */
+ u32 sp_blob_offset; /** blob offset wrt hdr in bytes */
void *entry; /** Address of sp entry point */
- uint32_t *css_abort; /** SP dmem abort flag */
+ u32 *css_abort; /** SP dmem abort flag */
void *isp_code; /** SP dmem address holding xmem
address of isp code */
struct ia_css_fw_info fw; /** SP fw descriptor */
- const uint8_t *code; /** ISP pointer of allocated SP code */
+ const u8 *code; /** ISP pointer of allocated SP code */
};
/* Acceleration firmware descriptor.
*/
struct ia_css_acc_fw_hdr {
enum ia_css_acc_type type; /** Type of accelerator */
- uint32_t isp_prog_name_offset; /** program name offset wrt
+ u32 isp_prog_name_offset; /** program name offset wrt
header in bytes */
- uint32_t isp_blob_offset; /** blob offset wrt header
+ u32 isp_blob_offset; /** blob offset wrt header
in bytes */
- uint32_t isp_size; /** Size of isp blob */
- const uint8_t *isp_code; /** ISP pointer to code */
+ u32 isp_size; /** Size of isp blob */
+ const u8 *isp_code; /** ISP pointer to code */
struct ia_css_acc_sp sp; /** Standalone sp code */
/** Firmware handle between user space and kernel */
- uint32_t handle;
+ u32 handle;
struct ia_css_data parameters; /** Current SP parameters */
};
};
/* Access macros for firmware */
-#define IA_CSS_ACC_OFFSET(t, f, n) ((t)((uint8_t *)(f)+(f->header.n)))
+#define IA_CSS_ACC_OFFSET(t, f, n) ((t)((uint8_t *)(f) + (f->header.n)))
#define IA_CSS_ACC_SP_PROG_NAME(f) IA_CSS_ACC_OFFSET(const char *, f, \
sp.sp_prog_name_offset)
#define IA_CSS_ACC_ISP_PROG_NAME(f) IA_CSS_ACC_OFFSET(const char *, f, \
#define IA_CSS_ACC_ISP_SIZE(f) ((f)->header.isp_size)
/* Binary name follows header immediately */
-#define IA_CSS_EXT_ISP_PROG_NAME(f) ((const char *)(f)+(f)->blob.prog_name_offset)
+#define IA_CSS_EXT_ISP_PROG_NAME(f) ((const char *)(f) + (f)->blob.prog_name_offset)
#define IA_CSS_EXT_ISP_MEM_OFFSETS(f) \
- ((const struct ia_css_memory_offsets *)((const char *)(f)+(f)->blob.mem_offsets))
+ ((const struct ia_css_memory_offsets *)((const char *)(f) + (f)->blob.mem_offsets))
#endif /* !defined(__ISP) */
struct ia_css_acc_param *custom_data; /** Custom buffer. */
struct ia_css_metadata *metadata; /** Sensor metadata. */
} data; /** Buffer data pointer. */
- uint64_t driver_cookie; /** cookie for the driver */
+ u64 driver_cookie; /** cookie for the driver */
struct ia_css_time_meas timing_data; /** timing data (readings from the timer) */
struct ia_css_clock_tick isys_eof_clock_tick; /** ISYS's end of frame timer tick*/
};
enum ia_css_err ia_css_init(
const struct ia_css_env *env,
const struct ia_css_fw *fw,
- uint32_t l1_base,
+ u32 l1_base,
enum ia_css_irq_type irq_type);
/* @brief Un-initialize the CSS API.
enum ia_css_err
ia_css_start_sp(void);
-
/* @brief stop SP hardware
*
* @return IA_CSS_SUCCESS or error code upon error.
void
ia_css_device_access_init(const struct ia_css_hw_access_env *env)
{
- assert(env != NULL);
+ assert(env);
my_env = *env;
}
SKC_DVS_STATISTICS
};
-
/* Structure that holds DVS statistics in the ISP internal
* format. Use ia_css_get_dvs_statistics() to translate
* this to the format used on the host (DVS engine).
struct ia_css_isp_dvs_statistics {
ia_css_ptr hor_proj;
ia_css_ptr ver_proj;
- uint32_t hor_size;
- uint32_t ver_size;
- uint32_t exp_id; /** see ia_css_event_public.h for more detail */
+ u32 hor_size;
+ u32 ver_size;
+ u32 exp_id; /** see ia_css_event_public.h for more detail */
ia_css_ptr data_ptr; /* base pointer containing all memory */
- uint32_t size; /* size of allocated memory in data_ptr */
+ u32 size; /* size of allocated memory in data_ptr */
};
/* Structure that holds SKC DVS statistics in the ISP internal
* */
struct ia_css_isp_skc_dvs_statistics;
-
#define SIZE_OF_IA_CSS_ISP_DVS_STATISTICS_STRUCT \
((3 * SIZE_OF_IA_CSS_PTR) + \
(4 * sizeof(uint32_t)))
*/
struct ia_css_isp_dvs_statistics_map {
void *data_ptr;
- int32_t *hor_proj;
- int32_t *ver_proj;
- uint32_t size; /* total size in bytes */
- uint32_t data_allocated; /* indicate whether data was allocated */
+ s32 *hor_proj;
+ s32 *ver_proj;
+ u32 size; /* total size in bytes */
+ u32 data_allocated; /* indicate whether data was allocated */
};
union ia_css_dvs_statistics_isp {
/** Extension stage complete. */
IA_CSS_EVENT_TYPE_TIMER = 1 << 12,
/** Timer event for measuring the SP side latencies. It contains the
- 32-bit timer value from the SP */
+ 32-bit timer value from the SP */
IA_CSS_EVENT_TYPE_PORT_EOF = 1 << 13,
/** End Of Frame event, sent when in buffered sensor mode. */
IA_CSS_EVENT_TYPE_FW_WARNING = 1 << 14,
events. */
enum ia_css_event_type type;
/** Type of Event, always valid/filled. */
- uint8_t port;
+ u8 port;
/** Port number for EOF event (not valid for other events). */
- uint8_t exp_id;
+ u8 exp_id;
/** Exposure id for EOF/FRAME_TAGGED/FW_WARNING event (not valid for other events)
The exposure ID is unique only within a logical stream and it is
only generated on systems that have an input system (such as 2400
Note that in case frames are dropped, this will not be reflected
in the exposure IDs. Therefor applications should not use this
to detect frame drops. */
- uint32_t fw_handle;
+ u32 fw_handle;
/** Firmware Handle for ACC_STAGE_COMPLETE event (not valid for other
events). */
enum ia_css_fw_warning fw_warning;
/** Firmware warning code, only for WARNING events. */
- uint8_t fw_assert_module_id;
+ u8 fw_assert_module_id;
/** Firmware module id, only for ASSERT events, should be logged by driver. */
- uint16_t fw_assert_line_no;
+ u16 fw_assert_line_no;
/** Firmware line number, only for ASSERT events, should be logged by driver. */
clock_value_t timer_data;
/** For storing the full 32-bit of the timer value. Valid only for TIMER
event */
- uint8_t timer_code;
+ u8 timer_code;
/** For storing the code of the TIMER event. Valid only for
TIMER event */
- uint8_t timer_subcode;
+ u8 timer_subcode;
/** For storing the subcode of the TIMER event. Valid only
for TIMER event */
};
* to save on extension operations in the ISP code.
*/
/* Unsigned fixed point value, 0 integer bits, 16 fractional bits */
-typedef uint32_t ia_css_u0_16;
+typedef u32 ia_css_u0_16;
/* Unsigned fixed point value, 5 integer bits, 11 fractional bits */
-typedef uint32_t ia_css_u5_11;
+typedef u32 ia_css_u5_11;
/* Unsigned fixed point value, 8 integer bits, 8 fractional bits */
-typedef uint32_t ia_css_u8_8;
+typedef u32 ia_css_u8_8;
/* Signed fixed point value, 0 integer bits, 15 fractional bits */
-typedef int32_t ia_css_s0_15;
+typedef s32 ia_css_s0_15;
#endif /* _IA_CSS_FRAC_H */
IA_CSS_BAYER_ORDER_BGGR, /** BGBGBGBGBG .. GRGRGRGRGR */
IA_CSS_BAYER_ORDER_GBRG, /** GBGBGBGBGB .. RGRGRGRGRG */
};
+
#define IA_CSS_BAYER_ORDER_NUM (IA_CSS_BAYER_ORDER_GBRG + 1)
/* Frame plane structure. This describes one plane in an image
enum ia_css_frame_flash_state flash_state;
unsigned int exp_id;
/** exposure id, see ia_css_event_public.h for more detail */
- uint32_t isp_config_id; /** Unique ID to track which config was actually applied to a particular frame */
+ u32 isp_config_id; /** Unique ID to track which config was actually applied to a particular frame */
bool valid; /** First video output frame is not valid */
bool contiguous; /** memory is allocated physically contiguously */
union {
ia_css_frame_map(struct ia_css_frame **frame,
const struct ia_css_frame_info *info,
const void __user *data,
- uint16_t attribute,
+ u16 attribute,
void *context);
/* @brief Unmap a CSS frame structure.
void ia_css_host_data_free(struct ia_css_host_data *me);
#endif /* __SH_CSS_HOST_DATA_H */
-
hrt_vaddress mmgr_alloc_attr(const size_t size, const uint16_t attrs)
{
- uint16_t masked_attrs = attrs & MMGR_ATTRIBUTE_MASK;
+ u16 masked_attrs = attrs & MMGR_ATTRIBUTE_MASK;
+
WARN_ON(attrs & MMGR_ATTRIBUTE_CONTIGUOUS);
if (masked_attrs & MMGR_ATTRIBUTE_CLEARED) {
hrt_vaddress
mmgr_mmap(const void __user *ptr, const size_t size,
- uint16_t attribute, void *context)
+ u16 attribute, void *context)
{
struct hrt_userbuffer_attr *userbuffer_attr = context;
+
return hrt_isp_css_mm_alloc_user_ptr(
size, ptr, userbuffer_attr->pgnr,
userbuffer_attr->type,
struct ia_css_metadata_info {
struct ia_css_resolution resolution; /** Resolution */
- uint32_t stride; /** Stride in bytes */
- uint32_t size; /** Total size in bytes */
+ u32 stride; /** Stride in bytes */
+ u32 size; /** Total size in bytes */
};
struct ia_css_metadata {
struct ia_css_metadata_info info; /** Layout info */
ia_css_ptr address; /** CSS virtual address */
- uint32_t exp_id;
+ u32 exp_id;
/** Exposure ID, see ia_css_event_public.h for more detail */
};
+
#define SIZE_OF_IA_CSS_METADATA_STRUCT sizeof(struct ia_css_metadata)
/* @brief Allocate a metadata buffer.
struct ia_css_isp_parameters *params,
bool commit, struct ia_css_pipe *pipe);
-
-
#endif /* __IA_CSS_PIPE_H__ */
IA_CSS_PIPE_MODE_YUVPP, /** YUV post processing pipe, used for all use cases with YUV input,
for SoC sensor and external ISP */
};
+
/* Temporary define */
#define IA_CSS_PIPE_MODE_NUM (IA_CSS_PIPE_MODE_YUVPP + 1)
/** Pipeline extension accelerator */
struct ia_css_fw_info **acc_stages;
/** Standalone accelerator stages */
- uint32_t num_acc_stages;
+ u32 num_acc_stages;
/** Number of standalone accelerator stages */
struct ia_css_capture_config default_capture_config;
/** Default capture config for initial capture pipe configuration. */
#endif
};
-
/**
* Default settings for newly created pipe configurations.
*/
ia_css_pipe_dequeue_buffer(struct ia_css_pipe *pipe,
struct ia_css_buffer *buffer);
-
/* @brief Set the state (Enable or Disable) of the Extension stage in the
* given pipe.
* @param[in] pipe Pipe handle.
* @param[in] enable Enable Flag (1 to enable ; 0 to disable)
*
* @return
- * IA_CSS_SUCCESS : Success
+ * IA_CSS_SUCCESS : Success
* IA_CSS_ERR_INVALID_ARGUMENTS : Invalid Parameters
* IA_CSS_ERR_RESOURCE_NOT_AVAILABLE : Inactive QOS Pipe
- * (No active stream with this pipe)
+ * (No active stream with this pipe)
*
* This function will request state change (enable or disable) for the Extension
* stage (firmware handle) in the given pipe.
*
* Note:
- * 1. Extension can be enabled/disabled only on QOS Extensions
- * 2. Extension can be enabled/disabled only with an active QOS Pipe
- * 3. Initial(Default) state of QOS Extensions is Disabled
- * 4. State change cannot be guaranteed immediately OR on frame boundary
+ * 1. Extension can be enabled/disabled only on QOS Extensions
+ * 2. Extension can be enabled/disabled only with an active QOS Pipe
+ * 3. Initial(Default) state of QOS Extensions is Disabled
+ * 4. State change cannot be guaranteed immediately OR on frame boundary
*
*/
enum ia_css_err
-ia_css_pipe_set_qos_ext_state (struct ia_css_pipe *pipe,
- uint32_t fw_handle,
- bool enable);
+ia_css_pipe_set_qos_ext_state(struct ia_css_pipe *pipe,
+ u32 fw_handle,
+ bool enable);
/* @brief Get the state (Enable or Disable) of the Extension stage in the
* given pipe.
* @param[out] *enable Enable Flag
*
* @return
- * IA_CSS_SUCCESS : Success
+ * IA_CSS_SUCCESS : Success
* IA_CSS_ERR_INVALID_ARGUMENTS : Invalid Parameters
* IA_CSS_ERR_RESOURCE_NOT_AVAILABLE : Inactive QOS Pipe
- * (No active stream with this pipe)
+ * (No active stream with this pipe)
*
* This function will query the state of the Extension stage (firmware handle)
* in the given Pipe.
*
* Note:
- * 1. Extension state can be queried only on QOS Extensions
- * 2. Extension can be enabled/disabled only with an active QOS Pipe
- * 3. Initial(Default) state of QOS Extensions is Disabled.
+ * 1. Extension state can be queried only on QOS Extensions
+ * 2. Extension can be enabled/disabled only with an active QOS Pipe
+ * 3. Initial(Default) state of QOS Extensions is Disabled.
*
*/
enum ia_css_err
-ia_css_pipe_get_qos_ext_state (struct ia_css_pipe *pipe,
- uint32_t fw_handle,
- bool * enable);
+ia_css_pipe_get_qos_ext_state(struct ia_css_pipe *pipe,
+ u32 fw_handle,
+ bool *enable);
#ifdef ISP2401
/* @brief Update mapped CSS and ISP arguments for QoS pipe during SP runtime.
- * @param[in] pipe Pipe handle.
+ * @param[in] pipe Pipe handle.
* @param[in] fw_handle Extension firmware Handle (ia_css_fw_info.handle).
- * @param[in] css_seg Parameter memory descriptors for CSS segments.
- * @param[in] isp_seg Parameter memory descriptors for ISP segments.
+ * @param[in] css_seg Parameter memory descriptors for CSS segments.
+ * @param[in] isp_seg Parameter memory descriptors for ISP segments.
*
* @return
- * IA_CSS_SUCCESS : Success
+ * IA_CSS_SUCCESS : Success
* IA_CSS_ERR_INVALID_ARGUMENTS : Invalid Parameters
* IA_CSS_ERR_RESOURCE_NOT_AVAILABLE : Inactive QOS Pipe
- * (No active stream with this pipe)
+ * (No active stream with this pipe)
*
* \deprecated{This interface is used to temporarily support a late-developed,
* specific use-case on a specific IPU2 platform. It will not be supported or
* @param[in] lut Look up tabel
*
* @return
- * IA_CSS_SUCCESS : Success
+ * IA_CSS_SUCCESS : Success
* IA_CSS_ERR_INVALID_ARGUMENTS : Invalid Parameters
*
* Note:
*
*/
enum ia_css_err
-ia_css_pipe_set_bci_scaler_lut( struct ia_css_pipe *pipe,
+ia_css_pipe_set_bci_scaler_lut(struct ia_css_pipe *pipe,
const void *lut);
/* @brief Checking of DVS statistics ability
* @param[in] pipe_info The pipe info.
* @return true - has DVS statistics ability
- * false - otherwise
+ * false - otherwise
*/
bool ia_css_pipe_has_dvs_stats(struct ia_css_pipe_info *pipe_info);
* Make sure the value of this define gets changed to reflect the correct
* number of ia_css_prbs_id enum if you add/delete an item in the enum.
*/
-#define N_CSS_PRBS_IDS (IA_CSS_PRBS_ID2+1)
+#define N_CSS_PRBS_IDS (IA_CSS_PRBS_ID2 + 1)
/**
* PRBS configuration structure.
enum ia_css_bayer_order bayer_order; /** Bayer order for RAW streams */
};
-
/* Input stream description. This describes how input will flow into the
* CSS. This is used to program the CSS hardware.
*/
bool online; /** offline will activate RAW copy on SP, use this for
continuous capture. */
/* ISYS2401 usage: ISP receives data directly from sensor, no copy. */
- unsigned init_num_cont_raw_buf; /** initial number of raw buffers to
+ unsigned int init_num_cont_raw_buf; /** initial number of raw buffers to
allocate */
- unsigned target_num_cont_raw_buf; /** total number of raw buffers to
+ unsigned int target_num_cont_raw_buf; /** total number of raw buffers to
allocate */
bool pack_raw_pixels; /** Pack pixels in the raw buffers */
bool continuous; /** Use SP copy feature to continuously capture frames
to system memory and run pipes in offline mode */
bool disable_cont_viewfinder; /** disable continuous viewfinder for ZSL use case */
- int32_t flash_gpio_pin; /** pin on which the flash is connected, -1 for no flash */
+ s32 flash_gpio_pin; /** pin on which the flash is connected, -1 for no flash */
int left_padding; /** The number of input-formatter left-paddings, -1 for default from binary.*/
struct ia_css_mipi_buffer_config mipi_buffer_config; /** mipi buffer configuration */
struct ia_css_metadata_config metadata_config; /** Metadata configuration. */
ia_css_stream_request_flash(struct ia_css_stream *stream);
/* @brief Configure a stream with filter coefficients.
- * @deprecated {Replaced by
- * ia_css_pipe_set_isp_config_on_pipe()}
+ * @deprecated {Replaced by
+ * ia_css_pipe_set_isp_config_on_pipe()}
*
* @param[in] stream The stream.
* @param[in] config The set of filter coefficients.
struct ia_css_pipe *pipe);
/* @brief Configure a stream with filter coefficients.
- * @deprecated {Replaced by
- * ia_css_pipe_set_isp_config()}
+ * @deprecated {Replaced by
+ * ia_css_pipe_set_isp_config()}
* @param[in] stream The stream.
* @param[in] config The set of filter coefficients.
* @return IA_CSS_SUCCESS or error code upon error.
#include "ia_css_err.h"
/* @brief timer reading definition */
-typedef uint32_t clock_value_t;
+typedef u32 clock_value_t;
/* @brief 32 bit clock tick,(timestamp based on timer-value of CSS-internal timer)*/
struct ia_css_clock_tick {
* Make sure the value of this define gets changed to reflect the correct
* number of ia_css_tpg_id enum if you add/delete an item in the enum.
*/
-#define N_CSS_TPG_IDS (IA_CSS_TPG_ID2+1)
+#define N_CSS_TPG_IDS (IA_CSS_TPG_ID2 + 1)
/* Enumerate the TPG modes.
*/
struct ia_css_state_memory_offsets;
/* Virtual address within the CSS address space. */
-typedef uint32_t ia_css_ptr;
+typedef u32 ia_css_ptr;
/* Generic resolution structure.
*/
struct ia_css_resolution {
- uint32_t width; /** Width */
- uint32_t height; /** Height */
+ u32 width; /** Width */
+ u32 height; /** Height */
};
/* Generic coordinate structure.
*/
struct ia_css_coordinate {
- int32_t x; /** Value of a coordinate on the horizontal axis */
- int32_t y; /** Value of a coordinate on the vertical axis */
+ s32 x; /** Value of a coordinate on the horizontal axis */
+ s32 y; /** Value of a coordinate on the vertical axis */
};
/* Vector with signed values. This is used to indicate motion for
* Digital Image Stabilization.
*/
struct ia_css_vector {
- int32_t x; /** horizontal motion (in pixels) */
- int32_t y; /** vertical motion (in pixels) */
+ s32 x; /** horizontal motion (in pixels) */
+ s32 y; /** vertical motion (in pixels) */
};
/* Short hands */
/* CSS data descriptor */
struct ia_css_data {
ia_css_ptr address; /** CSS virtual address */
- uint32_t size; /** Disabled if 0 */
+ u32 size; /** Disabled if 0 */
};
/* Host data descriptor */
struct ia_css_host_data {
char *address; /** Host address */
- uint32_t size; /** Disabled if 0 */
+ u32 size; /** Disabled if 0 */
};
/* ISP data descriptor */
struct ia_css_isp_data {
- uint32_t address; /** ISP address */
- uint32_t size; /** Disabled if 0 */
+ u32 address; /** ISP address */
+ u32 size; /** Disabled if 0 */
};
/* Shading Correction types. */
*/
struct {
#ifndef ISP2401
- uint32_t enable; /** Shading correction enabled.
+ u32 enable; /** Shading correction enabled.
0:disabled, 1:enabled */
- uint32_t num_hor_grids; /** Number of data points per line
+ u32 num_hor_grids; /** Number of data points per line
per color on shading table. */
- uint32_t num_ver_grids; /** Number of lines of data points
+ u32 num_ver_grids; /** Number of lines of data points
per color on shading table. */
- uint32_t bqs_per_grid_cell; /** Grid cell size
+ u32 bqs_per_grid_cell; /** Grid cell size
in BQ(Bayer Quad) unit.
(1BQ means {Gr,R,B,Gb}(2x2 pixels).)
Valid values are 8,16,32,64. */
#else
- uint32_t num_hor_grids; /** Number of data points per line per color on shading table. */
- uint32_t num_ver_grids; /** Number of lines of data points per color on shading table. */
- uint32_t bqs_per_grid_cell; /** Grid cell size in BQ unit.
+ u32 num_hor_grids; /** Number of data points per line per color on shading table. */
+ u32 num_ver_grids; /** Number of lines of data points per color on shading table. */
+ u32 bqs_per_grid_cell; /** Grid cell size in BQ unit.
NOTE: bqs = size in BQ(Bayer Quad) unit.
1BQ means {Gr,R,B,Gb} (2x2 pixels).
Horizontal 1 bqs corresponds to horizontal 2 pixels.
Vertical 1 bqs corresponds to vertical 2 pixels. */
#endif
- uint32_t bayer_scale_hor_ratio_in;
- uint32_t bayer_scale_hor_ratio_out;
+ u32 bayer_scale_hor_ratio_in;
+ u32 bayer_scale_hor_ratio_out;
#ifndef ISP2401
/** Horizontal ratio of bayer scaling
between input width and output width, for the scaling
output_width = input_width * bayer_scale_hor_ratio_out
/ bayer_scale_hor_ratio_in + 0.5 */
#endif
- uint32_t bayer_scale_ver_ratio_in;
- uint32_t bayer_scale_ver_ratio_out;
+ u32 bayer_scale_ver_ratio_in;
+ u32 bayer_scale_ver_ratio_out;
#ifndef ISP2401
/** Vertical ratio of bayer scaling
between input height and output height, for the scaling
which should be done before shading correction.
output_height = input_height * bayer_scale_ver_ratio_out
/ bayer_scale_ver_ratio_in */
- uint32_t sc_bayer_origin_x_bqs_on_shading_table;
+ u32 sc_bayer_origin_x_bqs_on_shading_table;
/** X coordinate (in bqs) of bayer origin on shading table.
This indicates the left-most pixel of bayer
(not include margin) inputted to the shading correction.
This corresponds to the left-most pixel of bayer
inputted to isp from sensor. */
- uint32_t sc_bayer_origin_y_bqs_on_shading_table;
+ u32 sc_bayer_origin_y_bqs_on_shading_table;
/** Y coordinate (in bqs) of bayer origin on shading table.
This indicates the top pixel of bayer
(not include margin) inputted to the shading correction.
* that is visible for user
* @{
*/
- uint32_t isp_in_width;
- uint32_t isp_in_height;
+ u32 isp_in_width;
+ u32 isp_in_height;
/* @}*/
struct ia_css_3a_grid_info s3a_grid; /** 3A grid info */
* advanced ISP can correct for these imperfections using this table.
*/
struct ia_css_morph_table {
- uint32_t enable; /** To disable GDC, set this field to false. The
+ u32 enable; /** To disable GDC, set this field to false. The
coordinates fields can be set to NULL in this case. */
- uint32_t height; /** Table height */
- uint32_t width; /** Table width */
- uint16_t *coordinates_x[IA_CSS_MORPH_TABLE_NUM_PLANES];
+ u32 height; /** Table height */
+ u32 width; /** Table width */
+ u16 *coordinates_x[IA_CSS_MORPH_TABLE_NUM_PLANES];
/** X coordinates that describe the sensor imperfection */
- uint16_t *coordinates_y[IA_CSS_MORPH_TABLE_NUM_PLANES];
+ u16 *coordinates_y[IA_CSS_MORPH_TABLE_NUM_PLANES];
/** Y coordinates that describe the sensor imperfection */
};
struct ia_css_dvs_6axis_config {
unsigned int exp_id;
/** Exposure ID, see ia_css_event_public.h for more detail */
- uint32_t width_y;
- uint32_t height_y;
- uint32_t width_uv;
- uint32_t height_uv;
- uint32_t *xcoords_y;
- uint32_t *ycoords_y;
- uint32_t *xcoords_uv;
- uint32_t *ycoords_uv;
+ u32 width_y;
+ u32 height_y;
+ u32 width_uv;
+ u32 height_uv;
+ u32 *xcoords_y;
+ u32 *ycoords_y;
+ u32 *xcoords_uv;
+ u32 *ycoords_uv;
};
/**
* This specifies the coordinates (x,y)
*/
struct ia_css_point {
- int32_t x; /** x coordinate */
- int32_t y; /** y coordinate */
+ s32 x; /** x coordinate */
+ s32 y; /** y coordinate */
};
/**
* y + height <= effective input height
*/
struct ia_css_dz_config {
- uint32_t dx; /** Horizontal zoom factor */
- uint32_t dy; /** Vertical zoom factor */
+ u32 dx; /** Horizontal zoom factor */
+ u32 dy; /** Vertical zoom factor */
struct ia_css_region zoom_region; /** region for zoom */
};
struct ia_css_capture_config {
enum ia_css_capture_mode mode; /** Still capture mode */
- uint32_t enable_xnr; /** Enable/disable XNR */
- uint32_t enable_raw_output;
+ u32 enable_xnr; /** Enable/disable XNR */
+ u32 enable_raw_output;
bool enable_capture_pp_bli; /** Enable capture_pp_bli mode */
};
.mode = IA_CSS_CAPTURE_MODE_PRIMARY, \
}
-
/* ISP filter configuration. This is a collection of configurations
* for each of the ISP filters (modules).
*
struct ia_css_output_config *output_config_display; /** Viewfinder/display output mirroring, flipping (optional) */
struct ia_css_frame *output_frame; /** Output frame the config is to be applied to (optional) */
- uint32_t isp_config_id; /** Unique ID to track which config was actually applied to a particular frame */
+ u32 isp_config_id; /** Unique ID to track which config was actually applied to a particular frame */
};
#endif /* _IA_CSS_TYPES_H */
#ifndef __IA_CSS_VERSION_DATA_H
#define __IA_CSS_VERSION_DATA_H
-
#ifndef ISP2401
#define CSS_VERSION_STRING "REL:20150521_21.4_0539; API:2.1.15.3; GIT:irci_candrpv_0415_20150504_35b345#35b345be52ac575f8934abb3a88fea26a94e7343; SDK:/nfs/iir/disks/iir_hivepackages_003/iir_hivepkgs_disk017/Css_Mizuchi/packages/Css_Mizuchi/int_css_mizuchi_20140829_1053; USER:viedifw; "
#else
#define CSS_VERSION_STRING "REL:20150911_37.5_1652; API:2.1.20.9; GIT:irci___#ebf437d53a8951bb7ff6d13fdb7270dab393a92a; SDK:; USER:viedifw; "
#endif
-
#endif
-
const struct ia_css_aa_config default_baa_config = {
8191 /* default should be 0 */
};
-
#include "type_support.h"
struct sh_css_isp_aa_params {
- int32_t strength;
+ s32 strength;
};
#endif /* __IA_CSS_AA_PARAM_H */
* CSS-API header file for Anti-Aliasing parameters.
*/
-
/* Anti-Aliasing configuration.
*
* This structure is used both for YUV AA and Bayer AA.
* ISP2: BAA2 is used.
*/
struct ia_css_aa_config {
- uint16_t strength; /** Strength of the filter.
+ u16 strength; /** Strength of the filter.
u0.13, [0,8191],
default/ineffective 0 */
};
#endif /* __IA_CSS_AA2_TYPES_H */
-
ia_css_anr_encode(
struct sh_css_isp_anr_params *to,
const struct ia_css_anr_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->threshold = from->threshold;
void
ia_css_anr_dump(
const struct sh_css_isp_anr_params *anr,
- unsigned level)
+ unsigned int level)
{
if (!anr) return;
ia_css_debug_dtrace(level, "Advance Noise Reduction:\n");
void
ia_css_anr_debug_dtrace(
const struct ia_css_anr_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
"config.threshold=%d\n",
config->threshold);
}
-
ia_css_anr_encode(
struct sh_css_isp_anr_params *to,
const struct ia_css_anr_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_anr_dump(
const struct sh_css_isp_anr_params *anr,
- unsigned level);
+ unsigned int level);
void
ia_css_anr_debug_dtrace(
- const struct ia_css_anr_config *config, unsigned level)
+ const struct ia_css_anr_config *config, unsigned int level)
;
#endif /* __IA_CSS_ANR_HOST_H */
/* ANR (Advanced Noise Reduction) */
struct sh_css_isp_anr_params {
- int32_t threshold;
+ s32 threshold;
};
#endif /* __IA_CSS_ANR_PARAM_H */
/* Application specific DMA settings */
#define ANR_BPP 10
-#define ANR_ELEMENT_BITS ((CEIL_DIV(ANR_BPP, 8))*8)
+#define ANR_ELEMENT_BITS ((CEIL_DIV(ANR_BPP, 8)) * 8)
/* Advanced Noise Reduction configuration.
* This is also known as Low-Light.
*/
struct ia_css_anr_config {
- int32_t threshold; /** Threshold */
- int32_t thresholds[4*4*4];
- int32_t factors[3];
+ s32 threshold; /** Threshold */
+ s32 thresholds[4 * 4 * 4];
+ s32 factors[3];
};
#endif /* __IA_CSS_ANR_TYPES_H */
-
const struct ia_css_anr_thres *from,
size_t size)
{
- unsigned i;
+ unsigned int i;
(void)size;
for (i = 0; i < ANR_PARAM_SIZE; i++) {
- unsigned j;
+ unsigned int j;
+
for (j = 0; j < ISP_VEC_NELEMS; j++) {
- to->data[i][j] = from->data[i*ISP_VEC_NELEMS+j];
+ to->data[i][j] = from->data[i * ISP_VEC_NELEMS + j];
}
}
}
void
ia_css_anr2_debug_dtrace(
const struct ia_css_anr_thres *config,
- unsigned level)
+ unsigned int level)
{
(void)config;
(void)level;
}
-
void
ia_css_anr2_debug_dtrace(
- const struct ia_css_anr_thres *config, unsigned level)
+ const struct ia_css_anr_thres *config, unsigned int level)
;
#endif /* __IA_CSS_ANR2_HOST_H */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
#endif
-
/* Advanced Noise Reduction (ANR) thresholds */
struct ia_css_anr_thres {
- int16_t data[13*64];
+ s16 data[13 * 64];
};
#endif /* __IA_CSS_ANR2_TYPES_H */
-
/* Advanced Noise Reduction (ANR) thresholds */
struct ia_css_isp_anr2_params {
- VMEM_ARRAY(data, ANR_PARAM_SIZE*ISP_VEC_NELEMS);
+ VMEM_ARRAY(data, ANR_PARAM_SIZE * ISP_VEC_NELEMS);
};
#endif /* __IA_CSS_ANR2_PARAM_H */
/*
* No weighted histogram, hence no grid definition
*/
- if(!hmem_buf)
+ if (!hmem_buf)
return;
assert(sizeof_hmem(HMEM0_ID) == sizeof(*hmem_buf));
ia_css_bh_encode(
struct sh_css_isp_bh_params *to,
const struct ia_css_3a_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
/* coefficients to calculate Y */
ia_css_bh_encode(
struct sh_css_isp_bh_params *to,
const struct ia_css_3a_config *from,
- unsigned size);
+ unsigned int size);
#endif /* __IA_CSS_BH_HOST_H */
/* AE (3A Support) */
struct sh_css_isp_bh_params {
/* coefficients to calculate Y */
- int32_t y_coef_r;
- int32_t y_coef_g;
- int32_t y_coef_b;
+ s32 y_coef_r;
+ s32 y_coef_g;
+ s32 y_coef_b;
};
/* This should be hmem_data_t, but that breaks the pipe generator */
struct sh_css_isp_bh_hmem_params {
- uint32_t bh[ISP_HIST_COMPONENTS][IA_CSS_HMEM_BH_UNIT_SIZE];
+ u32 bh[ISP_HIST_COMPONENTS][IA_CSS_HMEM_BH_UNIT_SIZE];
};
#endif /* __IA_CSS_HB_PARAM_H */
* Should be consistent with hmem.h
*/
#define IA_CSS_HMEM_BH_TABLE_SIZE ISP_HIST_DEPTH
-#define IA_CSS_HMEM_BH_UNIT_SIZE (ISP_HIST_DEPTH/ISP_HIST_COMPONENTS)
+#define IA_CSS_HMEM_BH_UNIT_SIZE (ISP_HIST_DEPTH / ISP_HIST_COMPONENTS)
#define BH_COLOR_R (0)
#define BH_COLOR_G (1)
/* BH table */
struct ia_css_bh_table {
- uint32_t hmem[ISP_HIST_COMPONENTS][IA_CSS_HMEM_BH_UNIT_SIZE];
+ u32 hmem[ISP_HIST_COMPONENTS][IA_CSS_HMEM_BH_UNIT_SIZE];
};
#endif /* __IA_CSS_BH_TYPES_H */
-
-
#include <assert_support.h>
#define BNLM_DIV_LUT_SIZE (12)
-static const int32_t div_lut_nearests[BNLM_DIV_LUT_SIZE] = {
+static const s32 div_lut_nearests[BNLM_DIV_LUT_SIZE] = {
0, 454, 948, 1484, 2070, 2710, 3412, 4184, 5035, 5978, 7025, 8191
};
-static const int32_t div_lut_slopes[BNLM_DIV_LUT_SIZE] = {
+static const s32 div_lut_slopes[BNLM_DIV_LUT_SIZE] = {
-7760, -6960, -6216, -5536, -4912, -4344, -3832, -3360, -2936, -2552, -2208, -2208
};
-static const int32_t div_lut_intercepts[BNLM_DIV_LUT_SIZE] = {
+static const s32 div_lut_intercepts[BNLM_DIV_LUT_SIZE] = {
8184, 7752, 7336, 6928, 6536, 6152, 5776, 5416, 5064, 4728, 4408, 4408
};
*/
assert((lut_size >= 2) && (lut_size <= block_size));
/* array lut_thr has (lut_size-1) entries */
- for (i = 0; i < lut_size-2; i++) {
+ for (i = 0; i < lut_size - 2; i++) {
/* Check if the lut_thr is monotonically increasing */
- assert(lut_thr[i] <= lut_thr[i+1]);
+ assert(lut_thr[i] <= lut_thr[i + 1]);
}
/* Initialize */
/* Copy data from first block to all blocks */
for (blk = 1; blk < total_blocks; blk++) {
u32 blk_offset = blk * block_size;
+
for (i = 1; i < lut_size; i++) {
lut->thr[0][blk_offset + i] = lut->thr[0][i];
lut->val[0][blk_offset + i] = lut->val[0][i];
bnlm_lut_encode(&to->div_lut, div_lut_nearests, div_lut_slopes, BNLM_DIV_LUT_SIZE);
memset(to->div_lut_intercepts, 0, sizeof(to->div_lut_intercepts));
- for(i = 0; i < BNLM_DIV_LUT_SIZE; i++) {
+ for (i = 0; i < BNLM_DIV_LUT_SIZE; i++) {
to->div_lut_intercepts[0][i] = div_lut_intercepts[i];
}
memset(to->power_of_2, 0, sizeof(to->power_of_2));
- for (i = 0; i < (ISP_VEC_ELEMBITS-1); i++) {
+ for (i = 0; i < (ISP_VEC_ELEMBITS - 1); i++) {
to->power_of_2[0][i] = 1 << i;
}
}
void
ia_css_bnlm_debug_trace(
const struct ia_css_bnlm_config *config,
- unsigned level)
+ unsigned int level)
{
if (!config)
return;
/* ToDo: print traces for LUTs */
#endif /* IA_CSS_NO_DEBUG */
-
}
void
ia_css_bnlm_debug_trace(
const struct ia_css_bnlm_config *config,
- unsigned level);
+ unsigned int level);
#endif
#endif /* __IA_CSS_BNLM_HOST_H */
/* LUTs used for division approximiation */
struct bnlm_lut div_lut;
+
VMEM_ARRAY(div_lut_intercepts, ISP_VEC_NELEMS);
/* 240x does not have an ISP instruction to left shift each element of a
/* BNLM ISP parameters */
struct bnlm_dmem_params {
bool rad_enable;
- int32_t rad_x_origin;
- int32_t rad_y_origin;
- int32_t avg_min_th;
- int32_t max_min_th;
-
- int32_t exp_coeff_a;
- uint32_t exp_coeff_b;
- int32_t exp_coeff_c;
- uint32_t exp_exponent;
+ s32 rad_x_origin;
+ s32 rad_y_origin;
+ s32 avg_min_th;
+ s32 max_min_th;
+
+ s32 exp_coeff_a;
+ u32 exp_coeff_b;
+ s32 exp_coeff_c;
+ u32 exp_exponent;
};
#endif /* __IA_CSS_BNLM_PARAM_H */
*/
struct ia_css_bnlm_config {
bool rad_enable; /** Enable a radial dependency in a weight calculation */
- int32_t rad_x_origin; /** Initial x coordinate for a radius calculation */
- int32_t rad_y_origin; /** Initial x coordinate for a radius calculation */
+ s32 rad_x_origin; /** Initial x coordinate for a radius calculation */
+ s32 rad_y_origin; /** Initial x coordinate for a radius calculation */
/* a threshold for average of weights if this < Th, do not denoise pixel */
- int32_t avg_min_th;
+ s32 avg_min_th;
/* minimum weight for denoising if max < th, do not denoise pixel */
- int32_t max_min_th;
+ s32 max_min_th;
/**@{*/
/* Coefficient for approximation, in the form of (1 + x / N)^N,
* that fits the first-order exp() to default exp_lut in BNLM sheet
* */
- int32_t exp_coeff_a;
- uint32_t exp_coeff_b;
- int32_t exp_coeff_c;
- uint32_t exp_exponent;
+ s32 exp_coeff_a;
+ u32 exp_coeff_b;
+ s32 exp_coeff_c;
+ u32 exp_exponent;
/**@}*/
- int32_t nl_th[3]; /** Detail thresholds */
+ s32 nl_th[3]; /** Detail thresholds */
/* Index for n-th maximum candidate weight for each detail group */
- int32_t match_quality_max_idx[4];
+ s32 match_quality_max_idx[4];
/**@{*/
/* A lookup table for 1/sqrt(1+mu) approximation */
- int32_t mu_root_lut_thr[15];
- int32_t mu_root_lut_val[16];
+ s32 mu_root_lut_thr[15];
+ s32 mu_root_lut_val[16];
/**@}*/
/**@{*/
/* A lookup table for SAD normalization */
- int32_t sad_norm_lut_thr[15];
- int32_t sad_norm_lut_val[16];
+ s32 sad_norm_lut_thr[15];
+ s32 sad_norm_lut_val[16];
/**@}*/
/**@{*/
/* A lookup table that models a weight's dependency on textures */
- int32_t sig_detail_lut_thr[15];
- int32_t sig_detail_lut_val[16];
+ s32 sig_detail_lut_thr[15];
+ s32 sig_detail_lut_val[16];
/**@}*/
/**@{*/
/* A lookup table that models a weight's dependency on a pixel's radial distance */
- int32_t sig_rad_lut_thr[15];
- int32_t sig_rad_lut_val[16];
+ s32 sig_rad_lut_thr[15];
+ s32 sig_rad_lut_val[16];
/**@}*/
/**@{*/
/* A lookup table to control denoise power depending on a pixel's radial distance */
- int32_t rad_pow_lut_thr[15];
- int32_t rad_pow_lut_val[16];
+ s32 rad_pow_lut_thr[15];
+ s32 rad_pow_lut_val[16];
/**@}*/
/**@{*/
/* Non linear transfer functions to calculate the blending coefficient depending on detail group */
/* detail group 0 */
/**@{*/
- int32_t nl_0_lut_thr[15];
- int32_t nl_0_lut_val[16];
+ s32 nl_0_lut_thr[15];
+ s32 nl_0_lut_val[16];
/**@}*/
/**@{*/
/* detail group 1 */
- int32_t nl_1_lut_thr[15];
- int32_t nl_1_lut_val[16];
+ s32 nl_1_lut_thr[15];
+ s32 nl_1_lut_val[16];
/**@}*/
/**@{*/
/* detail group 2 */
- int32_t nl_2_lut_thr[15];
- int32_t nl_2_lut_val[16];
+ s32 nl_2_lut_thr[15];
+ s32 nl_2_lut_val[16];
/**@}*/
/**@{*/
/* detail group 3 */
- int32_t nl_3_lut_thr[15];
- int32_t nl_3_lut_val[16];
+ s32 nl_3_lut_thr[15];
+ s32 nl_3_lut_val[16];
/**@}*/
/**@}*/
};
void
ia_css_bnr2_2_debug_dtrace(
const struct ia_css_bnr2_2_config *bnr,
- unsigned level)
+ unsigned int level)
{
if (!bnr)
return;
void
ia_css_bnr2_2_debug_dtrace(
const struct ia_css_bnr2_2_config *config,
- unsigned level);
+ unsigned int level);
#endif
#endif /* __IA_CSS_BNR2_2_HOST_H */
/* BNR (Bayer Noise Reduction) ISP parameters */
struct sh_css_isp_bnr2_2_params {
- int32_t d_var_gain_r;
- int32_t d_var_gain_g;
- int32_t d_var_gain_b;
- int32_t d_var_gain_slope_r;
- int32_t d_var_gain_slope_g;
- int32_t d_var_gain_slope_b;
- int32_t n_var_gain_r;
- int32_t n_var_gain_g;
- int32_t n_var_gain_b;
- int32_t n_var_gain_slope_r;
- int32_t n_var_gain_slope_g;
- int32_t n_var_gain_slope_b;
- int32_t dir_thres;
- int32_t dir_thres_w;
- int32_t var_offset_coef;
- int32_t dir_gain;
- int32_t detail_gain;
- int32_t detail_gain_divisor;
- int32_t detail_level_offset;
- int32_t d_var_th_min;
- int32_t d_var_th_max;
- int32_t n_var_th_min;
- int32_t n_var_th_max;
+ s32 d_var_gain_r;
+ s32 d_var_gain_g;
+ s32 d_var_gain_b;
+ s32 d_var_gain_slope_r;
+ s32 d_var_gain_slope_g;
+ s32 d_var_gain_slope_b;
+ s32 n_var_gain_r;
+ s32 n_var_gain_g;
+ s32 n_var_gain_b;
+ s32 n_var_gain_slope_r;
+ s32 n_var_gain_slope_g;
+ s32 n_var_gain_slope_b;
+ s32 dir_thres;
+ s32 dir_thres_w;
+ s32 var_offset_coef;
+ s32 dir_gain;
+ s32 detail_gain;
+ s32 detail_gain_divisor;
+ s32 detail_level_offset;
+ s32 d_var_th_min;
+ s32 d_var_th_max;
+ s32 n_var_th_min;
+ s32 n_var_th_max;
};
#endif /* __IA_CSS_BNR2_2_PARAM_H */
struct ia_css_bnr2_2_config {
/**@{*/
/* Directional variance gain for R/G/B components in dark region */
- int32_t d_var_gain_r;
- int32_t d_var_gain_g;
- int32_t d_var_gain_b;
+ s32 d_var_gain_r;
+ s32 d_var_gain_g;
+ s32 d_var_gain_b;
/**@}*/
/**@{*/
/* Slope of Directional variance gain between dark and bright region */
- int32_t d_var_gain_slope_r;
- int32_t d_var_gain_slope_g;
- int32_t d_var_gain_slope_b;
+ s32 d_var_gain_slope_r;
+ s32 d_var_gain_slope_g;
+ s32 d_var_gain_slope_b;
/**@}*/
/**@{*/
/* Non-Directional variance gain for R/G/B components in dark region */
- int32_t n_var_gain_r;
- int32_t n_var_gain_g;
- int32_t n_var_gain_b;
+ s32 n_var_gain_r;
+ s32 n_var_gain_g;
+ s32 n_var_gain_b;
/**@}*/
/**@{*/
/* Slope of Non-Directional variance gain between dark and bright region */
- int32_t n_var_gain_slope_r;
- int32_t n_var_gain_slope_g;
- int32_t n_var_gain_slope_b;
+ s32 n_var_gain_slope_r;
+ s32 n_var_gain_slope_g;
+ s32 n_var_gain_slope_b;
/**@}*/
- int32_t dir_thres; /** Threshold for directional filtering */
- int32_t dir_thres_w; /** Threshold width for directional filtering */
- int32_t var_offset_coef; /** Variance offset coefficient */
- int32_t dir_gain; /** Gain for directional coefficient */
- int32_t detail_gain; /** Gain for low contrast texture control */
- int32_t detail_gain_divisor; /** Gain divisor for low contrast texture control */
- int32_t detail_level_offset; /** Bias value for low contrast texture control */
- int32_t d_var_th_min; /** Minimum clipping value for directional variance*/
- int32_t d_var_th_max; /** Maximum clipping value for diretional variance*/
- int32_t n_var_th_min; /** Minimum clipping value for non-directional variance*/
- int32_t n_var_th_max; /** Maximum clipping value for non-directional variance*/
+ s32 dir_thres; /** Threshold for directional filtering */
+ s32 dir_thres_w; /** Threshold width for directional filtering */
+ s32 var_offset_coef; /** Variance offset coefficient */
+ s32 dir_gain; /** Gain for directional coefficient */
+ s32 detail_gain; /** Gain for low contrast texture control */
+ s32 detail_gain_divisor; /** Gain divisor for low contrast texture control */
+ s32 detail_level_offset; /** Bias value for low contrast texture control */
+ s32 d_var_th_min; /** Minimum clipping value for directional variance*/
+ s32 d_var_th_max; /** Maximum clipping value for diretional variance*/
+ s32 n_var_th_min; /** Minimum clipping value for non-directional variance*/
+ s32 n_var_th_max; /** Maximum clipping value for non-directional variance*/
};
#endif /* __IA_CSS_BNR2_2_TYPES_H */
ia_css_bnr_encode(
struct sh_css_isp_bnr_params *to,
const struct ia_css_nr_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
/* BNR (Bayer Noise Reduction) */
uDIGIT_FITTING(from->bnr_gain, 16, SH_CSS_BNR_GAIN_SHIFT);
to->gain_dir =
uDIGIT_FITTING(from->bnr_gain, 16, SH_CSS_BNR_GAIN_SHIFT);
- to->clip = uDIGIT_FITTING((unsigned)16384, 16, SH_CSS_BAYER_BITS);
+ to->clip = uDIGIT_FITTING(16384U, 16, SH_CSS_BAYER_BITS);
}
void
ia_css_bnr_dump(
const struct sh_css_isp_bnr_params *bnr,
- unsigned level)
+ unsigned int level)
{
if (!bnr) return;
ia_css_debug_dtrace(level, "Bayer Noise Reduction:\n");
ia_css_bnr_encode(
struct sh_css_isp_bnr_params *to,
const struct ia_css_nr_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_bnr_dump(
const struct sh_css_isp_bnr_params *bnr,
- unsigned level);
+ unsigned int level);
#endif /* __IA_CSS_DP_HOST_H */
/* BNR (Bayer Noise Reduction) */
struct sh_css_isp_bnr_params {
- int32_t gain_all;
- int32_t gain_dir;
- int32_t threshold_low;
- int32_t threshold_width_log2;
- int32_t threshold_width;
- int32_t clip;
+ s32 gain_all;
+ s32 gain_dir;
+ s32 threshold_low;
+ s32 threshold_width_log2;
+ s32 threshold_width;
+ s32 clip;
};
#endif /* __IA_CSS_BNR_PARAM_H */
/* keep the interface here, it is not enabled yet because host doesn't know the size of individual state */
void
ia_css_init_cnr_state(
- void/*struct sh_css_isp_cnr_vmem_state*/ *state,
+ void/*struct sh_css_isp_cnr_vmem_state*/ * state,
size_t size)
{
memset(state, 0, size);
void
ia_css_init_cnr_state(
- void/*struct sh_css_isp_cnr_vmem_state*/ *state,
+ void/*struct sh_css_isp_cnr_vmem_state*/ * state,
size_t size);
#endif /* __IA_CSS_CNR_HOST_H */
ia_css_cnr_encode(
struct sh_css_isp_cnr_params *to,
const struct ia_css_cnr_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->coring_u = from->coring_u;
void
ia_css_cnr_dump(
const struct sh_css_isp_cnr_params *cnr,
- unsigned level);
+ unsigned int level);
void
ia_css_cnr_debug_dtrace(
const struct ia_css_cnr_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
- "config.coring_u=%d, config.coring_v=%d, "
- "config.sense_gain_vy=%d, config.sense_gain_hy=%d, "
- "config.sense_gain_vu=%d, config.sense_gain_hu=%d, "
- "config.sense_gain_vv=%d, config.sense_gain_hv=%d\n",
+ "config.coring_u=%d, config.coring_v=%d, config.sense_gain_vy=%d, config.sense_gain_hy=%d, config.sense_gain_vu=%d, config.sense_gain_hu=%d, config.sense_gain_vv=%d, config.sense_gain_hv=%d\n",
config->coring_u, config->coring_v,
config->sense_gain_vy, config->sense_gain_hy,
config->sense_gain_vu, config->sense_gain_hu,
void
ia_css_init_cnr2_state(
- void/*struct sh_css_isp_cnr_vmem_state*/ *state,
+ void/*struct sh_css_isp_cnr_vmem_state*/ * state,
size_t size)
{
memset(state, 0, size);
ia_css_cnr_encode(
struct sh_css_isp_cnr_params *to,
const struct ia_css_cnr_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_cnr_dump(
const struct sh_css_isp_cnr_params *cnr,
- unsigned level);
+ unsigned int level);
void
ia_css_cnr_debug_dtrace(
const struct ia_css_cnr_config *config,
- unsigned level);
+ unsigned int level);
void
ia_css_init_cnr2_state(
- void/*struct sh_css_isp_cnr_vmem_state*/ *state,
+ void/*struct sh_css_isp_cnr_vmem_state*/ * state,
size_t size);
#endif /* __IA_CSS_CNR2_HOST_H */
/* CNR (Chroma Noise Reduction) */
struct sh_css_isp_cnr_params {
- int32_t coring_u;
- int32_t coring_v;
- int32_t sense_gain_vy;
- int32_t sense_gain_vu;
- int32_t sense_gain_vv;
- int32_t sense_gain_hy;
- int32_t sense_gain_hu;
- int32_t sense_gain_hv;
+ s32 coring_u;
+ s32 coring_v;
+ s32 sense_gain_vy;
+ s32 sense_gain_vu;
+ s32 sense_gain_vv;
+ s32 sense_gain_hy;
+ s32 sense_gain_hu;
+ s32 sense_gain_hv;
};
#endif /* __IA_CSS_CNR2_PARAM_H */
* ISP2: CNR2 is used for Still.
*/
struct ia_css_cnr_config {
- uint16_t coring_u; /** Coring level of U.
+ u16 coring_u; /** Coring level of U.
u0.13, [0,8191], default/ineffective 0 */
- uint16_t coring_v; /** Coring level of V.
+ u16 coring_v; /** Coring level of V.
u0.13, [0,8191], default/ineffective 0 */
- uint16_t sense_gain_vy; /** Sensitivity of horizontal edge of Y.
+ u16 sense_gain_vy; /** Sensitivity of horizontal edge of Y.
u13.0, [0,8191], default 100, ineffective 8191 */
- uint16_t sense_gain_vu; /** Sensitivity of horizontal edge of U.
+ u16 sense_gain_vu; /** Sensitivity of horizontal edge of U.
u13.0, [0,8191], default 100, ineffective 8191 */
- uint16_t sense_gain_vv; /** Sensitivity of horizontal edge of V.
+ u16 sense_gain_vv; /** Sensitivity of horizontal edge of V.
u13.0, [0,8191], default 100, ineffective 8191 */
- uint16_t sense_gain_hy; /** Sensitivity of vertical edge of Y.
+ u16 sense_gain_hy; /** Sensitivity of vertical edge of Y.
u13.0, [0,8191], default 50, ineffective 8191 */
- uint16_t sense_gain_hu; /** Sensitivity of vertical edge of U.
+ u16 sense_gain_hu; /** Sensitivity of vertical edge of U.
u13.0, [0,8191], default 50, ineffective 8191 */
- uint16_t sense_gain_hv; /** Sensitivity of vertical edge of V.
+ u16 sense_gain_hv; /** Sensitivity of vertical edge of V.
u13.0, [0,8191], default 50, ineffective 8191 */
};
#endif /* __IA_CSS_CNR2_TYPES_H */
-
ia_css_conversion_encode(
struct sh_css_isp_conversion_params *to,
const struct ia_css_conversion_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->en = from->en;
ia_css_conversion_encode(
struct sh_css_isp_conversion_params *to,
const struct ia_css_conversion_config *from,
- unsigned size);
+ unsigned int size);
#ifdef ISP2401
/* workaround until code generation in isp_kernelparameters.host.c is fixed */
/* CONVERSION */
struct sh_css_isp_conversion_params {
- uint32_t en;
- uint32_t dummy0;
- uint32_t dummy1;
- uint32_t dummy2;
+ u32 en;
+ u32 dummy0;
+ u32 dummy1;
+ u32 dummy2;
};
#endif /* __IA_CSS_CONVERSION_PARAM_H */
*
*/
struct ia_css_conversion_config {
- uint32_t en; /** en parameter */
- uint32_t dummy0; /** dummy0 dummy parameter 0 */
- uint32_t dummy1; /** dummy1 dummy parameter 1 */
- uint32_t dummy2; /** dummy2 dummy parameter 2 */
+ u32 en; /** en parameter */
+ u32 dummy0; /** dummy0 dummy parameter 0 */
+ u32 dummy1; /** dummy1 dummy parameter 1 */
+ u32 dummy2; /** dummy2 dummy parameter 2 */
};
#endif /* __IA_CSS_CONVERSION_TYPES_H */
ia_css_copy_output_config(
struct sh_css_isp_copy_output_isp_config *to,
const struct ia_css_copy_output_configuration *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->enable = from->enable;
ia_css_configure_copy_output(binary, &config);
}
-
ia_css_copy_output_config(
struct sh_css_isp_copy_output_isp_config *to,
const struct ia_css_copy_output_configuration *from,
- unsigned size);
+ unsigned int size);
void
ia_css_copy_output_configure(
};
struct sh_css_isp_copy_output_isp_config {
- uint32_t enable;
+ u32 enable;
};
#endif /* __IA_CSS_COPY_PARAM_H */
ia_css_crop_encode(
struct sh_css_isp_crop_isp_params *to,
const struct ia_css_crop_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->crop_pos = from->crop_pos;
ia_css_crop_config(
struct sh_css_isp_crop_isp_config *to,
const struct ia_css_crop_configuration *from,
- unsigned size)
+ unsigned int size)
{
- unsigned elems_a = ISP_VEC_NELEMS;
+ unsigned int elems_a = ISP_VEC_NELEMS;
(void)size;
ia_css_dma_configure_from_info(&to->port_b, from->info);
to->width_a_over_b = elems_a / to->port_b.elems;
/* Assume divisiblity here, may need to generalize to fixed point. */
- assert (elems_a % to->port_b.elems == 0);
+ assert(elems_a % to->port_b.elems == 0);
}
void
ia_css_crop_encode(
struct sh_css_isp_crop_isp_params *to,
const struct ia_css_crop_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_crop_config(
struct sh_css_isp_crop_isp_config *to,
const struct ia_css_crop_configuration *from,
- unsigned size);
+ unsigned int size);
void
ia_css_crop_configure(
/* Crop frame */
struct sh_css_isp_crop_isp_config {
- uint32_t width_a_over_b;
+ u32 width_a_over_b;
struct dma_port_config port_b;
};
};
#endif /* __IA_CSS_CROP_TYPES_H */
-
ia_css_encode_cc(
struct sh_css_isp_csc_params *to,
const struct ia_css_cc_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
#ifndef IA_CSS_NO_DEBUG
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_encode_cc() enter:\n");
#endif
- to->m_shift = (int16_t) from->fraction_bits;
- to->m00 = (int16_t) from->matrix[0];
- to->m01 = (int16_t) from->matrix[1];
- to->m02 = (int16_t) from->matrix[2];
- to->m10 = (int16_t) from->matrix[3];
- to->m11 = (int16_t) from->matrix[4];
- to->m12 = (int16_t) from->matrix[5];
- to->m20 = (int16_t) from->matrix[6];
- to->m21 = (int16_t) from->matrix[7];
- to->m22 = (int16_t) from->matrix[8];
+ to->m_shift = (int16_t)from->fraction_bits;
+ to->m00 = (int16_t)from->matrix[0];
+ to->m01 = (int16_t)from->matrix[1];
+ to->m02 = (int16_t)from->matrix[2];
+ to->m10 = (int16_t)from->matrix[3];
+ to->m11 = (int16_t)from->matrix[4];
+ to->m12 = (int16_t)from->matrix[5];
+ to->m20 = (int16_t)from->matrix[6];
+ to->m21 = (int16_t)from->matrix[7];
+ to->m22 = (int16_t)from->matrix[8];
#ifndef IA_CSS_NO_DEBUG
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_encode_cc() leave:\n");
ia_css_csc_encode(
struct sh_css_isp_csc_params *to,
const struct ia_css_cc_config *from,
- unsigned size)
+ unsigned int size)
{
ia_css_encode_cc(to, from, size);
}
void
ia_css_cc_dump(
const struct sh_css_isp_csc_params *csc,
- unsigned level,
+ unsigned int level,
const char *name)
{
if (!csc) return;
void
ia_css_csc_dump(
const struct sh_css_isp_csc_params *csc,
- unsigned level)
+ unsigned int level)
{
ia_css_cc_dump(csc, level, "Color Space Conversion");
}
void
ia_css_cc_config_debug_dtrace(
const struct ia_css_cc_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
- "config.m[0]=%d, "
- "config.m[1]=%d, config.m[2]=%d, "
- "config.m[3]=%d, config.m[4]=%d, "
- "config.m[5]=%d, config.m[6]=%d, "
- "config.m[7]=%d, config.m[8]=%d\n",
+ "config.m[0]=%d, config.m[1]=%d, config.m[2]=%d, config.m[3]=%d, config.m[4]=%d, config.m[5]=%d, config.m[6]=%d, config.m[7]=%d, config.m[8]=%d\n",
config->matrix[0],
config->matrix[1], config->matrix[2],
config->matrix[3], config->matrix[4],
config->matrix[7], config->matrix[8]);
}
#endif
-
ia_css_encode_cc(
struct sh_css_isp_csc_params *to,
const struct ia_css_cc_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_csc_encode(
struct sh_css_isp_csc_params *to,
const struct ia_css_cc_config *from,
- unsigned size);
+ unsigned int size);
#ifndef IA_CSS_NO_DEBUG
void
ia_css_cc_dump(
- const struct sh_css_isp_csc_params *csc, unsigned level,
+ const struct sh_css_isp_csc_params *csc, unsigned int level,
const char *name);
void
ia_css_csc_dump(
const struct sh_css_isp_csc_params *csc,
- unsigned level);
+ unsigned int level);
void
ia_css_cc_config_debug_dtrace(
const struct ia_css_cc_config *config,
- unsigned level);
+ unsigned int level);
#define ia_css_csc_debug_dtrace ia_css_cc_config_debug_dtrace
#endif
#include "type_support.h"
/* CSC (Color Space Conversion) */
struct sh_css_isp_csc_params {
- uint16_t m_shift;
- int16_t m00;
- int16_t m01;
- int16_t m02;
- int16_t m10;
- int16_t m11;
- int16_t m12;
- int16_t m20;
- int16_t m21;
- int16_t m22;
+ u16 m_shift;
+ s16 m00;
+ s16 m01;
+ s16 m02;
+ s16 m10;
+ s16 m11;
+ s16 m12;
+ s16 m20;
+ s16 m21;
+ s16 m22;
};
-
#endif /* __IA_CSS_CSC_PARAM_H */
*
* default/ineffective:
* 1. YCgCo -> YUV
- * 1 0.174 0.185
- * 0 -0.66252 -0.66874
- * 0 -0.83738 0.58131
+ * 1 0.174 0.185
+ * 0 -0.66252 -0.66874
+ * 0 -0.83738 0.58131
*
* fraction_bits = 12
- * 4096 713 758
- * 0 -2714 -2739
- * 0 -3430 2381
+ * 4096 713 758
+ * 0 -2714 -2739
+ * 0 -3430 2381
*
* 2. YCgCo -> RGB
- * 1 -1 1
- * 1 1 0
- * 1 -1 -1
+ * 1 -1 1
+ * 1 1 0
+ * 1 -1 -1
*
* fraction_bits = 12
- * 4096 -4096 4096
- * 4096 4096 0
- * 4096 -4096 -4096
+ * 4096 -4096 4096
+ * 4096 4096 0
+ * 4096 -4096 -4096
*
* 3. RGB -> YUV
* 0.299 0.587 0.114
- * -0.16874 -0.33126 0.5
- * 0.5 -0.41869 -0.08131
+ * -0.16874 -0.33126 0.5
+ * 0.5 -0.41869 -0.08131
*
* fraction_bits = 13
- * 2449 4809 934
- * -1382 -2714 4096
- * 4096 -3430 -666
+ * 2449 4809 934
+ * -1382 -2714 4096
+ * 4096 -3430 -666
*/
struct ia_css_cc_config {
- uint32_t fraction_bits;/** Fractional bits of matrix.
+ u32 fraction_bits;/** Fractional bits of matrix.
u8.0, [0,13] */
- int32_t matrix[3 * 3]; /** Conversion matrix.
+ s32 matrix[3 * 3]; /** Conversion matrix.
s[13-fraction_bits].[fraction_bits],
[-8192,8191] */
};
assert(y0 >= 0 && y0 <= max_dydx);
assert(y1 >= 0 && y1 <= max_dydx);
assert(x0 < x1);
- assert(dydx != NULL);
- assert(shift != NULL);
+ assert(dydx);
+ assert(shift);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ctc_gradient() enter:\n");
ia_css_ctc_encode(
struct sh_css_isp_ctc_params *to,
const struct ia_css_ctc_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->y0 = from->y0;
to->x3 = from->x3;
to->x4 = from->x4;
- ctc_gradient(&(to->dydx0),
- &(to->dydx0_shift),
+ ctc_gradient(&to->dydx0,
+ &to->dydx0_shift,
from->y1, from->y0,
from->x1, 0);
- ctc_gradient(&(to->dydx1),
- &(to->dydx1_shift),
+ ctc_gradient(&to->dydx1,
+ &to->dydx1_shift,
from->y2, from->y1,
from->x2, from->x1);
from->y4, from->y3,
from->x4, from->x3);
- ctc_gradient(&(to->dydx4),
- &(to->dydx4_shift),
+ ctc_gradient(&to->dydx4,
+ &to->dydx4_shift,
from->y5, from->y4,
SH_CSS_BAYER_MAXVAL, from->x4);
}
void
ia_css_ctc_dump(
const struct sh_css_isp_ctc_params *ctc,
- unsigned level);
+ unsigned int level);
ia_css_ctc_encode(
struct sh_css_isp_ctc_params *to,
const struct ia_css_ctc_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_ctc_dump(
const struct sh_css_isp_ctc_params *ctc,
- unsigned level);
+ unsigned int level);
#endif /* __IA_CSS_CTC1_5_HOST_H */
/* CTC (Color Tone Control) */
struct sh_css_isp_ctc_params {
- int32_t y0;
- int32_t y1;
- int32_t y2;
- int32_t y3;
- int32_t y4;
- int32_t y5;
- int32_t ce_gain_exp;
- int32_t x1;
- int32_t x2;
- int32_t x3;
- int32_t x4;
- int32_t dydx0;
- int32_t dydx0_shift;
- int32_t dydx1;
- int32_t dydx1_shift;
- int32_t dydx2;
- int32_t dydx2_shift;
- int32_t dydx3;
- int32_t dydx3_shift;
- int32_t dydx4;
- int32_t dydx4_shift;
+ s32 y0;
+ s32 y1;
+ s32 y2;
+ s32 y3;
+ s32 y4;
+ s32 y5;
+ s32 ce_gain_exp;
+ s32 x1;
+ s32 x2;
+ s32 x3;
+ s32 x4;
+ s32 dydx0;
+ s32 dydx0_shift;
+ s32 dydx1;
+ s32 dydx1_shift;
+ s32 dydx2;
+ s32 dydx2_shift;
+ s32 dydx3;
+ s32 dydx3_shift;
+ s32 dydx4;
+ s32 dydx4_shift;
};
#endif /* __IA_CSS_CTC1_5_PARAM_H */
if (dy < 0)
rounding = -rounding;
- slope = (int) (dy_shift + rounding) / dx;
+ slope = (int)(dy_shift + rounding) / dx;
/*the slope must lie within the range
(-max_slope-1) >= (dydx) >= (max_slope)
*/
- if (slope <= -max_slope-1) {
- dydx = -max_slope-1;
+ if (slope <= -max_slope - 1) {
+ dydx = -max_slope - 1;
} else if (slope >= max_slope) {
dydx = max_slope;
} else {
const struct ia_css_ctc2_config *from,
size_t size)
{
- unsigned i, j;
- const unsigned shffl_blck = 4;
- const unsigned length_zeros = 11;
+ unsigned int i, j;
+ const unsigned int shffl_blck = 4;
+ const unsigned int length_zeros = 11;
short dydx0, dydx1, dydx2, dydx3, dydx4;
(void)size;
for (j = 0; j < length_zeros; j++) {
to->y_x[0][(i << shffl_blck) + 5 + j] = 0;
to->y_y[0][(i << shffl_blck) + 5 + j] = 0;
- to->e_y_slope[0][(i << shffl_blck)+ 5 + j] = 0;
+ to->e_y_slope[0][(i << shffl_blck) + 5 + j] = 0;
}
}
}
/*DMEM Chroma params*/
struct ia_css_isp_ctc2_dmem_params {
-
/* Gains by UV(Chroma) under kneepoints uv_x0 and uv_x1*/
- int32_t uv_y0;
- int32_t uv_y1;
+ s32 uv_y0;
+ s32 uv_y1;
/* Kneepoints by UV(Chroma)- uv_x0 and uv_x1*/
- int32_t uv_x0;
- int32_t uv_x1;
+ s32 uv_x0;
+ s32 uv_x1;
/* Slope of line interconnecting uv_x0 -> uv_x1*/
- int32_t uv_dydx;
+ s32 uv_dydx;
};
#endif /* __IA_CSS_CTC2_PARAM_H */
* ISP261: CTC2 (CTC by Fast Approximate Distance)
*/
struct ia_css_ctc2_config {
-
/** Gains by Y(Luma) at Y =0.0,Y_X1, Y_X2, Y_X3, Y_X4 and Y_X5
* --default/ineffective value: 4096(0.5f)
*/
- int32_t y_y0;
- int32_t y_y1;
- int32_t y_y2;
- int32_t y_y3;
- int32_t y_y4;
- int32_t y_y5;
+ s32 y_y0;
+ s32 y_y1;
+ s32 y_y2;
+ s32 y_y3;
+ s32 y_y4;
+ s32 y_y5;
/* 1st-4th kneepoints by Y(Luma) --default/ineffective value:n/a
* requirement: 0.0 < y_x1 < y_x2 <y _x3 < y_x4 < 1.0
*/
- int32_t y_x1;
- int32_t y_x2;
- int32_t y_x3;
- int32_t y_x4;
+ s32 y_x1;
+ s32 y_x2;
+ s32 y_x3;
+ s32 y_x4;
/* Gains by UV(Chroma) under threholds uv_x0 and uv_x1
* --default/ineffective value: 4096(0.5f)
*/
- int32_t uv_y0;
- int32_t uv_y1;
+ s32 uv_y0;
+ s32 uv_y1;
/* Minimum and Maximum Thresholds by UV(Chroma)- uv_x0 and uv_x1
* --default/ineffective value: n/a
*/
- int32_t uv_x0;
- int32_t uv_x1;
+ s32 uv_x0;
+ s32 uv_x1;
};
#endif /* __IA_CSS_CTC2_TYPES_H */
ia_css_ctc_vamem_encode(
struct sh_css_isp_ctc_vamem_params *to,
const struct ia_css_ctc_table *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
- memcpy (&to->ctc, &from->data, sizeof(to->ctc));
+ memcpy(&to->ctc, &from->data, sizeof(to->ctc));
}
void
ia_css_ctc_debug_dtrace(
const struct ia_css_ctc_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
- "config.ce_gain_exp=%d, config.y0=%d, "
- "config.x1=%d, config.y1=%d, "
- "config.x2=%d, config.y2=%d, "
- "config.x3=%d, config.y3=%d, "
- "config.x4=%d, config.y4=%d\n",
+ "config.ce_gain_exp=%d, config.y0=%d, config.x1=%d, config.y1=%d, config.x2=%d, config.y2=%d, config.x3=%d, config.y3=%d, config.x4=%d, config.y4=%d\n",
config->ce_gain_exp, config->y0,
config->x1, config->y1,
config->x2, config->y2,
config->x3, config->y3,
config->x4, config->y4);
}
-
ia_css_ctc_vamem_encode(
struct sh_css_isp_ctc_vamem_params *to,
const struct ia_css_ctc_table *from,
- unsigned size);
+ unsigned int size);
void
ia_css_ctc_debug_dtrace(
- const struct ia_css_ctc_config *config, unsigned level)
+ const struct ia_css_ctc_config *config, unsigned int level)
;
#endif /* __IA_CSS_CTC_HOST_H */
#define SH_CSS_ISP_CTC_TABLE_SIZE_LOG2 IA_CSS_VAMEM_1_CTC_TABLE_SIZE_LOG2
#define SH_CSS_ISP_CTC_TABLE_SIZE IA_CSS_VAMEM_1_CTC_TABLE_SIZE
#else
-#error "VAMEM should be {VERSION1, VERSION2}"
+#error "VAMEM should be {VERSION1, VERSION2}"
#endif
#else
/* This should be vamem_data_t, but that breaks the pipe generator */
struct sh_css_isp_ctc_vamem_params {
- uint16_t ctc[SH_CSS_ISP_CTC_TABLE_SIZE];
+ u16 ctc[SH_CSS_ISP_CTC_TABLE_SIZE];
};
#endif /* __IA_CSS_CTC_PARAM_H */
default_ctc_table.vamem_type = 1IA_CSS_VAMEM_TYPE_1;
#endif
}
-
#ifndef __IA_CSS_CTC_TYPES_H
#define __IA_CSS_CTC_TYPES_H
+#include <linux/bitops.h>
+
/* @file
* CSS-API header file for Chroma Tone Control parameters.
*/
/* Number of elements in the CTC table. */
#define IA_CSS_VAMEM_1_CTC_TABLE_SIZE_LOG2 10
/* Number of elements in the CTC table. */
-#define IA_CSS_VAMEM_1_CTC_TABLE_SIZE (1U<<IA_CSS_VAMEM_1_CTC_TABLE_SIZE_LOG2)
+#define IA_CSS_VAMEM_1_CTC_TABLE_SIZE BIT(IA_CSS_VAMEM_1_CTC_TABLE_SIZE_LOG2)
/* Number of elements in the CTC table. */
#define IA_CSS_VAMEM_2_CTC_TABLE_SIZE_LOG2 8
/* Number of elements in the CTC table. */
-#define IA_CSS_VAMEM_2_CTC_TABLE_SIZE ((1U<<IA_CSS_VAMEM_2_CTC_TABLE_SIZE_LOG2) + 1)
+#define IA_CSS_VAMEM_2_CTC_TABLE_SIZE ((1U << IA_CSS_VAMEM_2_CTC_TABLE_SIZE_LOG2) + 1)
enum ia_css_vamem_type {
IA_CSS_VAMEM_TYPE_1,
* ISP2: CTC2 is used.
*/
struct ia_css_ctc_config {
- uint16_t y0; /** 1st kneepoint gain.
+ u16 y0; /** 1st kneepoint gain.
u[ce_gain_exp].[13-ce_gain_exp], [0,8191],
default/ineffective 4096(0.5) */
- uint16_t y1; /** 2nd kneepoint gain.
+ u16 y1; /** 2nd kneepoint gain.
u[ce_gain_exp].[13-ce_gain_exp], [0,8191],
default/ineffective 4096(0.5) */
- uint16_t y2; /** 3rd kneepoint gain.
+ u16 y2; /** 3rd kneepoint gain.
u[ce_gain_exp].[13-ce_gain_exp], [0,8191],
default/ineffective 4096(0.5) */
- uint16_t y3; /** 4th kneepoint gain.
+ u16 y3; /** 4th kneepoint gain.
u[ce_gain_exp].[13-ce_gain_exp], [0,8191],
default/ineffective 4096(0.5) */
- uint16_t y4; /** 5th kneepoint gain.
+ u16 y4; /** 5th kneepoint gain.
u[ce_gain_exp].[13-ce_gain_exp], [0,8191],
default/ineffective 4096(0.5) */
- uint16_t y5; /** 6th kneepoint gain.
+ u16 y5; /** 6th kneepoint gain.
u[ce_gain_exp].[13-ce_gain_exp], [0,8191],
default/ineffective 4096(0.5) */
- uint16_t ce_gain_exp; /** Common exponent of y-axis gain.
+ u16 ce_gain_exp; /** Common exponent of y-axis gain.
u8.0, [0,13],
default/ineffective 1 */
- uint16_t x1; /** 2nd kneepoint luma.
+ u16 x1; /** 2nd kneepoint luma.
u0.13, [0,8191], constraints: 0<x1<x2,
default/ineffective 1024 */
- uint16_t x2; /** 3rd kneepoint luma.
+ u16 x2; /** 3rd kneepoint luma.
u0.13, [0,8191], constraints: x1<x2<x3,
default/ineffective 2048 */
- uint16_t x3; /** 4th kneepoint luma.
+ u16 x3; /** 4th kneepoint luma.
u0.13, [0,8191], constraints: x2<x3<x4,
default/ineffective 6144 */
- uint16_t x4; /** 5tn kneepoint luma.
+ u16 x4; /** 5tn kneepoint luma.
u0.13, [0,8191], constraints: x3<x4<8191,
default/ineffective 7168 */
};
union ia_css_ctc_data {
- uint16_t vamem_1[IA_CSS_VAMEM_1_CTC_TABLE_SIZE];
- uint16_t vamem_2[IA_CSS_VAMEM_2_CTC_TABLE_SIZE];
+ u16 vamem_1[IA_CSS_VAMEM_1_CTC_TABLE_SIZE];
+ u16 vamem_2[IA_CSS_VAMEM_2_CTC_TABLE_SIZE];
};
/* CTC table, used for Chroma Tone Control.
};
#endif /* __IA_CSS_CTC_TYPES_H */
-
-
ia_css_de_encode(
struct sh_css_isp_de_params *to,
const struct ia_css_de_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->pixelnoise =
void
ia_css_de_dump(
const struct sh_css_isp_de_params *de,
- unsigned level)
+ unsigned int level)
{
if (!de) return;
ia_css_debug_dtrace(level, "Demosaic:\n");
void
ia_css_de_debug_dtrace(
const struct ia_css_de_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
- "config.pixelnoise=%d, "
- "config.c1_coring_threshold=%d, config.c2_coring_threshold=%d\n",
+ "config.pixelnoise=%d, config.c1_coring_threshold=%d, config.c2_coring_threshold=%d\n",
config->pixelnoise,
config->c1_coring_threshold, config->c2_coring_threshold);
}
void
ia_css_init_de_state(
- void/*struct sh_css_isp_de_vmem_state*/ *state,
+ void/*struct sh_css_isp_de_vmem_state*/ * state,
size_t size)
{
memset(state, 0, size);
ia_css_de_encode(
struct sh_css_isp_de_params *to,
const struct ia_css_de_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_de_dump(
const struct sh_css_isp_de_params *de,
- unsigned level);
+ unsigned int level);
void
ia_css_de_debug_dtrace(
const struct ia_css_de_config *config,
- unsigned level);
+ unsigned int level);
void
ia_css_init_de_state(
- void/*struct sh_css_isp_de_vmem_state*/ *state,
+ void/*struct sh_css_isp_de_vmem_state*/ * state,
size_t size);
#endif /* __IA_CSS_DE_HOST_H */
/* DE (Demosaic) */
struct sh_css_isp_de_params {
- int32_t pixelnoise;
- int32_t c1_coring_threshold;
- int32_t c2_coring_threshold;
+ s32 pixelnoise;
+ s32 c1_coring_threshold;
+ s32 c2_coring_threshold;
};
#endif /* __IA_CSS_DE_PARAM_H */
/* DE (Demosaic) */
struct sh_css_isp_de_vmem_state {
- VMEM_ARRAY(de_buf[4], MAX_VECTORS_PER_BUF_LINE*ISP_NWAY);
+ VMEM_ARRAY(de_buf[4], MAX_VECTORS_PER_BUF_LINE * ISP_NWAY);
};
#endif /* __IA_CSS_DE_STATE_H */
};
#endif /* __IA_CSS_DE_TYPES_H */
-
ia_css_ecd_encode(
struct sh_css_isp_ecd_params *to,
const struct ia_css_ecd_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->zip_strength = from->zip_strength;
void
ia_css_ecd_dump(
const struct sh_css_isp_ecd_params *ecd,
- unsigned level);
+ unsigned int level);
void
ia_css_ecd_debug_dtrace(
const struct ia_css_ecd_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
- "config.zip_strength=%d, "
- "config.fc_strength=%d, config.fc_debias=%d\n",
+ "config.zip_strength=%d, config.fc_strength=%d, config.fc_debias=%d\n",
config->zip_strength,
config->fc_strength, config->fc_debias);
}
ia_css_ecd_encode(
struct sh_css_isp_ecd_params *to,
const struct ia_css_ecd_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_ecd_dump(
const struct sh_css_isp_ecd_params *ecd,
- unsigned level);
+ unsigned int level);
void
ia_css_ecd_debug_dtrace(
- const struct ia_css_ecd_config *config, unsigned level);
+ const struct ia_css_ecd_config *config, unsigned int level);
#endif /* __IA_CSS_DE2_HOST_H */
/* DE (Demosaic) */
struct sh_css_isp_ecd_params {
- int32_t zip_strength;
- int32_t fc_strength;
- int32_t fc_debias;
+ s32 zip_strength;
+ s32 fc_strength;
+ s32 fc_debias;
};
#endif /* __IA_CSS_DE2_PARAM_H */
* ISP2: DE2 is used.
*/
struct ia_css_ecd_config {
- uint16_t zip_strength; /** Strength of zipper reduction.
+ u16 zip_strength; /** Strength of zipper reduction.
u0.13, [0,8191],
default 5489(0.67), ineffective 0 */
- uint16_t fc_strength; /** Strength of false color reduction.
+ u16 fc_strength; /** Strength of false color reduction.
u0.13, [0,8191],
default 8191(almost 1.0), ineffective 0 */
- uint16_t fc_debias; /** Prevent color change
+ u16 fc_debias; /** Prevent color change
on noise or Gr/Gb imbalance.
u0.13, [0,8191],
default 0, ineffective 0 */
};
#endif /* __IA_CSS_DE2_TYPES_H */
-
ia_css_dp_encode(
struct sh_css_isp_dp_params *to,
const struct ia_css_dp_config *from,
- unsigned size)
+ unsigned int size)
{
int gain = from->gain;
int gr = from->gr;
uDIGIT_FITTING(from->gain, 8, SH_CSS_DP_GAIN_SHIFT);
to->coef_rr_gr =
- uDIGIT_FITTING (gain * gr / r, 8, SH_CSS_DP_GAIN_SHIFT);
+ uDIGIT_FITTING(gain * gr / r, 8, SH_CSS_DP_GAIN_SHIFT);
to->coef_rr_gb =
- uDIGIT_FITTING (gain * gb / r, 8, SH_CSS_DP_GAIN_SHIFT);
+ uDIGIT_FITTING(gain * gb / r, 8, SH_CSS_DP_GAIN_SHIFT);
to->coef_bb_gb =
- uDIGIT_FITTING (gain * gb / b, 8, SH_CSS_DP_GAIN_SHIFT);
+ uDIGIT_FITTING(gain * gb / b, 8, SH_CSS_DP_GAIN_SHIFT);
to->coef_bb_gr =
- uDIGIT_FITTING (gain * gr / b, 8, SH_CSS_DP_GAIN_SHIFT);
+ uDIGIT_FITTING(gain * gr / b, 8, SH_CSS_DP_GAIN_SHIFT);
to->coef_gr_rr =
- uDIGIT_FITTING (gain * r / gr, 8, SH_CSS_DP_GAIN_SHIFT);
+ uDIGIT_FITTING(gain * r / gr, 8, SH_CSS_DP_GAIN_SHIFT);
to->coef_gr_bb =
- uDIGIT_FITTING (gain * b / gr, 8, SH_CSS_DP_GAIN_SHIFT);
+ uDIGIT_FITTING(gain * b / gr, 8, SH_CSS_DP_GAIN_SHIFT);
to->coef_gb_bb =
- uDIGIT_FITTING (gain * b / gb, 8, SH_CSS_DP_GAIN_SHIFT);
+ uDIGIT_FITTING(gain * b / gb, 8, SH_CSS_DP_GAIN_SHIFT);
to->coef_gb_rr =
- uDIGIT_FITTING (gain * r / gb, 8, SH_CSS_DP_GAIN_SHIFT);
+ uDIGIT_FITTING(gain * r / gb, 8, SH_CSS_DP_GAIN_SHIFT);
}
void
ia_css_dp_dump(
const struct sh_css_isp_dp_params *dp,
- unsigned level)
+ unsigned int level)
{
if (!dp) return;
ia_css_debug_dtrace(level, "Defect Pixel Correction:\n");
void
ia_css_dp_debug_dtrace(
const struct ia_css_dp_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
"config.threshold=%d, config.gain=%d\n",
void
ia_css_init_dp_state(
- void/*struct sh_css_isp_dp_vmem_state*/ *state,
+ void/*struct sh_css_isp_dp_vmem_state*/ * state,
size_t size)
{
memset(state, 0, size);
ia_css_dp_encode(
struct sh_css_isp_dp_params *to,
const struct ia_css_dp_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_dp_dump(
const struct sh_css_isp_dp_params *dp,
- unsigned level);
+ unsigned int level);
void
ia_css_dp_debug_dtrace(
const struct ia_css_dp_config *config,
- unsigned level);
+ unsigned int level);
void
ia_css_init_dp_state(
- void/*struct sh_css_isp_dp_vmem_state*/ *state,
+ void/*struct sh_css_isp_dp_vmem_state*/ * state,
size_t size);
#endif /* __IA_CSS_DP_HOST_H */
/* DP (Defect Pixel Correction) */
struct sh_css_isp_dp_params {
- int32_t threshold_single;
- int32_t threshold_2adjacent;
- int32_t gain;
- int32_t coef_rr_gr;
- int32_t coef_rr_gb;
- int32_t coef_bb_gb;
- int32_t coef_bb_gr;
- int32_t coef_gr_rr;
- int32_t coef_gr_bb;
- int32_t coef_gb_bb;
- int32_t coef_gb_rr;
+ s32 threshold_single;
+ s32 threshold_2adjacent;
+ s32 gain;
+ s32 coef_rr_gr;
+ s32 coef_rr_gb;
+ s32 coef_bb_gb;
+ s32 coef_bb_gr;
+ s32 coef_gr_rr;
+ s32 coef_gr_bb;
+ s32 coef_gb_bb;
+ s32 coef_gb_rr;
};
#endif /* __IA_CSS_DP_PARAM_H */
* CSS-API header file for Defect Pixel Correction (DPC) parameters.
*/
-
/* Defect Pixel Correction configuration.
*
* ISP block: DPC1 (DPC after WB)
too large.
u8.8, [0,65535],
default 4096, ineffective 65535 */
- uint32_t gr; /* unsigned <integer_bits>.<16-integer_bits> */
- uint32_t r; /* unsigned <integer_bits>.<16-integer_bits> */
- uint32_t b; /* unsigned <integer_bits>.<16-integer_bits> */
- uint32_t gb; /* unsigned <integer_bits>.<16-integer_bits> */
+ u32 gr; /* unsigned <integer_bits>.<16-integer_bits> */
+ u32 r; /* unsigned <integer_bits>.<16-integer_bits> */
+ u32 b; /* unsigned <integer_bits>.<16-integer_bits> */
+ u32 gb; /* unsigned <integer_bits>.<16-integer_bits> */
};
#endif /* __IA_CSS_DP_TYPES_H */
-
{
(void)size;
- assert ((from->metric1 >= 0) && (from->metric1 <= METRIC1_ONE_FP));
- assert ((from->metric3 >= 0) && (from->metric3 <= METRIC3_ONE_FP));
- assert ((from->metric2 >= METRIC2_ONE_FP) &&
- (from->metric2 < 256*METRIC2_ONE_FP));
- assert ((from->wb_gain_gr > 0) && (from->wb_gain_gr < 16*WBGAIN_ONE_FP));
- assert ((from->wb_gain_r > 0) && (from->wb_gain_r < 16*WBGAIN_ONE_FP));
- assert ((from->wb_gain_b > 0) && (from->wb_gain_b < 16*WBGAIN_ONE_FP));
- assert ((from->wb_gain_gb > 0) && (from->wb_gain_gb < 16*WBGAIN_ONE_FP));
+ assert((from->metric1 >= 0) && (from->metric1 <= METRIC1_ONE_FP));
+ assert((from->metric3 >= 0) && (from->metric3 <= METRIC3_ONE_FP));
+ assert((from->metric2 >= METRIC2_ONE_FP) &&
+ (from->metric2 < 256 * METRIC2_ONE_FP));
+ assert((from->wb_gain_gr > 0) && (from->wb_gain_gr < 16 * WBGAIN_ONE_FP));
+ assert((from->wb_gain_r > 0) && (from->wb_gain_r < 16 * WBGAIN_ONE_FP));
+ assert((from->wb_gain_b > 0) && (from->wb_gain_b < 16 * WBGAIN_ONE_FP));
+ assert((from->wb_gain_gb > 0) && (from->wb_gain_gb < 16 * WBGAIN_ONE_FP));
to->metric1 = from->metric1;
to->metric2 = from->metric2;
void
ia_css_dpc2_debug_dtrace(
const struct ia_css_dpc2_config *config,
- unsigned level)
+ unsigned int level)
{
(void)config;
(void)level;
void
ia_css_dpc2_debug_dtrace(
const struct ia_css_dpc2_config *config,
- unsigned level);
+ unsigned int level);
#endif
#endif /* __IA_CSS_DPC2_HOST_H */
#include "type_support.h"
#include "vmem.h" /* for VMEM_ARRAY*/
-
/* 4 planes : GR, R, B, GB */
#define NUM_PLANES 4
#define DPC2_STATE_SECOND_MINMAX_BUFFER_HEIGHT 1
#define DPC2_STATE_SECOND_MINMAX_BUFFER_WIDTH MAX_FRAME_SIMDWIDTH
-
struct ia_css_isp_dpc2_params {
- int32_t metric1;
- int32_t metric2;
- int32_t metric3;
- int32_t wb_gain_gr;
- int32_t wb_gain_r;
- int32_t wb_gain_b;
- int32_t wb_gain_gb;
+ s32 metric1;
+ s32 metric2;
+ s32 metric3;
+ s32 wb_gain_gr;
+ s32 wb_gain_r;
+ s32 wb_gain_b;
+ s32 wb_gain_gb;
};
#endif /* __IA_CSS_DPC2_PARAM_H */
/**@{*/
/* Floating point constants for different metrics. */
-#define METRIC1_ONE_FP (1<<12)
-#define METRIC2_ONE_FP (1<<5)
-#define METRIC3_ONE_FP (1<<12)
-#define WBGAIN_ONE_FP (1<<9)
+#define METRIC1_ONE_FP BIT(12)
+#define METRIC2_ONE_FP BIT(5)
+#define METRIC3_ONE_FP BIT(12)
+#define WBGAIN_ONE_FP BIT(9)
/**@}*/
/**@{*/
*/
struct ia_css_dpc2_config {
/**@{*/
- int32_t metric1;
- int32_t metric2;
- int32_t metric3;
- int32_t wb_gain_gr;
- int32_t wb_gain_r;
- int32_t wb_gain_b;
- int32_t wb_gain_gb;
+ s32 metric1;
+ s32 metric2;
+ s32 metric3;
+ s32 wb_gain_gr;
+ s32 wb_gain_r;
+ s32 wb_gain_b;
+ s32 wb_gain_gb;
/**@}*/
};
+
/**@}*/
#endif /* __IA_CSS_DPC2_TYPES_H */
-
ia_css_dvs_config(
struct sh_css_isp_dvs_isp_config *to,
const struct ia_css_dvs_configuration *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->num_horizontal_blocks =
DVS_GDC_BLI_INTERP_ENVELOPE : DVS_GDC_BCI_INTERP_ENVELOPE);
/* number of blocks per height and width */
- unsigned int num_blocks_y = (uv_flag ? DVS_NUM_BLOCKS_Y_CHROMA(o_height) : DVS_NUM_BLOCKS_Y(o_height) );
- unsigned int num_blocks_x = (uv_flag ? DVS_NUM_BLOCKS_X_CHROMA(o_width) : DVS_NUM_BLOCKS_X(o_width) ); // round num_x up to blockdim_x, if it concerns the Y0Y1 block (uv_flag==0) round up to even
-
+ unsigned int num_blocks_y = (uv_flag ? DVS_NUM_BLOCKS_Y_CHROMA(o_height) : DVS_NUM_BLOCKS_Y(o_height));
+ unsigned int num_blocks_x = (uv_flag ? DVS_NUM_BLOCKS_X_CHROMA(o_width) : DVS_NUM_BLOCKS_X(o_width)); // round num_x up to blockdim_x, if it concerns the Y0Y1 block (uv_flag==0) round up to even
unsigned int in_stride = i_stride * DVS_INPUT_BYTES_PER_PIXEL;
- unsigned width, height;
+ unsigned int width, height;
unsigned int *xbuff = NULL;
unsigned int *ybuff = NULL;
struct gdc_warp_param_mem_s *ptr;
- assert(config != NULL);
- assert(gdc_warp_table != NULL);
- assert(gdc_warp_table->address != NULL);
+ assert(config);
+ assert(gdc_warp_table);
+ assert(gdc_warp_table->address);
ptr = (struct gdc_warp_param_mem_s *)gdc_warp_table->address;
ptr += (2 * uv_flag); /* format is Y0 Y1 UV, so UV starts at 3rd position */
- if(uv_flag == 0)
+ if (uv_flag == 0)
{
xbuff = config->xcoords_y;
ybuff = config->ycoords_y;
width = config->width_y;
height = config->height_y;
- }
- else
+ } else
{
xbuff = config->xcoords_uv;
ybuff = config->ycoords_uv;
IA_CSS_LOG("blockdim_x %d blockdim_y %d",
DVS_BLOCKDIM_X, DVS_BLOCKDIM_Y_LUMA >> uv_flag);
- IA_CSS_LOG("num_blocks_x %d num_blocks_y %d", num_blocks_x,num_blocks_y);
+ IA_CSS_LOG("num_blocks_x %d num_blocks_y %d", num_blocks_x, num_blocks_y);
IA_CSS_LOG("width %d height %d", width, height);
assert(width == num_blocks_x + 1); // the width and height of the provided morphing table should be 1 more than the number of blocks
for (j = 0; j < num_blocks_y; j++) {
for (i = 0; i < num_blocks_x; i++) {
-
x00 = xbuff[j * width + i];
- x01 = xbuff[j * width + (i+1)];
- x10 = xbuff[(j+1) * width + i];
- x11 = xbuff[(j+1) * width + (i+1)];
+ x01 = xbuff[j * width + (i + 1)];
+ x10 = xbuff[(j + 1) * width + i];
+ x11 = xbuff[(j + 1) * width + (i + 1)];
y00 = ybuff[j * width + i];
- y01 = ybuff[j * width + (i+1)];
- y10 = ybuff[(j+1) * width + i];
- y11 = ybuff[(j+1) * width + (i+1)];
+ y01 = ybuff[j * width + (i + 1)];
+ y10 = ybuff[(j + 1) * width + i];
+ y11 = ybuff[(j + 1) * width + (i + 1)];
xmin = min(x00, x10);
xmax = max(x01, x11);
ymax = max(y10, y11);
/* Assert that right column's X is greater */
- assert ( x01 >= xmin);
- assert ( x11 >= xmin);
+ assert(x01 >= xmin);
+ assert(x11 >= xmin);
/* Assert that bottom row's Y is greater */
- assert ( y10 >= ymin);
- assert ( y11 >= ymin);
+ assert(y10 >= ymin);
+ assert(y11 >= ymin);
topleft_y = ymin >> DVS_COORD_FRAC_BITS;
topleft_x = ((xmin >> DVS_COORD_FRAC_BITS)
printf("p3_x: %d\n", s.p3_x);
printf("p3_y: %d\n", s.p3_y);
- printf("p0_x_nofrac[0]: %d\n", s.p0_x>>DVS_COORD_FRAC_BITS);
- printf("p0_y_nofrac[1]: %d\n", s.p0_y>>DVS_COORD_FRAC_BITS);
- printf("p1_x_nofrac[2]: %d\n", s.p1_x>>DVS_COORD_FRAC_BITS);
- printf("p1_y_nofrac[3]: %d\n", s.p1_y>>DVS_COORD_FRAC_BITS);
- printf("p2_x_nofrac[0]: %d\n", s.p2_x>>DVS_COORD_FRAC_BITS);
- printf("p2_y_nofrac[1]: %d\n", s.p2_y>>DVS_COORD_FRAC_BITS);
- printf("p3_x_nofrac[2]: %d\n", s.p3_x>>DVS_COORD_FRAC_BITS);
- printf("p3_y_nofrac[3]: %d\n", s.p3_y>>DVS_COORD_FRAC_BITS);
+ printf("p0_x_nofrac[0]: %d\n", s.p0_x >> DVS_COORD_FRAC_BITS);
+ printf("p0_y_nofrac[1]: %d\n", s.p0_y >> DVS_COORD_FRAC_BITS);
+ printf("p1_x_nofrac[2]: %d\n", s.p1_x >> DVS_COORD_FRAC_BITS);
+ printf("p1_y_nofrac[3]: %d\n", s.p1_y >> DVS_COORD_FRAC_BITS);
+ printf("p2_x_nofrac[0]: %d\n", s.p2_x >> DVS_COORD_FRAC_BITS);
+ printf("p2_y_nofrac[1]: %d\n", s.p2_y >> DVS_COORD_FRAC_BITS);
+ printf("p3_x_nofrac[2]: %d\n", s.p3_x >> DVS_COORD_FRAC_BITS);
+ printf("p3_y_nofrac[3]: %d\n", s.p3_y >> DVS_COORD_FRAC_BITS);
printf("\n");
#endif
if (uv_flag)
ptr += 3;
else
- ptr += (1 + (i&1));
+ ptr += (1 + (i & 1));
}
}
}
struct ia_css_host_data *me;
struct gdc_warp_param_mem_s *isp_data_ptr;
- assert(binary != NULL);
- assert(dvs_6axis_config != NULL);
- assert(dvs_in_frame_info != NULL);
+ assert(binary);
+ assert(dvs_6axis_config);
+ assert(dvs_in_frame_info);
me = ia_css_host_data_allocate((size_t)((DVS_6AXIS_BYTES(binary) / 2) * 3));
if (dvs_in_frame_info->format == IA_CSS_FRAME_FORMAT_YUV420) {
/*YUV420 has half the stride for U/V plane*/
- i_stride /=2;
+ i_stride /= 2;
}
/* UV plane (packed inside the y plane) */
convert_coords_to_ispparams(me, dvs_6axis_config,
- i_stride, o_width/2, o_height/2, 1);
+ i_stride, o_width / 2, o_height / 2, 1);
return me;
}
const struct ia_css_frame_info *dvs_in_frame_info,
hrt_vaddress ddr_addr_y)
{
-
struct ia_css_host_data *me;
- assert(dvs_6axis_config != NULL);
+
+ assert(dvs_6axis_config);
assert(ddr_addr_y != mmgr_NULL);
- assert(dvs_in_frame_info != NULL);
+ assert(dvs_in_frame_info);
me = convert_allocate_dvs_6axis_config(dvs_6axis_config,
binary,
return IA_CSS_SUCCESS;
}
-
ia_css_dvs_config(
struct sh_css_isp_dvs_isp_config *to,
const struct ia_css_dvs_configuration *from,
- unsigned size);
+ unsigned int size);
void
ia_css_dvs_configure(
#endif
/* dvserence frame */
struct sh_css_isp_dvs_isp_config {
- uint32_t num_horizontal_blocks;
- uint32_t num_vertical_blocks;
+ u32 num_horizontal_blocks;
+ u32 num_vertical_blocks;
};
#endif /* __IA_CSS_DVS_PARAM_H */
};
#endif /* __IA_CSS_DVS_TYPES_H */
-
#define NUMBER_OF_TCINV_POINTS 9
#define NUMBER_OF_FCINV_POINTS 9
-static const int16_t chgrinv_x[NUMBER_OF_CHGRINV_POINTS] = {
+static const s16 chgrinv_x[NUMBER_OF_CHGRINV_POINTS] = {
0, 16, 64, 144, 272, 448, 672, 976,
1376, 1888, 2528, 3312, 4256, 5376, 6688};
-static const int16_t chgrinv_a[NUMBER_OF_CHGRINV_POINTS] = {
+static const s16 chgrinv_a[NUMBER_OF_CHGRINV_POINTS] = {
-7171, -256, -29, -3456, -1071, -475, -189, -102,
-48, -38, -10, -9, -7, -6, 0};
-static const int16_t chgrinv_b[NUMBER_OF_CHGRINV_POINTS] = {
+static const s16 chgrinv_b[NUMBER_OF_CHGRINV_POINTS] = {
8191, 1021, 256, 114, 60, 37, 24, 17,
12, 9, 6, 5, 4, 3, 2};
-static const int16_t chgrinv_c[NUMBER_OF_CHGRINV_POINTS] = {
+static const s16 chgrinv_c[NUMBER_OF_CHGRINV_POINTS] = {
1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0};
-static const int16_t tcinv_x[NUMBER_OF_TCINV_POINTS] = {
+static const s16 tcinv_x[NUMBER_OF_TCINV_POINTS] = {
0, 4, 11, 23, 42, 68, 102, 148, 205};
-static const int16_t tcinv_a[NUMBER_OF_TCINV_POINTS] = {
+static const s16 tcinv_a[NUMBER_OF_TCINV_POINTS] = {
-6364, -631, -126, -34, -13, -6, -4452, -2156, 0};
-static const int16_t tcinv_b[NUMBER_OF_TCINV_POINTS] = {
+static const s16 tcinv_b[NUMBER_OF_TCINV_POINTS] = {
8191, 1828, 726, 352, 197, 121, 80, 55, 40};
-static const int16_t tcinv_c[NUMBER_OF_TCINV_POINTS] = {
+static const s16 tcinv_c[NUMBER_OF_TCINV_POINTS] = {
1, 1, 1, 1, 1, 1, 0, 0, 0};
-static const int16_t fcinv_x[NUMBER_OF_FCINV_POINTS] = {
+static const s16 fcinv_x[NUMBER_OF_FCINV_POINTS] = {
0, 80, 216, 456, 824, 1344, 2040, 2952, 4096};
-static const int16_t fcinv_a[NUMBER_OF_FCINV_POINTS] = {
+static const s16 fcinv_a[NUMBER_OF_FCINV_POINTS] = {
-5244, -486, -86, -2849, -961, -400, -180, -86, 0};
-static const int16_t fcinv_b[NUMBER_OF_FCINV_POINTS] = {
+static const s16 fcinv_b[NUMBER_OF_FCINV_POINTS] = {
8191, 1637, 607, 287, 159, 98, 64, 44, 32};
-static const int16_t fcinv_c[NUMBER_OF_FCINV_POINTS] = {
+static const s16 fcinv_c[NUMBER_OF_FCINV_POINTS] = {
1, 1, 1, 0, 0, 0, 0, 0, 0};
-
void
ia_css_eed1_8_vmem_encode(
struct eed1_8_vmem_params *to,
const struct ia_css_eed1_8_config *from,
size_t size)
{
- unsigned i, j, base;
- const unsigned total_blocks = 4;
- const unsigned shuffle_block = 16;
+ unsigned int i, j, base;
+ const unsigned int total_blocks = 4;
+ const unsigned int shuffle_block = 16;
(void)size;
}
for (j = 1; j < IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS; j++) {
- assert(from->dew_enhance_seg_x[j] > from->dew_enhance_seg_x[j-1]);
- assert(from->dew_enhance_seg_y[j] > from->dew_enhance_seg_y[j-1]);
+ assert(from->dew_enhance_seg_x[j] > from->dew_enhance_seg_x[j - 1]);
+ assert(from->dew_enhance_seg_y[j] > from->dew_enhance_seg_y[j - 1]);
}
assert(from->dew_enhance_seg_x[0] == 0);
assert(fcinv_x[0] == 0);
for (j = 1; j < NUMBER_OF_CHGRINV_POINTS; j++) {
- assert(chgrinv_x[j] > chgrinv_x[j-1]);
+ assert(chgrinv_x[j] > chgrinv_x[j - 1]);
}
for (j = 1; j < NUMBER_OF_TCINV_POINTS; j++) {
- assert(tcinv_x[j] > tcinv_x[j-1]);
+ assert(tcinv_x[j] > tcinv_x[j - 1]);
}
for (j = 1; j < NUMBER_OF_FCINV_POINTS; j++) {
- assert(fcinv_x[j] > fcinv_x[j-1]);
+ assert(fcinv_x[j] > fcinv_x[j - 1]);
}
/* The implementation of the calulating 1/x is based on the availability
* initialised as described in the KFS. The remaining elements of a vector are set to 0.
*/
/* TODO: guard this code with above assumptions */
- for(i = 0; i < total_blocks; i++) {
+ for (i = 0; i < total_blocks; i++) {
base = shuffle_block * i;
for (j = 0; j < IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS; j++) {
for (j = 0; j < (IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1); j++) {
to->e_dew_enh_a[0][base + j] = min_t(int, max_t(int,
from->dew_enhance_seg_slope[j],
- -8192), 8191);
+ -8192), 8191);
/* Convert dew_enhance_seg_exp to flag:
* 0 -> 0
* 1...13 -> 1
}
}
-
void
ia_css_eed1_8_encode(
struct eed1_8_dmem_params *to,
to->dedgew_max = from->dedgew_max;
}
-
void
ia_css_init_eed1_8_state(
void *state,
memset(state, 0, size);
}
-
#ifndef IA_CSS_NO_DEBUG
void
ia_css_eed1_8_debug_dtrace(
const struct ia_css_eed1_8_config *eed,
- unsigned level)
+ unsigned int level)
{
if (!eed)
return;
ia_css_debug_dtrace(level, "\t%-32s = %d\n", "dedgew_max", eed->dedgew_max);
}
#endif
-
void
ia_css_eed1_8_debug_dtrace(
const struct ia_css_eed1_8_config *config,
- unsigned level);
+ unsigned int level);
#endif
#endif /* __IA_CSS_EED1_8_HOST_H */
#include "ia_css_eed1_8_types.h" /* IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS */
-
/* Configuration parameters: */
/* Enable median for false color correction
/* EED (Edge Enhancing Demosaic) ISP parameters */
struct eed1_8_dmem_params {
- int32_t rbzp_strength;
-
- int32_t fcstrength;
- int32_t fcthres_0;
- int32_t fc_sat_coef;
- int32_t fc_coring_prm;
- int32_t fc_slope;
-
- int32_t aerel_thres0;
- int32_t aerel_gain0;
- int32_t aerel_thres_diff;
- int32_t aerel_gain_diff;
-
- int32_t derel_thres0;
- int32_t derel_gain0;
- int32_t derel_thres_diff;
- int32_t derel_gain_diff;
-
- int32_t coring_pos0;
- int32_t coring_pos_diff;
- int32_t coring_neg0;
- int32_t coring_neg_diff;
-
- int32_t gain_exp;
- int32_t gain_pos0;
- int32_t gain_pos_diff;
- int32_t gain_neg0;
- int32_t gain_neg_diff;
-
- int32_t margin_pos0;
- int32_t margin_pos_diff;
- int32_t margin_neg0;
- int32_t margin_neg_diff;
-
- int32_t e_dew_enh_asr;
- int32_t dedgew_max;
+ s32 rbzp_strength;
+
+ s32 fcstrength;
+ s32 fcthres_0;
+ s32 fc_sat_coef;
+ s32 fc_coring_prm;
+ s32 fc_slope;
+
+ s32 aerel_thres0;
+ s32 aerel_gain0;
+ s32 aerel_thres_diff;
+ s32 aerel_gain_diff;
+
+ s32 derel_thres0;
+ s32 derel_gain0;
+ s32 derel_thres_diff;
+ s32 derel_gain_diff;
+
+ s32 coring_pos0;
+ s32 coring_pos_diff;
+ s32 coring_neg0;
+ s32 coring_neg_diff;
+
+ s32 gain_exp;
+ s32 gain_pos0;
+ s32 gain_pos_diff;
+ s32 gain_neg0;
+ s32 gain_neg_diff;
+
+ s32 margin_pos0;
+ s32 margin_pos_diff;
+ s32 margin_neg0;
+ s32 margin_neg_diff;
+
+ s32 e_dew_enh_asr;
+ s32 dedgew_max;
};
#endif /* __IA_CSS_EED1_8_PARAM_H */
* CSS-API header file for Edge Enhanced Demosaic parameters.
*/
-
#include "type_support.h"
/**
*/
struct ia_css_eed1_8_config {
- int32_t rbzp_strength; /** Strength of zipper reduction. */
-
- int32_t fcstrength; /** Strength of false color reduction. */
- int32_t fcthres_0; /** Threshold to prevent chroma coring due to noise or green disparity in dark region. */
- int32_t fcthres_1; /** Threshold to prevent chroma coring due to noise or green disparity in bright region. */
- int32_t fc_sat_coef; /** How much color saturation to maintain in high color saturation region. */
- int32_t fc_coring_prm; /** Chroma coring coefficient for tint color suppression. */
-
- int32_t aerel_thres0; /** Threshold for Non-Directional Reliability at dark region. */
- int32_t aerel_gain0; /** Gain for Non-Directional Reliability at dark region. */
- int32_t aerel_thres1; /** Threshold for Non-Directional Reliability at bright region. */
- int32_t aerel_gain1; /** Gain for Non-Directional Reliability at bright region. */
-
- int32_t derel_thres0; /** Threshold for Directional Reliability at dark region. */
- int32_t derel_gain0; /** Gain for Directional Reliability at dark region. */
- int32_t derel_thres1; /** Threshold for Directional Reliability at bright region. */
- int32_t derel_gain1; /** Gain for Directional Reliability at bright region. */
-
- int32_t coring_pos0; /** Positive Edge Coring Threshold in dark region. */
- int32_t coring_pos1; /** Positive Edge Coring Threshold in bright region. */
- int32_t coring_neg0; /** Negative Edge Coring Threshold in dark region. */
- int32_t coring_neg1; /** Negative Edge Coring Threshold in bright region. */
-
- int32_t gain_exp; /** Common Exponent of Gain. */
- int32_t gain_pos0; /** Gain for Positive Edge in dark region. */
- int32_t gain_pos1; /** Gain for Positive Edge in bright region. */
- int32_t gain_neg0; /** Gain for Negative Edge in dark region. */
- int32_t gain_neg1; /** Gain for Negative Edge in bright region. */
-
- int32_t pos_margin0; /** Margin for Positive Edge in dark region. */
- int32_t pos_margin1; /** Margin for Positive Edge in bright region. */
- int32_t neg_margin0; /** Margin for Negative Edge in dark region. */
- int32_t neg_margin1; /** Margin for Negative Edge in bright region. */
-
- int32_t dew_enhance_seg_x[IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS]; /** Segment data for directional edge weight: X. */
- int32_t dew_enhance_seg_y[IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS]; /** Segment data for directional edge weight: Y. */
- int32_t dew_enhance_seg_slope[(IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1)]; /** Segment data for directional edge weight: Slope. */
- int32_t dew_enhance_seg_exp[(IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1)]; /** Segment data for directional edge weight: Exponent. */
- int32_t dedgew_max; /** Max Weight for Directional Edge. */
+ s32 rbzp_strength; /** Strength of zipper reduction. */
+
+ s32 fcstrength; /** Strength of false color reduction. */
+ s32 fcthres_0; /** Threshold to prevent chroma coring due to noise or green disparity in dark region. */
+ s32 fcthres_1; /** Threshold to prevent chroma coring due to noise or green disparity in bright region. */
+ s32 fc_sat_coef; /** How much color saturation to maintain in high color saturation region. */
+ s32 fc_coring_prm; /** Chroma coring coefficient for tint color suppression. */
+
+ s32 aerel_thres0; /** Threshold for Non-Directional Reliability at dark region. */
+ s32 aerel_gain0; /** Gain for Non-Directional Reliability at dark region. */
+ s32 aerel_thres1; /** Threshold for Non-Directional Reliability at bright region. */
+ s32 aerel_gain1; /** Gain for Non-Directional Reliability at bright region. */
+
+ s32 derel_thres0; /** Threshold for Directional Reliability at dark region. */
+ s32 derel_gain0; /** Gain for Directional Reliability at dark region. */
+ s32 derel_thres1; /** Threshold for Directional Reliability at bright region. */
+ s32 derel_gain1; /** Gain for Directional Reliability at bright region. */
+
+ s32 coring_pos0; /** Positive Edge Coring Threshold in dark region. */
+ s32 coring_pos1; /** Positive Edge Coring Threshold in bright region. */
+ s32 coring_neg0; /** Negative Edge Coring Threshold in dark region. */
+ s32 coring_neg1; /** Negative Edge Coring Threshold in bright region. */
+
+ s32 gain_exp; /** Common Exponent of Gain. */
+ s32 gain_pos0; /** Gain for Positive Edge in dark region. */
+ s32 gain_pos1; /** Gain for Positive Edge in bright region. */
+ s32 gain_neg0; /** Gain for Negative Edge in dark region. */
+ s32 gain_neg1; /** Gain for Negative Edge in bright region. */
+
+ s32 pos_margin0; /** Margin for Positive Edge in dark region. */
+ s32 pos_margin1; /** Margin for Positive Edge in bright region. */
+ s32 neg_margin0; /** Margin for Negative Edge in dark region. */
+ s32 neg_margin1; /** Margin for Negative Edge in bright region. */
+
+ s32 dew_enhance_seg_x[IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS]; /** Segment data for directional edge weight: X. */
+ s32 dew_enhance_seg_y[IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS]; /** Segment data for directional edge weight: Y. */
+ s32 dew_enhance_seg_slope[(IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1)]; /** Segment data for directional edge weight: Slope. */
+ s32 dew_enhance_seg_exp[(IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1)]; /** Segment data for directional edge weight: Exponent. */
+ s32 dedgew_max; /** Max Weight for Directional Edge. */
};
#endif /* __IA_CSS_EED1_8_TYPES_H */
ia_css_formats_encode(
struct sh_css_isp_formats_params *to,
const struct ia_css_formats_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->video_full_range_flag = from->video_full_range_flag;
}
+
#ifndef IA_CSS_NO_DEBUG
/* FIXME: See BZ 4427 */
void
ia_css_formats_dump(
const struct sh_css_isp_formats_params *formats,
- unsigned level)
+ unsigned int level)
{
if (!formats) return;
ia_css_debug_dtrace(level, "\t%-32s = %d\n",
void
ia_css_formats_debug_dtrace(
const struct ia_css_formats_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
"config.video_full_range_flag=%d\n",
ia_css_formats_encode(
struct sh_css_isp_formats_params *to,
const struct ia_css_formats_config *from,
- unsigned size);
+ unsigned int size);
#ifndef IA_CSS_NO_DEBUG
/* FIXME: See BZ 4427 */
void
ia_css_formats_dump(
const struct sh_css_isp_formats_params *formats,
- unsigned level);
+ unsigned int level);
#endif
#ifndef IA_CSS_NO_DEBUG
void
ia_css_formats_debug_dtrace(
const struct ia_css_formats_config *formats,
- unsigned level);
+ unsigned int level);
#endif /*IA_CSS_NO_DEBUG*/
#endif /* __IA_CSS_FORMATS_HOST_H */
-
/* FORMATS (Format conversion) */
struct sh_css_isp_formats_params {
- int32_t video_full_range_flag;
+ s32 video_full_range_flag;
};
#endif /* __IA_CSS_FORMATS_PARAM_H */
* ISP2: FORMATS is used.
*/
struct ia_css_formats_config {
- uint32_t video_full_range_flag; /** selects the range of YUV output.
+ u32 video_full_range_flag; /** selects the range of YUV output.
u8.0, [0,1],
default 1, ineffective n/a\n
1 - full range, luma 0-255, chroma 0-255\n
#ifdef ISP2401
#define BDS_UNIT 8
#define FRAC_LOG 3
-#define FRAC_ACC (1<<FRAC_LOG)
+#define FRAC_ACC BIT(FRAC_LOG)
#if FRAC_ACC != BDS_UNIT
#error "FRAC_ACC and BDS_UNIT need to be merged into one define"
#endif
#ifndef __IA_CSS_FIXEDBDS_TYPES_H
#define __IA_CSS_FIXEDBDS_TYPES_H
-
struct sh_css_bds_factor {
- unsigned numerator;
- unsigned denominator;
+ unsigned int numerator;
+ unsigned int denominator;
unsigned int bds_factor;
};
-
#endif /*__IA_CSS_FIXEDBDS_TYPES_H*/
ia_css_fpn_encode(
struct sh_css_isp_fpn_params *to,
const struct ia_css_fpn_table *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->shift = from->shift;
void
ia_css_fpn_dump(
const struct sh_css_isp_fpn_params *fpn,
- unsigned level)
+ unsigned int level)
{
if (!fpn) return;
ia_css_debug_dtrace(level, "Fixed Pattern Noise Reduction:\n");
ia_css_fpn_config(
struct sh_css_isp_fpn_isp_config *to,
const struct ia_css_fpn_configuration *from,
- unsigned size)
+ unsigned int size)
{
- unsigned elems_a = ISP_VEC_NELEMS;
+ unsigned int elems_a = ISP_VEC_NELEMS;
(void)size;
ia_css_dma_configure_from_info(&to->port_b, from->info);
to->width_a_over_b = elems_a / to->port_b.elems;
/* Assume divisiblity here, may need to generalize to fixed point. */
- assert (elems_a % to->port_b.elems == 0);
+ assert(elems_a % to->port_b.elems == 0);
}
void
ia_css_configure_fpn(binary, &config);
}
-
ia_css_fpn_encode(
struct sh_css_isp_fpn_params *to,
const struct ia_css_fpn_table *from,
- unsigned size);
+ unsigned int size);
void
ia_css_fpn_dump(
const struct sh_css_isp_fpn_params *fpn,
- unsigned level);
+ unsigned int level);
void
ia_css_fpn_config(
struct sh_css_isp_fpn_isp_config *to,
const struct ia_css_fpn_configuration *from,
- unsigned size);
+ unsigned int size);
void
ia_css_fpn_configure(
/* FPNR (Fixed Pattern Noise Reduction) */
struct sh_css_isp_fpn_params {
- int32_t shift;
- int32_t enabled;
+ s32 shift;
+ s32 enabled;
};
struct sh_css_isp_fpn_isp_config {
- uint32_t width_a_over_b;
+ u32 width_a_over_b;
struct dma_port_config port_b;
};
*/
struct ia_css_fpn_table {
- int16_t *data; /** Table content (fixed patterns noise).
+ s16 *data; /** Table content (fixed patterns noise).
u0.[13-shift], [0,63] */
- uint32_t width; /** Table width (in pixels).
+ u32 width; /** Table width (in pixels).
This is the input frame width. */
- uint32_t height; /** Table height (in pixels).
+ u32 height; /** Table height (in pixels).
This is the input frame height. */
- uint32_t shift; /** Common exponent of table content.
+ u32 shift; /** Common exponent of table content.
u8.0, [0,13] */
- uint32_t enabled; /** Fpn is enabled.
+ u32 enabled; /** Fpn is enabled.
bool */
};
ia_css_gc_encode(
struct sh_css_isp_gc_params *to,
const struct ia_css_gc_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->gain_k1 =
ia_css_ce_encode(
struct sh_css_isp_ce_params *to,
const struct ia_css_ce_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->uv_level_min = from->uv_level_min;
ia_css_gc_vamem_encode(
struct sh_css_isp_gc_vamem_params *to,
const struct ia_css_gamma_table *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
- memcpy (&to->gc, &from->data, sizeof(to->gc));
+ memcpy(&to->gc, &from->data, sizeof(to->gc));
}
#ifndef IA_CSS_NO_DEBUG
void
ia_css_gc_dump(
const struct sh_css_isp_gc_params *gc,
- unsigned level)
+ unsigned int level)
{
if (!gc) return;
ia_css_debug_dtrace(level, "Gamma Correction:\n");
void
ia_css_ce_dump(
const struct sh_css_isp_ce_params *ce,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level, "Chroma Enhancement:\n");
ia_css_debug_dtrace(level, "\t%-32s = %d\n",
void
ia_css_gc_debug_dtrace(
const struct ia_css_gc_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
"config.gain_k1=%d, config.gain_k2=%d\n",
void
ia_css_ce_debug_dtrace(
const struct ia_css_ce_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
"config.uv_level_min=%d, config.uv_level_max=%d\n",
config->uv_level_min, config->uv_level_max);
}
#endif
-
ia_css_gc_encode(
struct sh_css_isp_gc_params *to,
const struct ia_css_gc_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_gc_vamem_encode(
struct sh_css_isp_gc_vamem_params *to,
const struct ia_css_gamma_table *from,
- unsigned size);
+ unsigned int size);
void
ia_css_ce_encode(
struct sh_css_isp_ce_params *to,
const struct ia_css_ce_config *from,
- unsigned size);
+ unsigned int size);
#ifndef IA_CSS_NO_DEBUG
void
ia_css_gc_dump(
const struct sh_css_isp_gc_params *gc,
- unsigned level);
+ unsigned int level);
void
ia_css_ce_dump(
const struct sh_css_isp_ce_params *ce,
- unsigned level);
+ unsigned int level);
void
ia_css_gc_debug_dtrace(
const struct ia_css_gc_config *config,
- unsigned level);
+ unsigned int level);
void
ia_css_ce_debug_dtrace(
const struct ia_css_ce_config *config,
- unsigned level);
+ unsigned int level);
#endif
#endif
#define GAMMA_OUTPUT_BITS 8
-#define GAMMA_OUTPUT_MAX_VAL ((1<<GAMMA_OUTPUT_BITS)-1)
+#define GAMMA_OUTPUT_MAX_VAL ((1 << GAMMA_OUTPUT_BITS) - 1)
/* GC (Gamma Correction) */
struct sh_css_isp_gc_params {
- int32_t gain_k1;
- int32_t gain_k2;
+ s32 gain_k1;
+ s32 gain_k2;
};
/* CE (Chroma Enhancement) */
struct sh_css_isp_ce_params {
- int32_t uv_level_min;
- int32_t uv_level_max;
+ s32 uv_level_min;
+ s32 uv_level_max;
};
/* This should be vamem_data_t, but that breaks the pipe generator */
struct sh_css_isp_gc_vamem_params {
- uint16_t gc[SH_CSS_ISP_GC_TABLE_SIZE];
+ u16 gc[SH_CSS_ISP_GC_TABLE_SIZE];
};
#endif /* __IA_CSS_GC_PARAM_H */
default_gamma_table.vamem_type = IA_CSS_VAMEM_TYPE_1;
#endif
}
-
/* Number of elements in the gamma table. */
#define IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE_LOG2 10
-#define IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE (1U<<IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE_LOG2)
+#define IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE BIT(IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE_LOG2)
/* Number of elements in the gamma table. */
#define IA_CSS_VAMEM_2_GAMMA_TABLE_SIZE_LOG2 8
-#define IA_CSS_VAMEM_2_GAMMA_TABLE_SIZE ((1U<<IA_CSS_VAMEM_2_GAMMA_TABLE_SIZE_LOG2) + 1)
+#define IA_CSS_VAMEM_2_GAMMA_TABLE_SIZE ((1U << IA_CSS_VAMEM_2_GAMMA_TABLE_SIZE_LOG2) + 1)
/* Gamma table, used for Y(Luma) Gamma Correction.
*
/** IA_CSS_VAMEM_TYPE_1(ISP2300) or
IA_CSS_VAMEM_TYPE_2(ISP2400) */
union ia_css_gc_data {
- uint16_t vamem_1[IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE];
+ u16 vamem_1[IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE];
/** Y(Luma) Gamma table on vamem type 1. u0.8, [0,255] */
- uint16_t vamem_2[IA_CSS_VAMEM_2_GAMMA_TABLE_SIZE];
+ u16 vamem_2[IA_CSS_VAMEM_2_GAMMA_TABLE_SIZE];
/** Y(Luma) Gamma table on vamem type 2. u0.8, [0,255] */
};
* (ISP2: GC2 (sRGB Gamma Correction) is used.)
*/
struct ia_css_gc_config {
- uint16_t gain_k1; /** Gain to adjust U after YUV Gamma Correction.
+ u16 gain_k1; /** Gain to adjust U after YUV Gamma Correction.
u0.16, [0,65535],
default/ineffective 19000(0.29) */
- uint16_t gain_k2; /** Gain to adjust V after YUV Gamma Correction.
+ u16 gain_k2; /** Gain to adjust V after YUV Gamma Correction.
u0.16, [0,65535],
default/ineffective 19000(0.29) */
};
* (ISP2: CE1 is not used.)
*/
struct ia_css_ce_config {
- uint8_t uv_level_min; /** Minimum of chroma output level.
+ u8 uv_level_min; /** Minimum of chroma output level.
u0.8, [0,255], default/ineffective 0 */
- uint8_t uv_level_max; /** Maximum of chroma output level.
+ u8 uv_level_max; /** Maximum of chroma output level.
u0.8, [0,255], default/ineffective 255 */
};
* ISP2: MACC2 is used.
*/
struct ia_css_macc_config {
- uint8_t exp; /** Common exponent of ia_css_macc_table.
+ u8 exp; /** Common exponent of ia_css_macc_table.
u8.0, [0,13], default 1, ineffective 1 */
};
ia_css_yuv2rgb_encode(
struct sh_css_isp_csc_params *to,
const struct ia_css_cc_config *from,
- unsigned size)
+ unsigned int size)
{
ia_css_encode_cc(to, from, size);
}
ia_css_rgb2yuv_encode(
struct sh_css_isp_csc_params *to,
const struct ia_css_cc_config *from,
- unsigned size)
+ unsigned int size)
{
ia_css_encode_cc(to, from, size);
}
ia_css_r_gamma_vamem_encode(
struct sh_css_isp_rgb_gamma_vamem_params *to,
const struct ia_css_rgb_gamma_table *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
- memcpy (&to->gc, &from->data, sizeof(to->gc));
+ memcpy(&to->gc, &from->data, sizeof(to->gc));
}
void
ia_css_g_gamma_vamem_encode(
struct sh_css_isp_rgb_gamma_vamem_params *to,
const struct ia_css_rgb_gamma_table *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
- memcpy (&to->gc, &from->data, sizeof(to->gc));
+ memcpy(&to->gc, &from->data, sizeof(to->gc));
}
void
ia_css_b_gamma_vamem_encode(
struct sh_css_isp_rgb_gamma_vamem_params *to,
const struct ia_css_rgb_gamma_table *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
- memcpy (&to->gc, &from->data, sizeof(to->gc));
+ memcpy(&to->gc, &from->data, sizeof(to->gc));
}
#ifndef IA_CSS_NO_DEBUG
void
ia_css_yuv2rgb_dump(
const struct sh_css_isp_csc_params *yuv2rgb,
- unsigned level)
+ unsigned int level)
{
ia_css_cc_dump(yuv2rgb, level, "YUV to RGB Conversion");
}
void
ia_css_rgb2yuv_dump(
const struct sh_css_isp_csc_params *rgb2yuv,
- unsigned level)
+ unsigned int level)
{
ia_css_cc_dump(rgb2yuv, level, "RGB to YUV Conversion");
}
void
ia_css_rgb_gamma_table_debug_dtrace(
const struct ia_css_rgb_gamma_table *config,
- unsigned level)
+ unsigned int level)
{
(void)config;
(void)level;
}
#endif
-
ia_css_yuv2rgb_encode(
struct sh_css_isp_csc_params *to,
const struct ia_css_cc_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_rgb2yuv_encode(
struct sh_css_isp_csc_params *to,
const struct ia_css_cc_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_r_gamma_vamem_encode(
struct sh_css_isp_rgb_gamma_vamem_params *to,
const struct ia_css_rgb_gamma_table *from,
- unsigned size);
+ unsigned int size);
void
ia_css_g_gamma_vamem_encode(
struct sh_css_isp_rgb_gamma_vamem_params *to,
const struct ia_css_rgb_gamma_table *from,
- unsigned size);
+ unsigned int size);
void
ia_css_b_gamma_vamem_encode(
struct sh_css_isp_rgb_gamma_vamem_params *to,
const struct ia_css_rgb_gamma_table *from,
- unsigned size);
+ unsigned int size);
#ifndef IA_CSS_NO_DEBUG
void
ia_css_yuv2rgb_dump(
const struct sh_css_isp_csc_params *yuv2rgb,
- unsigned level);
+ unsigned int level);
void
ia_css_rgb2yuv_dump(
const struct sh_css_isp_csc_params *rgb2yuv,
- unsigned level);
+ unsigned int level);
void
ia_css_rgb_gamma_table_debug_dtrace(
const struct ia_css_rgb_gamma_table *config,
- unsigned level);
+ unsigned int level);
#define ia_css_yuv2rgb_debug_dtrace ia_css_cc_config_debug_dtrace
#define ia_css_rgb2yuv_debug_dtrace ia_css_cc_config_debug_dtrace
/* This should be vamem_data_t, but that breaks the pipe generator */
struct sh_css_isp_rgb_gamma_vamem_params {
- uint16_t gc[SH_CSS_ISP_RGB_GAMMA_TABLE_SIZE];
+ u16 gc[SH_CSS_ISP_RGB_GAMMA_TABLE_SIZE];
};
#endif /* __IA_CSS_GC2_PARAM_H */
default_b_gamma_table.vamem_type = IA_CSS_VAMEM_TYPE_1;
#endif
}
-
/* Number of elements in the sRGB gamma table. */
#define IA_CSS_VAMEM_1_RGB_GAMMA_TABLE_SIZE_LOG2 8
-#define IA_CSS_VAMEM_1_RGB_GAMMA_TABLE_SIZE (1U<<IA_CSS_VAMEM_1_RGB_GAMMA_TABLE_SIZE_LOG2)
+#define IA_CSS_VAMEM_1_RGB_GAMMA_TABLE_SIZE BIT(IA_CSS_VAMEM_1_RGB_GAMMA_TABLE_SIZE_LOG2)
/* Number of elements in the sRGB gamma table. */
#define IA_CSS_VAMEM_2_RGB_GAMMA_TABLE_SIZE_LOG2 8
-#define IA_CSS_VAMEM_2_RGB_GAMMA_TABLE_SIZE ((1U<<IA_CSS_VAMEM_2_RGB_GAMMA_TABLE_SIZE_LOG2) + 1)
+#define IA_CSS_VAMEM_2_RGB_GAMMA_TABLE_SIZE ((1U << IA_CSS_VAMEM_2_RGB_GAMMA_TABLE_SIZE_LOG2) + 1)
/** IA_CSS_VAMEM_TYPE_1(ISP2300) or
IA_CSS_VAMEM_TYPE_2(ISP2400) */
union ia_css_rgb_gamma_data {
- uint16_t vamem_1[IA_CSS_VAMEM_1_RGB_GAMMA_TABLE_SIZE];
+ u16 vamem_1[IA_CSS_VAMEM_1_RGB_GAMMA_TABLE_SIZE];
/** RGB Gamma table on vamem type1. This table is not used,
because sRGB Gamma Correction is not implemented for ISP2300. */
- uint16_t vamem_2[IA_CSS_VAMEM_2_RGB_GAMMA_TABLE_SIZE];
+ u16 vamem_2[IA_CSS_VAMEM_2_RGB_GAMMA_TABLE_SIZE];
/** RGB Gamma table on vamem type2. u0.12, [0,4095] */
};
ia_css_hdr_init_config(
struct sh_css_isp_hdr_params *to,
const struct ia_css_hdr_config *from,
- unsigned size)
+ unsigned int size)
{
int i;
(void)size;
ia_css_hdr_init_config(
struct sh_css_isp_hdr_params *to,
const struct ia_css_hdr_config *from,
- unsigned size);
+ unsigned int size);
#endif /* __IA_CSS_HDR_HOST_H */
/* HDR irradiance map parameters on ISP. */
struct sh_css_hdr_irradiance_params {
- int32_t test_irr;
- int32_t match_shift[HDR_NUM_INPUT_FRAMES - 1]; /* Histogram matching shift parameter */
- int32_t match_mul[HDR_NUM_INPUT_FRAMES - 1]; /* Histogram matching multiplication parameter */
- int32_t thr_low[HDR_NUM_INPUT_FRAMES - 1]; /* Weight map soft threshold low bound parameter */
- int32_t thr_high[HDR_NUM_INPUT_FRAMES - 1]; /* Weight map soft threshold high bound parameter */
- int32_t thr_coeff[HDR_NUM_INPUT_FRAMES - 1]; /* Soft threshold linear function coefficient */
- int32_t thr_shift[HDR_NUM_INPUT_FRAMES - 1]; /* Soft threshold precision shift parameter */
- int32_t weight_bpp; /* Weight map bits per pixel */
+ s32 test_irr;
+ s32 match_shift[HDR_NUM_INPUT_FRAMES - 1]; /* Histogram matching shift parameter */
+ s32 match_mul[HDR_NUM_INPUT_FRAMES - 1]; /* Histogram matching multiplication parameter */
+ s32 thr_low[HDR_NUM_INPUT_FRAMES - 1]; /* Weight map soft threshold low bound parameter */
+ s32 thr_high[HDR_NUM_INPUT_FRAMES - 1]; /* Weight map soft threshold high bound parameter */
+ s32 thr_coeff[HDR_NUM_INPUT_FRAMES - 1]; /* Soft threshold linear function coefficient */
+ s32 thr_shift[HDR_NUM_INPUT_FRAMES - 1]; /* Soft threshold precision shift parameter */
+ s32 weight_bpp; /* Weight map bits per pixel */
};
/* HDR deghosting parameters on ISP */
struct sh_css_hdr_deghost_params {
- int32_t test_deg;
+ s32 test_deg;
};
/* HDR exclusion parameters on ISP */
struct sh_css_hdr_exclusion_params {
- int32_t test_excl;
+ s32 test_excl;
};
/* HDR ISP parameters */
const struct sh_css_binary_args *args)
{
const struct ia_css_frame *in_frame = args->in_frame;
- const struct ia_css_frame **out_frames = (const struct ia_css_frame **)& args->out_frame;
+ const struct ia_css_frame **out_frames = (const struct ia_css_frame **)&args->out_frame;
const struct ia_css_frame_info *in_frame_info = (in_frame) ? &in_frame->info : &binary->in_frame_info;
- const unsigned ddr_bits_per_element = sizeof(short) * 8;
- const unsigned ddr_elems_per_word = ceil_div(HIVE_ISP_DDR_WORD_BITS, ddr_bits_per_element);
- unsigned size_get = 0, size_put = 0;
- unsigned offset = 0;
+ const unsigned int ddr_bits_per_element = sizeof(short) * 8;
+ const unsigned int ddr_elems_per_word = ceil_div(HIVE_ISP_DDR_WORD_BITS, ddr_bits_per_element);
+ unsigned int size_get = 0, size_put = 0;
+ unsigned int offset = 0;
if (binary->info->mem_offsets.offsets.param) {
size_get = binary->info->mem_offsets.offsets.param->dmem.get.size;
#include "ia_css_binary.h"
#include "sh_css_internal.h"
-
void
ia_css_bayer_io_config(
const struct ia_css_binary *binary,
#define MAX_IO_DMA_CHANNELS 2
struct ia_css_common_io_config {
- unsigned base_address;
- unsigned width;
- unsigned height;
- unsigned stride;
- unsigned ddr_elems_per_word;
- unsigned dma_channel[MAX_IO_DMA_CHANNELS];
+ unsigned int base_address;
+ unsigned int width;
+ unsigned int height;
+ unsigned int stride;
+ unsigned int ddr_elems_per_word;
+ unsigned int dma_channel[MAX_IO_DMA_CHANNELS];
};
#endif /* __IA_CSS_COMMON_IO_TYPES */
const struct sh_css_binary_args *args)
{
const struct ia_css_frame *in_frame = args->in_frame;
- const struct ia_css_frame **out_frames = (const struct ia_css_frame **)& args->out_frame;
+ const struct ia_css_frame **out_frames = (const struct ia_css_frame **)&args->out_frame;
const struct ia_css_frame_info *in_frame_info = (in_frame) ? &in_frame->info : &binary->in_frame_info;
- const unsigned ddr_bits_per_element = sizeof(short) * 8;
- const unsigned ddr_elems_per_word = ceil_div(HIVE_ISP_DDR_WORD_BITS, ddr_bits_per_element);
- unsigned size_get = 0, size_put = 0;
- unsigned offset = 0;
+ const unsigned int ddr_bits_per_element = sizeof(short) * 8;
+ const unsigned int ddr_elems_per_word = ceil_div(HIVE_ISP_DDR_WORD_BITS, ddr_bits_per_element);
+ unsigned int size_get = 0, size_put = 0;
+ unsigned int offset = 0;
if (binary->info->mem_offsets.offsets.param) {
size_get = binary->info->mem_offsets.offsets.param->dmem.get.size;
#include "ia_css_binary.h"
#include "sh_css_internal.h"
-
void
ia_css_bayer_io_config(
const struct ia_css_binary *binary,
#define MAX_IO_DMA_CHANNELS 3
struct ia_css_common_io_config {
- unsigned base_address;
- unsigned width;
- unsigned height;
- unsigned stride;
- unsigned ddr_elems_per_word;
- unsigned dma_channel[MAX_IO_DMA_CHANNELS];
+ unsigned int base_address;
+ unsigned int width;
+ unsigned int height;
+ unsigned int stride;
+ unsigned int ddr_elems_per_word;
+ unsigned int dma_channel[MAX_IO_DMA_CHANNELS];
};
#endif /* __IA_CSS_COMMON_IO_TYPES */
const struct sh_css_binary_args *args)
{
const struct ia_css_frame *in_frame = args->in_frame;
- const struct ia_css_frame **out_frames = (const struct ia_css_frame **)& args->out_frame;
+ const struct ia_css_frame **out_frames = (const struct ia_css_frame **)&args->out_frame;
const struct ia_css_frame_info *in_frame_info = (in_frame) ? &in_frame->info : &binary->in_frame_info;
- const unsigned ddr_bits_per_element = sizeof(short) * 8;
- const unsigned ddr_elems_per_word = ceil_div(HIVE_ISP_DDR_WORD_BITS, ddr_bits_per_element);
- unsigned size_get = 0, size_put = 0;
- unsigned offset = 0;
+ const unsigned int ddr_bits_per_element = sizeof(short) * 8;
+ const unsigned int ddr_elems_per_word = ceil_div(HIVE_ISP_DDR_WORD_BITS, ddr_bits_per_element);
+ unsigned int size_get = 0, size_put = 0;
+ unsigned int offset = 0;
if (binary->info->mem_offsets.offsets.param) {
size_get = binary->info->mem_offsets.offsets.param->dmem.get.size;
#include "ia_css_binary.h"
#include "sh_css_internal.h"
-
void
ia_css_yuv444_io_config(
const struct ia_css_binary *binary,
ia_css_iterator_config(
struct sh_css_isp_iterator_isp_config *to,
const struct ia_css_iterator_configuration *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
ia_css_frame_info_to_frame_sp_info(&to->input_info, from->input_info);
ia_css_iterator_config(
struct sh_css_isp_iterator_isp_config *to,
const struct ia_css_iterator_configuration *from,
- unsigned size);
+ unsigned int size);
enum ia_css_err
ia_css_iterator_configure(
params->data[2][(idx)] = from->data[j + 2];
params->data[3][(idx)] = from->data[j + 3];
}
-
}
#ifndef IA_CSS_NO_DEBUG
/* MACC */
struct sh_css_isp_macc1_5_params {
- int32_t exp;
+ s32 exp;
};
struct sh_css_isp_macc1_5_vmem_params {
- VMEM_ARRAY(data, IA_CSS_MACC_NUM_COEFS*ISP_NWAY);
+ VMEM_ARRAY(data, IA_CSS_MACC_NUM_COEFS * ISP_NWAY);
};
#endif /* __IA_CSS_MACC1_5_PARAM_H */
* ISP2.6.1: MACC1_5 is used.
*/
-
/* Number of axes in the MACC table. */
#define IA_CSS_MACC_NUM_AXES 16
/* Number of coefficients per MACC axes. */
* OutV = ( 0 * InU + 4096 * InV) >> (13 - 1)
*/
struct ia_css_macc1_5_table {
- int16_t data[IA_CSS_MACC_NUM_COEFS * IA_CSS_MACC_NUM_AXES];
+ s16 data[IA_CSS_MACC_NUM_COEFS * IA_CSS_MACC_NUM_AXES];
/** 16 of 2x2 matix
MACC1_5: s[macc_config.exp].[13-macc_config.exp], [-8192,8191]
default/ineffective: (s1.12)
* ISP2: MACC1_5 is used.
*/
struct ia_css_macc1_5_config {
- uint8_t exp; /** Common exponent of ia_css_macc_table.
+ u8 exp; /** Common exponent of ia_css_macc_table.
u8.0, [0,13], default 1, ineffective 1 */
};
ia_css_macc_encode(
struct sh_css_isp_macc_params *to,
const struct ia_css_macc_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->exp = from->exp;
void
ia_css_macc_dump(
const struct sh_css_isp_macc_params *macc,
- unsigned level);
+ unsigned int level);
void
ia_css_macc_debug_dtrace(
const struct ia_css_macc_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
"config.exp=%d\n",
ia_css_macc_encode(
struct sh_css_isp_macc_params *to,
const struct ia_css_macc_config *from,
- unsigned size);
-
+ unsigned int size);
void
ia_css_macc_dump(
const struct sh_css_isp_macc_params *macc,
- unsigned level);
+ unsigned int level);
void
ia_css_macc_debug_dtrace(
const struct ia_css_macc_config *config,
- unsigned level);
+ unsigned int level);
#endif /* __IA_CSS_MACC_HOST_H */
/* MACC */
struct sh_css_isp_macc_params {
- int32_t exp;
+ s32 exp;
};
#endif /* __IA_CSS_MACC_PARAM_H */
#include "ia_css_macc_table.host.h"
/* Multi-Axes Color Correction table for ISP1.
- * 64values = 2x2matrix for 16area, [s2.13]
- * ineffective: 16 of "identity 2x2 matix" {8192,0,0,8192}
+ * 64values = 2x2matrix for 16area, [s2.13]
+ * ineffective: 16 of "identity 2x2 matix" {8192,0,0,8192}
*/
const struct ia_css_macc_table default_macc_table = {
{ 8192, 0, 0, 8192, 8192, 0, 0, 8192,
};
/* Multi-Axes Color Correction table for ISP2.
- * 64values = 2x2matrix for 16area, [s1.12]
- * ineffective: 16 of "identity 2x2 matix" {4096,0,0,4096}
+ * 64values = 2x2matrix for 16area, [s1.12]
+ * ineffective: 16 of "identity 2x2 matix" {4096,0,0,4096}
*/
const struct ia_css_macc_table default_macc2_table = {
{ 4096, 0, 0, 4096, 4096, 0, 0, 4096,
*/
struct ia_css_macc_table {
- int16_t data[IA_CSS_MACC_NUM_COEFS * IA_CSS_MACC_NUM_AXES];
+ s16 data[IA_CSS_MACC_NUM_COEFS * IA_CSS_MACC_NUM_AXES];
/** 16 of 2x2 matix
MACC1: s2.13, [-65536,65535]
default/ineffective:
*/
#include "ia_css_norm.host.h"
-
#ifndef __IA_CSS_NORM_PARAM_H
#define __IA_CSS_NORM_PARAM_H
-
#endif /* __IA_CSS_NORM_PARAM_H */
ia_css_ob2_encode(
struct sh_css_isp_ob2_params *to,
const struct ia_css_ob2_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
void
ia_css_ob2_dump(
const struct sh_css_isp_ob2_params *ob2,
- unsigned level)
+ unsigned int level)
{
if (!ob2)
return;
"ob2_blacklevel_b", ob2->blacklevel_b);
ia_css_debug_dtrace(level, "\t%-32s = %d\n",
"ob2_blacklevel_gb", ob2->blacklevel_gb);
-
}
-
void
ia_css_ob2_debug_dtrace(
const struct ia_css_ob2_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
- "config.level_gr=%d, config.level_r=%d, "
- "config.level_b=%d, config.level_gb=%d, ",
+ "config.level_gr=%d, config.level_r=%d, config.level_b=%d, config.level_gb=%d, ",
config->level_gr, config->level_r,
config->level_b, config->level_gb);
}
ia_css_ob2_encode(
struct sh_css_isp_ob2_params *to,
const struct ia_css_ob2_config *from,
- unsigned size);
+ unsigned int size);
#ifndef IA_CSS_NO_DEBUG
void
ia_css_ob2_dump(
const struct sh_css_isp_ob2_params *ob2,
- unsigned level);
+ unsigned int level);
void
ia_css_ob2_debug_dtrace(
- const struct ia_css_ob2_config *config, unsigned level);
+ const struct ia_css_ob2_config *config, unsigned int level);
#endif
#endif /* __IA_CSS_OB2_HOST_H */
#include "type_support.h"
-
/* OB2 (Optical Black) */
struct sh_css_isp_ob2_params {
- int32_t blacklevel_gr;
- int32_t blacklevel_r;
- int32_t blacklevel_b;
- int32_t blacklevel_gb;
+ s32 blacklevel_gr;
+ s32 blacklevel_r;
+ s32 blacklevel_b;
+ s32 blacklevel_gb;
};
#endif /* __IA_CSS_OB2_PARAM_H */
};
#endif /* __IA_CSS_OB2_TYPES_H */
-
struct sh_css_isp_ob_params *to,
const struct ia_css_ob_config *from,
const struct sh_css_isp_ob_stream_config *config,
- unsigned size)
+ unsigned int size)
{
unsigned int ob_bit_depth
= config->isp_pipe_version == 2 ? SH_CSS_BAYER_BITS : config->raw_bit_depth;
struct sh_css_isp_ob_vmem_params *to,
const struct ia_css_ob_config *from,
const struct sh_css_isp_ob_stream_config *config,
- unsigned size)
+ unsigned int size)
{
struct sh_css_isp_ob_params tmp;
struct sh_css_isp_ob_params *ob = &tmp;
ia_css_ob_encode(&tmp, from, config, sizeof(tmp));
{
- unsigned i;
- unsigned sp_obarea_start_bq = ob->area_start_bq;
- unsigned sp_obarea_length_bq = ob->area_length_bq;
- unsigned low = sp_obarea_start_bq;
- unsigned high = low + sp_obarea_length_bq;
- uint16_t all_ones = ~0;
+ unsigned int i;
+ unsigned int sp_obarea_start_bq = ob->area_start_bq;
+ unsigned int sp_obarea_length_bq = ob->area_length_bq;
+ unsigned int low = sp_obarea_start_bq;
+ unsigned int high = low + sp_obarea_length_bq;
+ u16 all_ones = ~0;
for (i = 0; i < OBAREA_MASK_SIZE; i++) {
if (i >= low && i < high)
- to->vmask[i/ISP_VEC_NELEMS][i%ISP_VEC_NELEMS] = all_ones;
+ to->vmask[i / ISP_VEC_NELEMS][i % ISP_VEC_NELEMS] = all_ones;
else
- to->vmask[i/ISP_VEC_NELEMS][i%ISP_VEC_NELEMS] = 0;
+ to->vmask[i / ISP_VEC_NELEMS][i % ISP_VEC_NELEMS] = 0;
}
}
}
void
ia_css_ob_dump(
const struct sh_css_isp_ob_params *ob,
- unsigned level)
+ unsigned int level)
{
if (!ob) return;
ia_css_debug_dtrace(level, "Optical Black:\n");
ob->area_length_bq_inverse);
}
-
void
ia_css_ob_debug_dtrace(
const struct ia_css_ob_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
- "config.mode=%d, "
- "config.level_gr=%d, config.level_r=%d, "
- "config.level_b=%d, config.level_gb=%d, "
- "config.start_position=%d, config.end_position=%d\n",
+ "config.mode=%d, config.level_gr=%d, config.level_r=%d, config.level_b=%d, config.level_gb=%d, config.start_position=%d, config.end_position=%d\n",
config->mode,
config->level_gr, config->level_r,
config->level_b, config->level_gb,
config->start_position, config->end_position);
}
-
struct sh_css_isp_ob_params *to,
const struct ia_css_ob_config *from,
const struct sh_css_isp_ob_stream_config *config,
- unsigned size);
+ unsigned int size);
void
ia_css_ob_vmem_encode(
struct sh_css_isp_ob_vmem_params *to,
const struct ia_css_ob_config *from,
const struct sh_css_isp_ob_stream_config *config,
- unsigned size);
+ unsigned int size);
void
ia_css_ob_dump(
const struct sh_css_isp_ob_params *ob,
- unsigned level);
+ unsigned int level);
void
ia_css_ob_debug_dtrace(
- const struct ia_css_ob_config *config, unsigned level)
+ const struct ia_css_ob_config *config, unsigned int level)
;
#endif /* __IA_CSS_OB_HOST_H */
#define OBAREA_LENGTHBQ_INVERSE_SHIFT 12
/* AREA_LENGTH_UNIT is dependent on NWAY, requires rewrite */
-#define AREA_LENGTH_UNIT (1<<12)
-
+#define AREA_LENGTH_UNIT BIT(12)
/* OB (Optical Black) */
struct sh_css_isp_ob_stream_config {
- unsigned isp_pipe_version;
- unsigned raw_bit_depth;
+ unsigned int isp_pipe_version;
+ unsigned int raw_bit_depth;
};
struct sh_css_isp_ob_params {
- int32_t blacklevel_gr;
- int32_t blacklevel_r;
- int32_t blacklevel_b;
- int32_t blacklevel_gb;
- int32_t area_start_bq;
- int32_t area_length_bq;
- int32_t area_length_bq_inverse;
+ s32 blacklevel_gr;
+ s32 blacklevel_r;
+ s32 blacklevel_b;
+ s32 blacklevel_gb;
+ s32 area_start_bq;
+ s32 area_length_bq;
+ s32 area_length_bq_inverse;
};
struct sh_css_isp_ob_vmem_params {
(used for Fixed Mode only).
u0.16, [0,65535],
default/ineffective 0 */
- uint16_t start_position; /** Start position of OB area
+ u16 start_position; /** Start position of OB area
(used for Raster Mode only).
u16.0, [0,63],
default/ineffective 0 */
- uint16_t end_position; /** End position of OB area
+ u16 end_position; /** End position of OB area
(used for Raster Mode only).
u16.0, [0,63],
default/ineffective 0 */
};
#endif /* __IA_CSS_OB_TYPES_H */
-
ia_css_output_encode(
struct sh_css_isp_output_params *to,
const struct ia_css_output_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->enable_hflip = from->enable_hflip;
ia_css_output_config(
struct sh_css_isp_output_isp_config *to,
const struct ia_css_output_configuration *from,
- unsigned size)
+ unsigned int size)
{
- unsigned elems_a = ISP_VEC_NELEMS;
+ unsigned int elems_a = ISP_VEC_NELEMS;
(void)size;
ia_css_dma_configure_from_info(&to->port_b, from->info);
ia_css_frame_info_to_frame_sp_info(&to->info, from->info);
/* Assume divisiblity here, may need to generalize to fixed point. */
- assert (elems_a % to->port_b.elems == 0);
+ assert(elems_a % to->port_b.elems == 0);
}
void
ia_css_output0_config(
struct sh_css_isp_output_isp_config *to,
const struct ia_css_output0_configuration *from,
- unsigned size)
+ unsigned int size)
{
- ia_css_output_config (
+ ia_css_output_config(
to, (const struct ia_css_output_configuration *)from, size);
}
ia_css_output1_config(
struct sh_css_isp_output_isp_config *to,
const struct ia_css_output1_configuration *from,
- unsigned size)
+ unsigned int size)
{
- ia_css_output_config (
+ ia_css_output_config(
to, (const struct ia_css_output_configuration *)from, size);
}
const struct ia_css_binary *binary,
const struct ia_css_frame_info *info)
{
- if (NULL != info) {
+ if (info) {
struct ia_css_output_configuration config =
default_output_configuration;
const struct ia_css_binary *binary,
const struct ia_css_frame_info *info)
{
- if (NULL != info) {
+ if (info) {
struct ia_css_output0_configuration config =
default_output0_configuration;
const struct ia_css_binary *binary,
const struct ia_css_frame_info *info)
{
-
- if (NULL != info) {
+ if (info) {
struct ia_css_output1_configuration config =
default_output1_configuration;
void
ia_css_output_dump(
const struct sh_css_isp_output_params *output,
- unsigned level)
+ unsigned int level)
{
if (!output) return;
ia_css_debug_dtrace(level, "Horizontal Output Flip:\n");
void
ia_css_output_debug_dtrace(
const struct ia_css_output_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
"config.enable_hflip=%d",
ia_css_output_encode(
struct sh_css_isp_output_params *to,
const struct ia_css_output_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_output_config(
struct sh_css_isp_output_isp_config *to,
const struct ia_css_output_configuration *from,
- unsigned size);
+ unsigned int size);
void
ia_css_output0_config(
struct sh_css_isp_output_isp_config *to,
const struct ia_css_output0_configuration *from,
- unsigned size);
+ unsigned int size);
void
ia_css_output1_config(
struct sh_css_isp_output_isp_config *to,
const struct ia_css_output1_configuration *from,
- unsigned size);
+ unsigned int size);
void
ia_css_output_configure(
void
ia_css_output_dump(
const struct sh_css_isp_output_params *output,
- unsigned level);
+ unsigned int level);
void
ia_css_output_debug_dtrace(
const struct ia_css_output_config *config,
- unsigned level);
+ unsigned int level);
#endif /* __IA_CSS_OUTPUT_HOST_H */
/* output frame */
struct sh_css_isp_output_isp_config {
- uint32_t width_a_over_b;
- uint32_t height;
- uint32_t enable;
+ u32 width_a_over_b;
+ u32 height;
+ u32 enable;
struct ia_css_frame_sp_info info;
struct dma_port_config port_b;
};
struct sh_css_isp_output_params {
- uint8_t enable_hflip;
- uint8_t enable_vflip;
+ u8 enable_hflip;
+ u8 enable_vflip;
};
#endif /* __IA_CSS_OUTPUT_PARAM_H */
};
struct ia_css_output_config {
- uint8_t enable_hflip; /** enable horizontal output mirroring */
- uint8_t enable_vflip; /** enable vertical output mirroring */
+ u8 enable_hflip; /** enable horizontal output mirroring */
+ u8 enable_vflip; /** enable vertical output mirroring */
};
#endif /* __IA_CSS_OUTPUT_TYPES_H */
-
ia_css_qplane_config(
struct sh_css_isp_qplane_isp_config *to,
const struct ia_css_qplane_configuration *from,
- unsigned size)
+ unsigned int size)
{
- unsigned elems_a = ISP_VEC_NELEMS;
+ unsigned int elems_a = ISP_VEC_NELEMS;
(void)size;
ia_css_dma_configure_from_info(&to->port_b, from->info);
to->width_a_over_b = elems_a / to->port_b.elems;
/* Assume divisiblity here, may need to generalize to fixed point. */
- assert (elems_a % to->port_b.elems == 0);
+ assert(elems_a % to->port_b.elems == 0);
to->inout_port_config = from->pipe->inout_port_config;
to->format = from->info->format;
ia_css_qplane_config(
struct sh_css_isp_qplane_isp_config *to,
const struct ia_css_qplane_configuration *from,
- unsigned size);
+ unsigned int size);
void
ia_css_qplane_configure(
/* qplane channel */
struct sh_css_isp_qplane_isp_config {
- uint32_t width_a_over_b;
+ u32 width_a_over_b;
struct dma_port_config port_b;
- uint32_t inout_port_config;
- uint32_t input_needs_raw_binning;
- uint32_t format; /* enum ia_css_frame_format */
+ u32 inout_port_config;
+ u32 input_needs_raw_binning;
+ u32 format; /* enum ia_css_frame_format */
};
#endif /* __IA_CSS_QPLANE_PARAM_H */
* ISP block: qplane frame
*/
-
struct ia_css_qplane_configuration {
const struct sh_css_sp_pipeline *pipe;
const struct ia_css_frame_info *info;
};
#endif /* __IA_CSS_QPLANE_TYPES_H */
-
#include "ia_css_raw.host.h"
-
static const struct ia_css_raw_configuration default_config = {
.pipe = (struct sh_css_sp_pipeline *)NULL,
};
static inline unsigned
-sh_css_elems_bytes_from_info (unsigned raw_bit_depth)
+sh_css_elems_bytes_from_info(unsigned int raw_bit_depth)
{
- return CEIL_DIV(raw_bit_depth,8);
+ return CEIL_DIV(raw_bit_depth, 8);
}
/* MW: These areMIPI / ISYS properties, not camera function properties */
ia_css_raw_config(
struct sh_css_isp_raw_isp_config *to,
const struct ia_css_raw_configuration *from,
- unsigned size)
+ unsigned int size)
{
- unsigned elems_a = ISP_VEC_NELEMS;
+ unsigned int elems_a = ISP_VEC_NELEMS;
const struct ia_css_frame_info *in_info = from->in_info;
const struct ia_css_frame_info *internal_info = from->internal_info;
bool two_ppc,
bool deinterleaved)
{
- uint8_t enable_left_padding = (uint8_t)((binary->left_padding) ? 1 : 0);
+ u8 enable_left_padding = (uint8_t)((binary->left_padding) ? 1 : 0);
struct ia_css_raw_configuration config = default_config;
config.pipe = pipe;
ia_css_raw_config(
struct sh_css_isp_raw_isp_config *to,
const struct ia_css_raw_configuration *from,
- unsigned size);
+ unsigned int size);
void
ia_css_raw_configure(
/* Raw channel */
struct sh_css_isp_raw_isp_config {
- uint32_t width_a_over_b;
+ u32 width_a_over_b;
struct dma_port_config port_b;
- uint32_t inout_port_config;
- uint32_t input_needs_raw_binning;
- uint32_t format; /* enum ia_css_frame_format */
- uint32_t required_bds_factor;
- uint32_t two_ppc;
- uint32_t stream_format; /* enum sh_stream_format */
- uint32_t deinterleaved;
- uint32_t start_column; /*left crop offset*/
- uint32_t start_line; /*top crop offset*/
- uint8_t enable_left_padding; /*need this for multiple binary case*/
+ u32 inout_port_config;
+ u32 input_needs_raw_binning;
+ u32 format; /* enum ia_css_frame_format */
+ u32 required_bds_factor;
+ u32 two_ppc;
+ u32 stream_format; /* enum sh_stream_format */
+ u32 deinterleaved;
+ u32 start_column; /*left crop offset*/
+ u32 start_line; /*top crop offset*/
+ u8 enable_left_padding; /*need this for multiple binary case*/
};
#endif /* __IA_CSS_RAW_PARAM_H */
bool two_ppc;
enum atomisp_input_format stream_format;
bool deinterleaved;
- uint8_t enable_left_padding;
+ u8 enable_left_padding;
};
#endif /* __IA_CSS_RAW_TYPES_H */
-
ia_css_raa_encode(
struct sh_css_isp_aa_params *to,
const struct ia_css_aa_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
(void)to;
ia_css_raa_encode(
struct sh_css_isp_aa_params *to,
const struct ia_css_aa_config *from,
- unsigned size);
+ unsigned int size);
#endif /* __IA_CSS_RAA_HOST_H */
ia_css_ref_config(
struct sh_css_isp_ref_isp_config *to,
const struct ia_css_ref_configuration *from,
- unsigned size)
+ unsigned int size)
{
- unsigned elems_a = ISP_VEC_NELEMS, i;
+ unsigned int elems_a = ISP_VEC_NELEMS, i;
(void)size;
- ia_css_dma_configure_from_info(&to->port_b, &(from->ref_frames[0]->info));
+ ia_css_dma_configure_from_info(&to->port_b, &from->ref_frames[0]->info);
to->width_a_over_b = elems_a / to->port_b.elems;
to->dvs_frame_delay = from->dvs_frame_delay;
for (i = 0; i < MAX_NUM_VIDEO_DELAY_FRAMES; i++) {
}
/* Assume divisiblity here, may need to generalize to fixed point. */
- assert (elems_a % to->port_b.elems == 0);
+ assert(elems_a % to->port_b.elems == 0);
}
void
const uint32_t dvs_frame_delay)
{
struct ia_css_ref_configuration config;
- unsigned i;
+ unsigned int i;
for (i = 0; i < MAX_NUM_VIDEO_DELAY_FRAMES; i++)
config.ref_frames[i] = ref_frames[i];
void
ia_css_init_ref_state(
struct sh_css_isp_ref_dmem_state *state,
- unsigned size)
+ unsigned int size)
{
(void)size;
assert(MAX_NUM_VIDEO_DELAY_FRAMES >= 2);
ia_css_ref_config(
struct sh_css_isp_ref_isp_config *to,
const struct ia_css_ref_configuration *from,
- unsigned size);
+ unsigned int size);
void
ia_css_ref_configure(
void
ia_css_init_ref_state(
struct sh_css_isp_ref_dmem_state *state,
- unsigned size);
+ unsigned int size);
#endif /* __IA_CSS_REF_HOST_H */
/* Reference frame */
struct ia_css_ref_configuration {
const struct ia_css_frame *ref_frames[MAX_NUM_VIDEO_DELAY_FRAMES];
- uint32_t dvs_frame_delay;
+ u32 dvs_frame_delay;
};
struct sh_css_isp_ref_isp_config {
- uint32_t width_a_over_b;
+ u32 width_a_over_b;
struct dma_port_config port_b;
hrt_vaddress ref_frame_addr_y[MAX_NUM_VIDEO_DELAY_FRAMES];
hrt_vaddress ref_frame_addr_c[MAX_NUM_VIDEO_DELAY_FRAMES];
- uint32_t dvs_frame_delay;
+ u32 dvs_frame_delay;
};
#endif /* __IA_CSS_REF_PARAM_H */
/* REF (temporal noise reduction) */
struct sh_css_isp_ref_dmem_state {
- int32_t ref_in_buf_idx;
- int32_t ref_out_buf_idx;
+ s32 ref_in_buf_idx;
+ s32 ref_out_buf_idx;
};
#endif /* __IA_CSS_REF_STATE_H */
#include <ia_css_frame_public.h>
-
-
#endif /* __IA_CSS_REF_TYPES_H */
-
ia_css_ae_encode(
struct sh_css_isp_ae_params *to,
const struct ia_css_3a_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
/* coefficients to calculate Y */
ia_css_awb_encode(
struct sh_css_isp_awb_params *to,
const struct ia_css_3a_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
/* AWB level gate */
ia_css_af_encode(
struct sh_css_isp_af_params *to,
const struct ia_css_3a_config *from,
- unsigned size)
+ unsigned int size)
{
unsigned int i;
(void)size;
ia_css_s3a_encode(
struct sh_css_isp_s3a_params *to,
const struct ia_css_3a_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
#if 0
void
ia_css_process_s3a(
- unsigned pipe_id,
+ unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params)
{
short dmem_offset = stage->binary->info->mem_offsets->dmem.s3a;
- assert(params != NULL);
+ assert(params);
if (dmem_offset >= 0) {
ia_css_s3a_encode((struct sh_css_isp_s3a_params *)
void
ia_css_ae_dump(
const struct sh_css_isp_ae_params *ae,
- unsigned level)
+ unsigned int level)
{
if (!ae) return;
ia_css_debug_dtrace(level, "\t%-32s = %d\n",
void
ia_css_awb_dump(
const struct sh_css_isp_awb_params *awb,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level, "\t%-32s = %d\n",
"awb_lg_high_raw", awb->lg_high_raw);
void
ia_css_af_dump(
const struct sh_css_isp_af_params *af,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level, "\t%-32s = %d\n",
"af_fir1[0]", af->fir1[0]);
void
ia_css_s3a_dump(
const struct sh_css_isp_s3a_params *s3a,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level, "S3A Support:\n");
- ia_css_ae_dump (&s3a->ae, level);
- ia_css_awb_dump (&s3a->awb, level);
- ia_css_af_dump (&s3a->af, level);
+ ia_css_ae_dump(&s3a->ae, level);
+ ia_css_awb_dump(&s3a->awb, level);
+ ia_css_af_dump(&s3a->af, level);
}
void
ia_css_s3a_debug_dtrace(
const struct ia_css_3a_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
- "config.ae_y_coef_r=%d, config.ae_y_coef_g=%d, "
- "config.ae_y_coef_b=%d, config.awb_lg_high_raw=%d, "
- "config.awb_lg_low=%d, config.awb_lg_high=%d\n",
+ "config.ae_y_coef_r=%d, config.ae_y_coef_g=%d, config.ae_y_coef_b=%d, config.awb_lg_high_raw=%d, config.awb_lg_low=%d, config.awb_lg_high=%d\n",
config->ae_y_coef_r, config->ae_y_coef_g,
config->ae_y_coef_b, config->awb_lg_high_raw,
config->awb_lg_low, config->awb_lg_high);
int count_for_3a;
int sum_r, diff;
- assert(host_stats != NULL);
- assert(host_stats->rgby_data != NULL);
- assert(hmem_buf != NULL);
+ assert(host_stats);
+ assert(host_stats->rgby_data);
+ assert(hmem_buf);
count_for_3a = host_stats->grid.width * host_stats->grid.height
* host_stats->grid.bqs_per_grid_cell
int sum_g = 0;
int sum_b = 0;
int sum_y = 0;
+
for (i = 0; i < HMEM_UNIT_SIZE; i++) {
sum_g += out_ptr[i].g;
sum_b += out_ptr[i].b;
int isp_width, host_width, height, i;
struct ia_css_3a_output *host_ptr;
- assert(host_stats != NULL);
- assert(host_stats->data != NULL);
- assert(isp_stats != NULL);
+ assert(host_stats);
+ assert(host_stats->data);
+ assert(isp_stats);
isp_width = host_stats->grid.aligned_width;
host_width = host_stats->grid.width;
static inline int
merge_hi_lo_14(unsigned short hi, unsigned short lo)
{
- int val = (int) ((((unsigned int) hi << 14) & 0xfffc000) |
- ((unsigned int) lo & 0x3fff));
+ int val = (int)((((unsigned int)hi << 14) & 0xfffc000) |
+ ((unsigned int)lo & 0x3fff));
return val;
}
void
ia_css_s3a_vmem_decode(
struct ia_css_3a_statistics *host_stats,
- const uint16_t *isp_stats_hi,
+ const u16 *isp_stats_hi,
const uint16_t *isp_stats_lo)
{
int out_width, out_height, chunk, rest, kmax, y, x, k, elm_start, elm, ofs;
- const uint16_t *hi, *lo;
+ const u16 *hi, *lo;
struct ia_css_3a_output *output;
- assert(host_stats!= NULL);
- assert(host_stats->data != NULL);
- assert(isp_stats_hi != NULL);
- assert(isp_stats_lo != NULL);
+ assert(host_stats);
+ assert(host_stats->data);
+ assert(isp_stats_hi);
+ assert(isp_stats_lo);
output = host_stats->data;
out_width = host_stats->grid.width;
ia_css_s3a_encode(
struct sh_css_isp_s3a_params *to,
const struct ia_css_3a_config *from,
- unsigned size);
+ unsigned int size);
#ifndef IA_CSS_NO_DEBUG
void
ia_css_ae_dump(
const struct sh_css_isp_ae_params *ae,
- unsigned level);
+ unsigned int level);
void
ia_css_awb_dump(
const struct sh_css_isp_awb_params *awb,
- unsigned level);
+ unsigned int level);
void
ia_css_af_dump(
const struct sh_css_isp_af_params *af,
- unsigned level);
+ unsigned int level);
void
ia_css_s3a_dump(
const struct sh_css_isp_s3a_params *s3a,
- unsigned level);
+ unsigned int level);
void
ia_css_s3a_debug_dtrace(
const struct ia_css_3a_config *config,
- unsigned level);
+ unsigned int level);
#endif
void
void
ia_css_s3a_vmem_decode(
struct ia_css_3a_statistics *host_stats,
- const uint16_t *isp_stats_hi,
+ const u16 *isp_stats_hi,
const uint16_t *isp_stats_lo);
#endif /* __IA_CSS_S3A_HOST_H */
/* AE (3A Support) */
struct sh_css_isp_ae_params {
/* coefficients to calculate Y */
- int32_t y_coef_r;
- int32_t y_coef_g;
- int32_t y_coef_b;
+ s32 y_coef_r;
+ s32 y_coef_g;
+ s32 y_coef_b;
};
/* AWB (3A Support) */
struct sh_css_isp_awb_params {
- int32_t lg_high_raw;
- int32_t lg_low;
- int32_t lg_high;
+ s32 lg_high_raw;
+ s32 lg_low;
+ s32 lg_high;
};
/* AF (3A Support) */
struct sh_css_isp_af_params {
- int32_t fir1[7];
- int32_t fir2[7];
+ s32 fir1[7];
+ s32 fir2[7];
};
/* S3A (3A Support) */
struct sh_css_isp_s3a_params {
/* coefficients to calculate Y */
struct sh_css_isp_ae_params ae;
-
+
/* AWB level gate */
struct sh_css_isp_awb_params awb;
struct sh_css_isp_af_params af;
};
-
#endif /* __IA_CSS_S3A_PARAM_H */
#include <ia_css_frac.h>
-#if (defined(SYSTEM_css_skycam_c0_system)) && (! defined(PIPE_GENERATION) )
+#if (defined(SYSTEM_css_skycam_c0_system)) && (!defined(PIPE_GENERATION))
#include "../../../../components/stats_3a/src/stats_3a_public.h"
#endif
* ISP2: S3A2 is used.
*/
struct ia_css_3a_grid_info {
-
#if defined(SYSTEM_css_skycam_c0_system)
- uint32_t ae_enable; /** ae enabled in binary,
+ u32 ae_enable; /** ae enabled in binary,
0:disabled, 1:enabled */
struct ae_public_config_grid_config ae_grd_info; /** see description in ae_public.h*/
- uint32_t awb_enable; /** awb enabled in binary,
+ u32 awb_enable; /** awb enabled in binary,
0:disabled, 1:enabled */
struct awb_public_config_grid_config awb_grd_info; /** see description in awb_public.h*/
- uint32_t af_enable; /** af enabled in binary,
+ u32 af_enable; /** af enabled in binary,
0:disabled, 1:enabled */
struct af_public_grid_config af_grd_info; /** see description in af_public.h*/
- uint32_t awb_fr_enable; /** awb_fr enabled in binary,
+ u32 awb_fr_enable; /** awb_fr enabled in binary,
0:disabled, 1:enabled */
struct awb_fr_public_grid_config awb_fr_grd_info;/** see description in awb_fr_public.h*/
- uint32_t elem_bit_depth; /** TODO:Taken from BYT - need input from AIQ
+ u32 elem_bit_depth; /** TODO:Taken from BYT - need input from AIQ
if needed for SKC
Bit depth of element used
to calculate 3A statistics.
bayer bit depth in DSP. */
#else
- uint32_t enable; /** 3A statistics enabled.
+ u32 enable; /** 3A statistics enabled.
0:disabled, 1:enabled */
- uint32_t use_dmem; /** DMEM or VMEM determines layout.
+ u32 use_dmem; /** DMEM or VMEM determines layout.
0:3A statistics are stored to VMEM,
1:3A statistics are stored to DMEM */
- uint32_t has_histogram; /** Statistics include histogram.
+ u32 has_histogram; /** Statistics include histogram.
0:no histogram, 1:has histogram */
- uint32_t width; /** Width of 3A grid table.
+ u32 width; /** Width of 3A grid table.
(= Horizontal number of grid cells
in table, which cells have effective
statistics.) */
- uint32_t height; /** Height of 3A grid table.
+ u32 height; /** Height of 3A grid table.
(= Vertical number of grid cells
in table, which cells have effective
statistics.) */
- uint32_t aligned_width; /** Horizontal stride (for alloc).
+ u32 aligned_width; /** Horizontal stride (for alloc).
(= Horizontal number of grid cells
in table, which means
the allocated width.) */
- uint32_t aligned_height; /** Vertical stride (for alloc).
+ u32 aligned_height; /** Vertical stride (for alloc).
(= Vertical number of grid cells
in table, which means
the allocated height.) */
- uint32_t bqs_per_grid_cell; /** Grid cell size in BQ(Bayer Quad) unit.
+ u32 bqs_per_grid_cell; /** Grid cell size in BQ(Bayer Quad) unit.
(1BQ means {Gr,R,B,Gb}(2x2 pixels).)
Valid values are 8,16,32,64. */
- uint32_t deci_factor_log2; /** log2 of bqs_per_grid_cell. */
- uint32_t elem_bit_depth; /** Bit depth of element used
+ u32 deci_factor_log2; /** log2 of bqs_per_grid_cell. */
+ u32 elem_bit_depth; /** Bit depth of element used
to calculate 3A statistics.
This is 13, which is the normalized
bayer bit depth in DSP. */
#endif
};
-
/* This struct should be split into 3, for AE, AWB and AF.
* However, that will require driver/ 3A lib modifications.
*/
* ISP2: S3A2 is used.
*/
struct ia_css_3a_output {
- int32_t ae_y; /** Sum of Y in a statistics window, for AE.
+ s32 ae_y; /** Sum of Y in a statistics window, for AE.
(u19.13) */
- int32_t awb_cnt; /** Number of effective pixels
+ s32 awb_cnt; /** Number of effective pixels
in a statistics window.
Pixels passed by the AWB level gate check are
judged as "effective". (u32) */
- int32_t awb_gr; /** Sum of Gr in a statistics window, for AWB.
+ s32 awb_gr; /** Sum of Gr in a statistics window, for AWB.
All Gr pixels (not only for effective pixels)
are summed. (u19.13) */
- int32_t awb_r; /** Sum of R in a statistics window, for AWB.
+ s32 awb_r; /** Sum of R in a statistics window, for AWB.
All R pixels (not only for effective pixels)
are summed. (u19.13) */
- int32_t awb_b; /** Sum of B in a statistics window, for AWB.
+ s32 awb_b; /** Sum of B in a statistics window, for AWB.
All B pixels (not only for effective pixels)
are summed. (u19.13) */
- int32_t awb_gb; /** Sum of Gb in a statistics window, for AWB.
+ s32 awb_gb; /** Sum of Gb in a statistics window, for AWB.
All Gb pixels (not only for effective pixels)
are summed. (u19.13) */
- int32_t af_hpf1; /** Sum of |Y| following high pass filter af_fir1
+ s32 af_hpf1; /** Sum of |Y| following high pass filter af_fir1
within a statistics window, for AF. (u19.13) */
- int32_t af_hpf2; /** Sum of |Y| following high pass filter af_fir2
+ s32 af_hpf2; /** Sum of |Y| following high pass filter af_fir2
within a statistics window, for AF. (u19.13) */
};
-
/* 3A Statistics. This structure describes the statistics that are generated
* using the provided configuration (ia_css_3a_config).
*/
* ISP2: HIST2 is used.
*/
struct ia_css_3a_rgby_output {
- uint32_t r; /** Number of R of one bin of the histogram R. (u24) */
- uint32_t g; /** Number of G of one bin of the histogram G. (u24) */
- uint32_t b; /** Number of B of one bin of the histogram B. (u24) */
- uint32_t y; /** Number of Y of one bin of the histogram Y. (u24) */
+ u32 r; /** Number of R of one bin of the histogram R. (u24) */
+ u32 g; /** Number of G of one bin of the histogram G. (u24) */
+ u32 b; /** Number of B of one bin of the histogram B. (u24) */
+ u32 y; /** Number of Y of one bin of the histogram Y. (u24) */
};
#endif /* __IA_CSS_S3A_TYPES_H */
-
ia_css_sc_encode(
struct sh_css_isp_sc_params *to,
struct ia_css_shading_table **from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->gain_shift = (*from)->fraction_bits;
void
ia_css_sc_dump(
const struct sh_css_isp_sc_params *sc,
- unsigned level)
+ unsigned int level)
{
if (!sc) return;
ia_css_debug_dtrace(level, "Shading Correction:\n");
ia_css_sc_config(
struct sh_css_isp_sc_isp_config *to,
const struct ia_css_sc_configuration *from,
- unsigned size)
+ unsigned int size)
{
- uint32_t internal_org_x_bqs = from->internal_frame_origin_x_bqs_on_sctbl;
- uint32_t internal_org_y_bqs = from->internal_frame_origin_y_bqs_on_sctbl;
- uint32_t slice, rest, i;
+ u32 internal_org_x_bqs = from->internal_frame_origin_x_bqs_on_sctbl;
+ u32 internal_org_y_bqs = from->internal_frame_origin_y_bqs_on_sctbl;
+ u32 slice, rest, i;
(void)size;
void
ia_css_sc_configure(
const struct ia_css_binary *binary,
- uint32_t internal_frame_origin_x_bqs_on_sctbl,
+ u32 internal_frame_origin_x_bqs_on_sctbl,
uint32_t internal_frame_origin_y_bqs_on_sctbl)
{
const struct ia_css_sc_configuration config = {
sh_css_get_shading_settings(const struct ia_css_isp_parameters *params,
struct ia_css_shading_settings *settings)
{
- if (settings == NULL)
+ if (!settings)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_get_shading_settings() enter: settings=%p\n", settings);
sh_css_set_shading_settings(struct ia_css_isp_parameters *params,
const struct ia_css_shading_settings *settings)
{
- if (settings == NULL)
+ if (!settings)
return;
- assert(params != NULL);
+ assert(params);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_set_shading_settings() enter: settings.enable_shading_table_conversion=%d\n",
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_set_shading_settings() leave: return_void\n");
}
+
/* ------ deprecated(bz675) : to ------ */
ia_css_sc_encode(
struct sh_css_isp_sc_params *to,
struct ia_css_shading_table **from,
- unsigned size);
+ unsigned int size);
void
ia_css_sc_dump(
const struct sh_css_isp_sc_params *sc,
- unsigned level);
+ unsigned int level);
#ifdef ISP2401
/* @brief Configure the shading correction.
ia_css_sc_config(
struct sh_css_isp_sc_isp_config *to,
const struct ia_css_sc_configuration *from,
- unsigned size);
+ unsigned int size);
/* @brief Configure the shading correction.
* @param[in] binary The binary, which has the shading correction.
void
ia_css_sc_configure(
const struct ia_css_binary *binary,
- uint32_t internal_frame_origin_x_bqs_on_sctbl,
+ u32 internal_frame_origin_x_bqs_on_sctbl,
uint32_t internal_frame_origin_y_bqs_on_sctbl);
#endif
#endif
/* SC (Shading Corrction) */
struct sh_css_isp_sc_params {
- int32_t gain_shift;
+ s32 gain_shift;
};
#ifdef ISP2401
#define SH_CSS_SC_INTERPED_GAIN_HOR_SLICE_TIMES 8
struct sh_css_isp_sc_isp_config {
- uint32_t interped_gain_hor_slice_bqs[SH_CSS_SC_INTERPED_GAIN_HOR_SLICE_TIMES];
- uint32_t internal_frame_origin_y_bqs_on_sctbl;
+ u32 interped_gain_hor_slice_bqs[SH_CSS_SC_INTERPED_GAIN_HOR_SLICE_TIMES];
+ u32 internal_frame_origin_y_bqs_on_sctbl;
};
#endif
* CSS-API header file for Lens Shading Correction (SC) parameters.
*/
-
/* Number of color planes in the shading table. */
#define IA_CSS_SC_NUM_COLORS 4
* ISP2: SC1 is used.
*/
struct ia_css_shading_table {
- uint32_t enable; /** Set to false for no shading correction.
- The data field can be NULL when enable == true */
+ u32 enable; /** Set to false for no shading correction.
+ The data field can be NULL when enable == true */
/* ------ deprecated(bz675) : from ------ */
- uint32_t sensor_width; /** Native sensor width in pixels. */
- uint32_t sensor_height; /** Native sensor height in lines.
+ u32 sensor_width; /** Native sensor width in pixels. */
+ u32 sensor_height; /** Native sensor height in lines.
When shading_settings.enable_shading_table_conversion is set
as 0, sensor_width and sensor_height are NOT used.
These are used only in the legacy shading table conversion
in the css, when shading_settings.
enable_shading_table_conversion is set as 1. */
/* ------ deprecated(bz675) : to ------ */
- uint32_t width; /** Number of data points per line per color.
+ u32 width; /** Number of data points per line per color.
u8.0, [0,81] */
- uint32_t height; /** Number of lines of data points per color.
+ u32 height; /** Number of lines of data points per color.
u8.0, [0,61] */
- uint32_t fraction_bits; /** Bits of fractional part in the data
+ u32 fraction_bits; /** Bits of fractional part in the data
points.
u8.0, [0,13] */
- uint16_t *data[IA_CSS_SC_NUM_COLORS];
+ u16 *data[IA_CSS_SC_NUM_COLORS];
/** Table data, one array for each color.
Use ia_css_sc_color to index this array.
u[13-fraction_bits].[fraction_bits], [0,8191] */
* removed from the css.
*/
struct ia_css_shading_settings {
- uint32_t enable_shading_table_conversion; /** Set to 0,
+ u32 enable_shading_table_conversion; /** Set to 0,
if the conversion of the shading table should be disabled
in the css. (default 1)
0: The shading table is directly sent to the isp.
enable_shading_table_conversion is set as 1 by default
in the css. */
};
+
/* ------ deprecated(bz675) : to ------ */
#ifdef ISP2401
* NOTE: The shading table size is larger than or equal to the internal frame size.
*/
struct ia_css_sc_configuration {
- uint32_t internal_frame_origin_x_bqs_on_sctbl; /** Origin X (in bqs) of internal frame on shading table. */
- uint32_t internal_frame_origin_y_bqs_on_sctbl; /** Origin Y (in bqs) of internal frame on shading table. */
+ u32 internal_frame_origin_x_bqs_on_sctbl; /** Origin X (in bqs) of internal frame on shading table. */
+ u32 internal_frame_origin_y_bqs_on_sctbl; /** Origin Y (in bqs) of internal frame on shading table. */
/** NOTE: bqs = size in BQ(Bayer Quad) unit.
1BQ means {Gr,R,B,Gb}(2x2 pixels).
Horizontal 1 bqs corresponds to horizontal 2 pixels.
IA_CSS_DVS_NUM_COEF_TYPES)
#ifndef PIPE_GENERATION
-#if defined(__ISP) || defined (MK_FIRMWARE)
+#if defined(__ISP) || defined(MK_FIRMWARE)
/* Array cannot be 2-dimensional, since driver ddr allocation does not know stride */
struct sh_css_isp_sdis_hori_proj_tbl {
- int32_t tbl[ISP_DVS_NUM_COEF_TYPES * ISP_MAX_SDIS_HOR_PROJ_NUM_ISP];
+ s32 tbl[ISP_DVS_NUM_COEF_TYPES * ISP_MAX_SDIS_HOR_PROJ_NUM_ISP];
#if DVS2_PROJ_MARGIN > 0
- int32_t margin[DVS2_PROJ_MARGIN];
+ s32 margin[DVS2_PROJ_MARGIN];
#endif
};
struct sh_css_isp_sdis_vert_proj_tbl {
- int32_t tbl[ISP_DVS_NUM_COEF_TYPES * ISP_MAX_SDIS_VER_PROJ_NUM_ISP];
+ s32 tbl[ISP_DVS_NUM_COEF_TYPES * ISP_MAX_SDIS_VER_PROJ_NUM_ISP];
#if DVS2_PROJ_MARGIN > 0
- int32_t margin[DVS2_PROJ_MARGIN];
+ s32 margin[DVS2_PROJ_MARGIN];
#endif
};
struct sh_css_isp_sdis_hori_coef_tbl {
- VMEM_ARRAY(tbl[ISP_DVS_NUM_COEF_TYPES], ISP_MAX_SDIS_HOR_COEF_NUM_VECS*ISP_NWAY);
+ VMEM_ARRAY(tbl[ISP_DVS_NUM_COEF_TYPES], ISP_MAX_SDIS_HOR_COEF_NUM_VECS * ISP_NWAY);
};
struct sh_css_isp_sdis_vert_coef_tbl {
- VMEM_ARRAY(tbl[ISP_DVS_NUM_COEF_TYPES], ISP_MAX_SDIS_VER_COEF_NUM_VECS*ISP_NWAY);
+ VMEM_ARRAY(tbl[ISP_DVS_NUM_COEF_TYPES], ISP_MAX_SDIS_VER_COEF_NUM_VECS * ISP_NWAY);
};
#endif /* defined(__ISP) || defined (MK_FIRMWARE) */
#ifndef PIPE_GENERATION
struct s_sdis_config {
- unsigned horicoef_vectors;
- unsigned vertcoef_vectors;
- unsigned horiproj_num;
- unsigned vertproj_num;
+ unsigned int horicoef_vectors;
+ unsigned int vertcoef_vectors;
+ unsigned int horiproj_num;
+ unsigned int vertproj_num;
};
extern struct s_sdis_config sdis_config;
*/
struct ia_css_dvs_grid_dim {
- uint32_t width; /** Width of DVS grid table in cells */
- uint32_t height; /** Height of DVS grid table in cells */
+ u32 width; /** Width of DVS grid table in cells */
+ u32 height; /** Height of DVS grid table in cells */
};
/* DVS statistics dimensions in number of cells for
struct ia_css_dvs_grid_dim dim; /* Dimensions */
struct ia_css_dvs_grid_dim pad; /* Padded dimensions */
} grid, coef, proj;
- uint32_t deci_factor_log2;
+ u32 deci_factor_log2;
};
/* DVS statistics grid
* ISP2: SDVS2 is used.
*/
struct ia_css_dvs_grid_res {
- uint32_t width; /** Width of DVS grid table.
+ u32 width; /** Width of DVS grid table.
(= Horizontal number of grid cells
in table, which cells have effective
statistics.)
For DVS1, this is equal to
the number of vertical statistics. */
- uint32_t aligned_width; /** Stride of each grid line.
+ u32 aligned_width; /** Stride of each grid line.
(= Horizontal number of grid cells
in table, which means
the allocated width.) */
- uint32_t height; /** Height of DVS grid table.
+ u32 height; /** Height of DVS grid table.
(= Vertical number of grid cells
in table, which cells have effective
statistics.)
For DVS1, This is equal to
the number of horizontal statistics. */
- uint32_t aligned_height;/** Stride of each grid column.
+ u32 aligned_height;/** Stride of each grid column.
(= Vertical number of grid cells
in table, which means
the allocated height.) */
* However, that implies driver I/F changes
*/
struct ia_css_dvs_grid_info {
- uint32_t enable; /** DVS statistics enabled.
+ u32 enable; /** DVS statistics enabled.
0:disabled, 1:enabled */
- uint32_t width; /** Width of DVS grid table.
+ u32 width; /** Width of DVS grid table.
(= Horizontal number of grid cells
in table, which cells have effective
statistics.)
For DVS1, this is equal to
the number of vertical statistics. */
- uint32_t aligned_width; /** Stride of each grid line.
+ u32 aligned_width; /** Stride of each grid line.
(= Horizontal number of grid cells
in table, which means
the allocated width.) */
- uint32_t height; /** Height of DVS grid table.
+ u32 height; /** Height of DVS grid table.
(= Vertical number of grid cells
in table, which cells have effective
statistics.)
For DVS1, This is equal to
the number of horizontal statistics. */
- uint32_t aligned_height;/** Stride of each grid column.
+ u32 aligned_height;/** Stride of each grid column.
(= Vertical number of grid cells
in table, which means
the allocated height.) */
- uint32_t bqs_per_grid_cell; /** Grid cell size in BQ(Bayer Quad) unit.
+ u32 bqs_per_grid_cell; /** Grid cell size in BQ(Bayer Quad) unit.
(1BQ means {Gr,R,B,Gb}(2x2 pixels).)
For DVS1, valid value is 64.
For DVS2, valid value is only 64,
currently. */
- uint32_t num_hor_coefs; /** Number of horizontal coefficients. */
- uint32_t num_ver_coefs; /** Number of vertical coefficients. */
+ u32 num_hor_coefs; /** Number of horizontal coefficients. */
+ u32 num_ver_coefs; /** Number of vertical coefficients. */
};
/* Number of DVS statistics levels
};
static void
-fill_row(short *private, const short *public, unsigned width, unsigned padding)
+fill_row(short *private, const short *public, unsigned int width, unsigned int padding)
{
assert((int)width >= 0);
assert((int)padding >= 0);
- memcpy (private, public, width*sizeof(short));
- memset (&private[width], 0, padding*sizeof(short));
+ memcpy(private, public, width * sizeof(short));
+ memset(&private[width], 0, padding * sizeof(short));
}
-void ia_css_sdis_horicoef_vmem_encode (
+void ia_css_sdis_horicoef_vmem_encode(
struct sh_css_isp_sdis_hori_coef_tbl *to,
const struct ia_css_dvs_coefficients *from,
- unsigned size)
+ unsigned int size)
{
- unsigned aligned_width = from->grid.aligned_width * from->grid.bqs_per_grid_cell;
- unsigned width = from->grid.num_hor_coefs;
- int padding = aligned_width-width;
- unsigned stride = size/IA_CSS_DVS_NUM_COEF_TYPES/sizeof(short);
- unsigned total_bytes = aligned_width*IA_CSS_DVS_NUM_COEF_TYPES*sizeof(short);
+ unsigned int aligned_width = from->grid.aligned_width * from->grid.bqs_per_grid_cell;
+ unsigned int width = from->grid.num_hor_coefs;
+ int padding = aligned_width - width;
+ unsigned int stride = size / IA_CSS_DVS_NUM_COEF_TYPES / sizeof(short);
+ unsigned int total_bytes = aligned_width * IA_CSS_DVS_NUM_COEF_TYPES * sizeof(short);
short *public = from->hor_coefs;
- short *private = (short*)to;
- unsigned type;
+ short *private = (short *)to;
+ unsigned int type;
/* Copy the table, add padding */
assert(padding >= 0);
assert(total_bytes <= size);
- assert(size % (IA_CSS_DVS_NUM_COEF_TYPES*ISP_VEC_NELEMS*sizeof(short)) == 0);
+ assert(size % (IA_CSS_DVS_NUM_COEF_TYPES * ISP_VEC_NELEMS * sizeof(short)) == 0);
for (type = 0; type < IA_CSS_DVS_NUM_COEF_TYPES; type++) {
- fill_row(&private[type*stride], &public[type*width], width, padding);
+ fill_row(&private[type * stride], &public[type * width], width, padding);
}
}
-void ia_css_sdis_vertcoef_vmem_encode (
+void ia_css_sdis_vertcoef_vmem_encode(
struct sh_css_isp_sdis_vert_coef_tbl *to,
const struct ia_css_dvs_coefficients *from,
- unsigned size)
+ unsigned int size)
{
- unsigned aligned_height = from->grid.aligned_height * from->grid.bqs_per_grid_cell;
- unsigned height = from->grid.num_ver_coefs;
- int padding = aligned_height-height;
- unsigned stride = size/IA_CSS_DVS_NUM_COEF_TYPES/sizeof(short);
- unsigned total_bytes = aligned_height*IA_CSS_DVS_NUM_COEF_TYPES*sizeof(short);
+ unsigned int aligned_height = from->grid.aligned_height * from->grid.bqs_per_grid_cell;
+ unsigned int height = from->grid.num_ver_coefs;
+ int padding = aligned_height - height;
+ unsigned int stride = size / IA_CSS_DVS_NUM_COEF_TYPES / sizeof(short);
+ unsigned int total_bytes = aligned_height * IA_CSS_DVS_NUM_COEF_TYPES * sizeof(short);
short *public = from->ver_coefs;
- short *private = (short*)to;
- unsigned type;
+ short *private = (short *)to;
+ unsigned int type;
/* Copy the table, add padding */
assert(padding >= 0);
assert(total_bytes <= size);
- assert(size % (IA_CSS_DVS_NUM_COEF_TYPES*ISP_VEC_NELEMS*sizeof(short)) == 0);
+ assert(size % (IA_CSS_DVS_NUM_COEF_TYPES * ISP_VEC_NELEMS * sizeof(short)) == 0);
for (type = 0; type < IA_CSS_DVS_NUM_COEF_TYPES; type++) {
- fill_row(&private[type*stride], &public[type*height], height, padding);
+ fill_row(&private[type * stride], &public[type * height], height, padding);
}
}
-void ia_css_sdis_horiproj_encode (
+void ia_css_sdis_horiproj_encode(
struct sh_css_isp_sdis_hori_proj_tbl *to,
const struct ia_css_dvs_coefficients *from,
- unsigned size)
+ unsigned int size)
{
(void)to;
(void)from;
(void)size;
}
-void ia_css_sdis_vertproj_encode (
+void ia_css_sdis_vertproj_encode(
struct sh_css_isp_sdis_vert_proj_tbl *to,
const struct ia_css_dvs_coefficients *from,
- unsigned size)
+ unsigned int size)
{
(void)to;
(void)from;
IA_CSS_ENTER("void");
- assert(horizontal_coefficients != NULL);
- assert(vertical_coefficients != NULL);
+ assert(horizontal_coefficients);
+ assert(vertical_coefficients);
params = stream->isp_params_configs;
ver_num_3a = dvs_binary->dis.coef.dim.height;
for (i = 0; i < IA_CSS_DVS_NUM_COEF_TYPES; i++) {
- fill_row(&horizontal_coefficients[i*hor_num_isp],
- ¶ms->dvs_coefs.hor_coefs[i*hor_num_3a], hor_num_3a, hor_num_isp-hor_num_3a);
+ fill_row(&horizontal_coefficients[i * hor_num_isp],
+ ¶ms->dvs_coefs.hor_coefs[i * hor_num_3a], hor_num_3a, hor_num_isp - hor_num_3a);
}
for (i = 0; i < SH_CSS_DIS_VER_NUM_COEF_TYPES(dvs_binary); i++) {
- fill_row(&vertical_coefficients[i*ver_num_isp],
- ¶ms->dvs_coefs.ver_coefs[i*ver_num_3a], ver_num_3a, ver_num_isp-ver_num_3a);
+ fill_row(&vertical_coefficients[i * ver_num_isp],
+ ¶ms->dvs_coefs.ver_coefs[i * ver_num_3a], ver_num_3a, ver_num_isp - ver_num_3a);
}
IA_CSS_LEAVE("void");
void
ia_css_sdis_init_info(
struct ia_css_sdis_info *dis,
- unsigned sc_3a_dis_width,
- unsigned sc_3a_dis_padded_width,
- unsigned sc_3a_dis_height,
- unsigned isp_pipe_version,
- unsigned enabled)
+ unsigned int sc_3a_dis_width,
+ unsigned int sc_3a_dis_padded_width,
+ unsigned int sc_3a_dis_height,
+ unsigned int isp_pipe_version,
+ unsigned int enabled)
{
if (!enabled) {
*dis = (struct ia_css_sdis_info) { };
IA_CSS_ENTER("host_stats=%p, isp_stats=%p", host_stats, isp_stats);
- assert(host_stats != NULL);
- assert(isp_stats != NULL);
+ assert(host_stats);
+ assert(isp_stats);
map = ia_css_isp_dvs_statistics_map_allocate(isp_stats, NULL);
if (map) {
const struct ia_css_isp_dvs_statistics_map *isp_stats)
{
unsigned int hor_num_isp, ver_num_isp, hor_num_dvs, ver_num_dvs, i;
- int32_t *hor_ptr_dvs, *ver_ptr_dvs, *hor_ptr_isp, *ver_ptr_isp;
+ s32 *hor_ptr_dvs, *ver_ptr_dvs, *hor_ptr_isp, *ver_ptr_isp;
- assert(host_stats != NULL);
- assert(host_stats->hor_proj != NULL);
- assert(host_stats->ver_proj != NULL);
- assert(isp_stats != NULL);
- assert(isp_stats->hor_proj != NULL);
- assert(isp_stats->ver_proj != NULL);
+ assert(host_stats);
+ assert(host_stats->hor_proj);
+ assert(host_stats->ver_proj);
+ assert(isp_stats);
+ assert(isp_stats->hor_proj);
+ assert(isp_stats->ver_proj);
IA_CSS_ENTER("hproj=%p, vproj=%p, haddr=%p, vaddr=%p",
host_stats->hor_proj, host_stats->ver_proj,
struct ia_css_isp_dvs_statistics *me;
int hor_size, ver_size;
- assert(grid != NULL);
+ assert(grid);
IA_CSS_ENTER("grid=%p", grid);
if (!grid->enable)
return NULL;
- me = sh_css_calloc(1,sizeof(*me));
+ me = sh_css_calloc(1, sizeof(*me));
if (!me)
goto err;
ver_size = CEIL_MUL(sizeof(int) * IA_CSS_DVS_NUM_COEF_TYPES * grid->aligned_width,
HIVE_ISP_DDR_WORD_BYTES);
-
me->size = hor_size + ver_size;
me->data_ptr = mmgr_malloc(me->size);
if (me->data_ptr == mmgr_NULL)
}
me->data_ptr = data_ptr;
- me->data_allocated = data_ptr == NULL;
+ me->data_allocated = !data_ptr;
if (!me->data_ptr) {
me->data_ptr = sh_css_malloc(isp_stats->size);
me->size = isp_stats->size;
/* GCC complains when we assign a char * to a void *, so these
* casts are necessary unfortunately. */
- me->hor_proj = (void*)base_ptr;
- me->ver_proj = (void*)(base_ptr + isp_stats->hor_size);
+ me->hor_proj = (void *)base_ptr;
+ me->ver_proj = (void *)(base_ptr + isp_stats->hor_size);
return me;
err:
void
ia_css_isp_dvs_statistics_free(struct ia_css_isp_dvs_statistics *me)
{
- if (me != NULL) {
+ if (me) {
hmm_free(me->data_ptr);
sh_css_free(me);
}
}
void ia_css_sdis_horicoef_debug_dtrace(
- const struct ia_css_dvs_coefficients *config, unsigned level)
+ const struct ia_css_dvs_coefficients *config, unsigned int level)
{
(void)config;
(void)level;
}
void ia_css_sdis_vertcoef_debug_dtrace(
- const struct ia_css_dvs_coefficients *config, unsigned level)
+ const struct ia_css_dvs_coefficients *config, unsigned int level)
{
(void)config;
(void)level;
}
void ia_css_sdis_horiproj_debug_dtrace(
- const struct ia_css_dvs_coefficients *config, unsigned level)
+ const struct ia_css_dvs_coefficients *config, unsigned int level)
{
(void)config;
(void)level;
}
void ia_css_sdis_vertproj_debug_dtrace(
- const struct ia_css_dvs_coefficients *config, unsigned level)
+ const struct ia_css_dvs_coefficients *config, unsigned int level)
{
(void)config;
(void)level;
struct sh_css_isp_sdis_hori_proj_tbl;
struct sh_css_isp_sdis_vert_proj_tbl;
-void ia_css_sdis_horicoef_vmem_encode (
+void ia_css_sdis_horicoef_vmem_encode(
struct sh_css_isp_sdis_hori_coef_tbl *to,
const struct ia_css_dvs_coefficients *from,
- unsigned size);
+ unsigned int size);
-void ia_css_sdis_vertcoef_vmem_encode (
+void ia_css_sdis_vertcoef_vmem_encode(
struct sh_css_isp_sdis_vert_coef_tbl *to,
const struct ia_css_dvs_coefficients *from,
- unsigned size);
+ unsigned int size);
-void ia_css_sdis_horiproj_encode (
+void ia_css_sdis_horiproj_encode(
struct sh_css_isp_sdis_hori_proj_tbl *to,
const struct ia_css_dvs_coefficients *from,
- unsigned size);
+ unsigned int size);
-void ia_css_sdis_vertproj_encode (
+void ia_css_sdis_vertproj_encode(
struct sh_css_isp_sdis_vert_proj_tbl *to,
const struct ia_css_dvs_coefficients *from,
- unsigned size);
+ unsigned int size);
void ia_css_get_isp_dis_coefficients(
struct ia_css_stream *stream,
void
ia_css_sdis_init_info(
struct ia_css_sdis_info *dis,
- unsigned sc_3a_dis_width,
- unsigned sc_3a_dis_padded_width,
- unsigned sc_3a_dis_height,
- unsigned isp_pipe_version,
- unsigned enabled);
+ unsigned int sc_3a_dis_width,
+ unsigned int sc_3a_dis_padded_width,
+ unsigned int sc_3a_dis_height,
+ unsigned int isp_pipe_version,
+ unsigned int enabled);
void ia_css_sdis_clear_coefficients(
struct ia_css_dvs_coefficients *dvs_coefs);
void ia_css_sdis_horicoef_debug_dtrace(
- const struct ia_css_dvs_coefficients *config, unsigned level);
+ const struct ia_css_dvs_coefficients *config, unsigned int level);
void ia_css_sdis_vertcoef_debug_dtrace(
- const struct ia_css_dvs_coefficients *config, unsigned level);
+ const struct ia_css_dvs_coefficients *config, unsigned int level);
void ia_css_sdis_horiproj_debug_dtrace(
- const struct ia_css_dvs_coefficients *config, unsigned level);
+ const struct ia_css_dvs_coefficients *config, unsigned int level);
void ia_css_sdis_vertproj_debug_dtrace(
- const struct ia_css_dvs_coefficients *config, unsigned level);
+ const struct ia_css_dvs_coefficients *config, unsigned int level);
#endif /* __IA_CSS_SDIS_HOST_H */
struct ia_css_dvs_coefficients {
struct ia_css_dvs_grid_info grid;/** grid info contains the dimensions of the dvs grid */
- int16_t *hor_coefs; /** the pointer to int16_t[grid.num_hor_coefs * IA_CSS_DVS_NUM_COEF_TYPES]
+ s16 *hor_coefs; /** the pointer to int16_t[grid.num_hor_coefs * IA_CSS_DVS_NUM_COEF_TYPES]
containing the horizontal coefficients */
- int16_t *ver_coefs; /** the pointer to int16_t[grid.num_ver_coefs * IA_CSS_DVS_NUM_COEF_TYPES]
+ s16 *ver_coefs; /** the pointer to int16_t[grid.num_ver_coefs * IA_CSS_DVS_NUM_COEF_TYPES]
containing the vertical coefficients */
};
struct ia_css_dvs_statistics {
struct ia_css_dvs_grid_info grid;/** grid info contains the dimensions of the dvs grid */
- int32_t *hor_proj; /** the pointer to int16_t[grid.height * IA_CSS_DVS_NUM_COEF_TYPES]
+ s32 *hor_proj; /** the pointer to int16_t[grid.height * IA_CSS_DVS_NUM_COEF_TYPES]
containing the horizontal projections */
- int32_t *ver_proj; /** the pointer to int16_t[grid.width * IA_CSS_DVS_NUM_COEF_TYPES]
+ s32 *ver_proj; /** the pointer to int16_t[grid.width * IA_CSS_DVS_NUM_COEF_TYPES]
containing the vertical projections */
};
};
static void
-fill_row(short *private, const short *public, unsigned width, unsigned padding)
+fill_row(short *private, const short *public, unsigned int width, unsigned int padding)
{
- memcpy (private, public, width*sizeof(short));
- memset (&private[width], 0, padding*sizeof(short));
+ memcpy(private, public, width * sizeof(short));
+ memset(&private[width], 0, padding * sizeof(short));
}
-void ia_css_sdis2_horicoef_vmem_encode (
+void ia_css_sdis2_horicoef_vmem_encode(
struct sh_css_isp_sdis_hori_coef_tbl *to,
const struct ia_css_dvs2_coefficients *from,
- unsigned size)
+ unsigned int size)
{
- unsigned aligned_width = from->grid.aligned_width * from->grid.bqs_per_grid_cell;
- unsigned width = from->grid.num_hor_coefs;
- int padding = aligned_width-width;
- unsigned stride = size/IA_CSS_DVS2_NUM_COEF_TYPES/sizeof(short);
- unsigned total_bytes = aligned_width*IA_CSS_DVS2_NUM_COEF_TYPES*sizeof(short);
- short *private = (short*)to;
-
+ unsigned int aligned_width = from->grid.aligned_width * from->grid.bqs_per_grid_cell;
+ unsigned int width = from->grid.num_hor_coefs;
+ int padding = aligned_width - width;
+ unsigned int stride = size / IA_CSS_DVS2_NUM_COEF_TYPES / sizeof(short);
+ unsigned int total_bytes = aligned_width * IA_CSS_DVS2_NUM_COEF_TYPES * sizeof(short);
+ short *private = (short *)to;
/* Copy the table, add padding */
assert(padding >= 0);
assert(total_bytes <= size);
- assert(size % (IA_CSS_DVS2_NUM_COEF_TYPES*ISP_VEC_NELEMS*sizeof(short)) == 0);
- fill_row(&private[0*stride], from->hor_coefs.odd_real, width, padding);
- fill_row(&private[1*stride], from->hor_coefs.odd_imag, width, padding);
- fill_row(&private[2*stride], from->hor_coefs.even_real, width, padding);
- fill_row(&private[3*stride], from->hor_coefs.even_imag, width, padding);
+ assert(size % (IA_CSS_DVS2_NUM_COEF_TYPES * ISP_VEC_NELEMS * sizeof(short)) == 0);
+ fill_row(&private[0 * stride], from->hor_coefs.odd_real, width, padding);
+ fill_row(&private[1 * stride], from->hor_coefs.odd_imag, width, padding);
+ fill_row(&private[2 * stride], from->hor_coefs.even_real, width, padding);
+ fill_row(&private[3 * stride], from->hor_coefs.even_imag, width, padding);
}
-void ia_css_sdis2_vertcoef_vmem_encode (
+void ia_css_sdis2_vertcoef_vmem_encode(
struct sh_css_isp_sdis_vert_coef_tbl *to,
const struct ia_css_dvs2_coefficients *from,
- unsigned size)
+ unsigned int size)
{
- unsigned aligned_height = from->grid.aligned_height * from->grid.bqs_per_grid_cell;
- unsigned height = from->grid.num_ver_coefs;
- int padding = aligned_height-height;
- unsigned stride = size/IA_CSS_DVS2_NUM_COEF_TYPES/sizeof(short);
- unsigned total_bytes = aligned_height*IA_CSS_DVS2_NUM_COEF_TYPES*sizeof(short);
- short *private = (short*)to;
+ unsigned int aligned_height = from->grid.aligned_height * from->grid.bqs_per_grid_cell;
+ unsigned int height = from->grid.num_ver_coefs;
+ int padding = aligned_height - height;
+ unsigned int stride = size / IA_CSS_DVS2_NUM_COEF_TYPES / sizeof(short);
+ unsigned int total_bytes = aligned_height * IA_CSS_DVS2_NUM_COEF_TYPES * sizeof(short);
+ short *private = (short *)to;
/* Copy the table, add padding */
assert(padding >= 0);
assert(total_bytes <= size);
- assert(size % (IA_CSS_DVS2_NUM_COEF_TYPES*ISP_VEC_NELEMS*sizeof(short)) == 0);
- fill_row(&private[0*stride], from->ver_coefs.odd_real, height, padding);
- fill_row(&private[1*stride], from->ver_coefs.odd_imag, height, padding);
- fill_row(&private[2*stride], from->ver_coefs.even_real, height, padding);
- fill_row(&private[3*stride], from->ver_coefs.even_imag, height, padding);
+ assert(size % (IA_CSS_DVS2_NUM_COEF_TYPES * ISP_VEC_NELEMS * sizeof(short)) == 0);
+ fill_row(&private[0 * stride], from->ver_coefs.odd_real, height, padding);
+ fill_row(&private[1 * stride], from->ver_coefs.odd_imag, height, padding);
+ fill_row(&private[2 * stride], from->ver_coefs.even_real, height, padding);
+ fill_row(&private[3 * stride], from->ver_coefs.even_imag, height, padding);
}
-void ia_css_sdis2_horiproj_encode (
+void ia_css_sdis2_horiproj_encode(
struct sh_css_isp_sdis_hori_proj_tbl *to,
const struct ia_css_dvs2_coefficients *from,
- unsigned size)
+ unsigned int size)
{
(void)to;
(void)from;
(void)size;
}
-void ia_css_sdis2_vertproj_encode (
+void ia_css_sdis2_vertproj_encode(
struct sh_css_isp_sdis_vert_proj_tbl *to,
const struct ia_css_dvs2_coefficients *from,
- unsigned size)
+ unsigned int size)
{
(void)to;
(void)from;
IA_CSS_ENTER("void");
- assert(stream != NULL);
- assert(hor_coefs_odd_real != NULL);
- assert(hor_coefs_odd_imag != NULL);
- assert(hor_coefs_even_real != NULL);
- assert(hor_coefs_even_imag != NULL);
- assert(ver_coefs_odd_real != NULL);
- assert(ver_coefs_odd_imag != NULL);
- assert(ver_coefs_even_real != NULL);
- assert(ver_coefs_even_imag != NULL);
+ assert(stream);
+ assert(hor_coefs_odd_real);
+ assert(hor_coefs_odd_imag);
+ assert(hor_coefs_even_real);
+ assert(hor_coefs_even_imag);
+ assert(ver_coefs_odd_real);
+ assert(ver_coefs_odd_imag);
+ assert(ver_coefs_even_real);
+ assert(ver_coefs_even_imag);
params = stream->isp_params_configs;
hor_num_isp = dvs_binary->dis.coef.pad.width;
ver_num_isp = dvs_binary->dis.coef.pad.height;
- memcpy (hor_coefs_odd_real, params->dvs2_coefs.hor_coefs.odd_real, hor_num_3a * sizeof(short));
- memcpy (hor_coefs_odd_imag, params->dvs2_coefs.hor_coefs.odd_imag, hor_num_3a * sizeof(short));
- memcpy (hor_coefs_even_real, params->dvs2_coefs.hor_coefs.even_real, hor_num_3a * sizeof(short));
- memcpy (hor_coefs_even_imag, params->dvs2_coefs.hor_coefs.even_imag, hor_num_3a * sizeof(short));
- memcpy (ver_coefs_odd_real, params->dvs2_coefs.ver_coefs.odd_real, ver_num_3a * sizeof(short));
- memcpy (ver_coefs_odd_imag, params->dvs2_coefs.ver_coefs.odd_imag, ver_num_3a * sizeof(short));
- memcpy (ver_coefs_even_real, params->dvs2_coefs.ver_coefs.even_real, ver_num_3a * sizeof(short));
- memcpy (ver_coefs_even_imag, params->dvs2_coefs.ver_coefs.even_imag, ver_num_3a * sizeof(short));
+ memcpy(hor_coefs_odd_real, params->dvs2_coefs.hor_coefs.odd_real, hor_num_3a * sizeof(short));
+ memcpy(hor_coefs_odd_imag, params->dvs2_coefs.hor_coefs.odd_imag, hor_num_3a * sizeof(short));
+ memcpy(hor_coefs_even_real, params->dvs2_coefs.hor_coefs.even_real, hor_num_3a * sizeof(short));
+ memcpy(hor_coefs_even_imag, params->dvs2_coefs.hor_coefs.even_imag, hor_num_3a * sizeof(short));
+ memcpy(ver_coefs_odd_real, params->dvs2_coefs.ver_coefs.odd_real, ver_num_3a * sizeof(short));
+ memcpy(ver_coefs_odd_imag, params->dvs2_coefs.ver_coefs.odd_imag, ver_num_3a * sizeof(short));
+ memcpy(ver_coefs_even_real, params->dvs2_coefs.ver_coefs.even_real, ver_num_3a * sizeof(short));
+ memcpy(ver_coefs_even_imag, params->dvs2_coefs.ver_coefs.even_imag, ver_num_3a * sizeof(short));
IA_CSS_LEAVE("void");
}
IA_CSS_ENTER("host_stats=%p, isp_stats=%p", host_stats, isp_stats);
- assert(host_stats != NULL);
- assert(isp_stats != NULL);
+ assert(host_stats);
+ assert(isp_stats);
map = ia_css_isp_dvs_statistics_map_allocate(isp_stats, NULL);
if (map) {
{
unsigned int size_bytes, table_width, table_size, height;
unsigned int src_offset = 0, dst_offset = 0;
- int32_t *htemp_ptr, *vtemp_ptr;
-
- assert(host_stats != NULL);
- assert(host_stats->hor_prod.odd_real != NULL);
- assert(host_stats->hor_prod.odd_imag != NULL);
- assert(host_stats->hor_prod.even_real != NULL);
- assert(host_stats->hor_prod.even_imag != NULL);
- assert(host_stats->ver_prod.odd_real != NULL);
- assert(host_stats->ver_prod.odd_imag != NULL);
- assert(host_stats->ver_prod.even_real != NULL);
- assert(host_stats->ver_prod.even_imag != NULL);
- assert(isp_stats != NULL);
- assert(isp_stats->hor_proj != NULL);
- assert(isp_stats->ver_proj != NULL);
-
- IA_CSS_ENTER("hor_coefs.odd_real=%p, hor_coefs.odd_imag=%p, "
- "hor_coefs.even_real=%p, hor_coefs.even_imag=%p, "
- "ver_coefs.odd_real=%p, ver_coefs.odd_imag=%p, "
- "ver_coefs.even_real=%p, ver_coefs.even_imag=%p, "
- "haddr=%p, vaddr=%p",
+ s32 *htemp_ptr, *vtemp_ptr;
+
+ assert(host_stats);
+ assert(host_stats->hor_prod.odd_real);
+ assert(host_stats->hor_prod.odd_imag);
+ assert(host_stats->hor_prod.even_real);
+ assert(host_stats->hor_prod.even_imag);
+ assert(host_stats->ver_prod.odd_real);
+ assert(host_stats->ver_prod.odd_imag);
+ assert(host_stats->ver_prod.even_real);
+ assert(host_stats->ver_prod.even_imag);
+ assert(isp_stats);
+ assert(isp_stats->hor_proj);
+ assert(isp_stats->ver_proj);
+
+ IA_CSS_ENTER("hor_coefs.odd_real=%p, hor_coefs.odd_imag=%p, hor_coefs.even_real=%p, hor_coefs.even_imag=%p, ver_coefs.odd_real=%p, ver_coefs.odd_imag=%p, ver_coefs.even_real=%p, ver_coefs.even_imag=%p, haddr=%p, vaddr=%p",
host_stats->hor_prod.odd_real, host_stats->hor_prod.odd_imag,
host_stats->hor_prod.even_real, host_stats->hor_prod.even_imag,
host_stats->ver_prod.odd_real, host_stats->ver_prod.odd_imag,
for (height = 0; height < host_stats->grid.aligned_height; height++) {
/* hor stats */
memcpy(host_stats->hor_prod.odd_real + dst_offset,
- &htemp_ptr[0*table_size+src_offset], size_bytes);
+ &htemp_ptr[0 * table_size + src_offset], size_bytes);
memcpy(host_stats->hor_prod.odd_imag + dst_offset,
- &htemp_ptr[1*table_size+src_offset], size_bytes);
+ &htemp_ptr[1 * table_size + src_offset], size_bytes);
memcpy(host_stats->hor_prod.even_real + dst_offset,
- &htemp_ptr[2*table_size+src_offset], size_bytes);
+ &htemp_ptr[2 * table_size + src_offset], size_bytes);
memcpy(host_stats->hor_prod.even_imag + dst_offset,
- &htemp_ptr[3*table_size+src_offset], size_bytes);
+ &htemp_ptr[3 * table_size + src_offset], size_bytes);
/* ver stats */
memcpy(host_stats->ver_prod.odd_real + dst_offset,
- &vtemp_ptr[0*table_size+src_offset], size_bytes);
+ &vtemp_ptr[0 * table_size + src_offset], size_bytes);
memcpy(host_stats->ver_prod.odd_imag + dst_offset,
- &vtemp_ptr[1*table_size+src_offset], size_bytes);
+ &vtemp_ptr[1 * table_size + src_offset], size_bytes);
memcpy(host_stats->ver_prod.even_real + dst_offset,
- &vtemp_ptr[2*table_size+src_offset], size_bytes);
+ &vtemp_ptr[2 * table_size + src_offset], size_bytes);
memcpy(host_stats->ver_prod.even_imag + dst_offset,
- &vtemp_ptr[3*table_size+src_offset], size_bytes);
+ &vtemp_ptr[3 * table_size + src_offset], size_bytes);
src_offset += table_width; /* aligned table width */
dst_offset += host_stats->grid.aligned_width;
struct ia_css_isp_dvs_statistics *me;
int size;
- assert(grid != NULL);
+ assert(grid);
IA_CSS_ENTER("grid=%p", grid);
if (!grid->enable)
return NULL;
- me = sh_css_calloc(1,sizeof(*me));
+ me = sh_css_calloc(1, sizeof(*me));
if (!me)
goto err;
size = CEIL_MUL(sizeof(int) * grid->aligned_width, HIVE_ISP_DDR_WORD_BYTES)
* grid->aligned_height * IA_CSS_DVS2_NUM_COEF_TYPES;
- me->size = 2*size;
+ me->size = 2 * size;
me->data_ptr = mmgr_malloc(me->size);
if (me->data_ptr == mmgr_NULL)
goto err;
void
ia_css_isp_dvs2_statistics_free(struct ia_css_isp_dvs_statistics *me)
{
- if (me != NULL) {
+ if (me) {
hmm_free(me->data_ptr);
sh_css_free(me);
}
}
void ia_css_sdis2_horicoef_debug_dtrace(
- const struct ia_css_dvs2_coefficients *config, unsigned level)
+ const struct ia_css_dvs2_coefficients *config, unsigned int level)
{
(void)config;
(void)level;
}
void ia_css_sdis2_vertcoef_debug_dtrace(
- const struct ia_css_dvs2_coefficients *config, unsigned level)
+ const struct ia_css_dvs2_coefficients *config, unsigned int level)
{
(void)config;
(void)level;
}
void ia_css_sdis2_horiproj_debug_dtrace(
- const struct ia_css_dvs2_coefficients *config, unsigned level)
+ const struct ia_css_dvs2_coefficients *config, unsigned int level)
{
(void)config;
(void)level;
}
void ia_css_sdis2_vertproj_debug_dtrace(
- const struct ia_css_dvs2_coefficients *config, unsigned level)
+ const struct ia_css_dvs2_coefficients *config, unsigned int level)
{
(void)config;
(void)level;
struct sh_css_isp_sdis_hori_proj_tbl;
struct sh_css_isp_sdis_vert_proj_tbl;
-void ia_css_sdis2_horicoef_vmem_encode (
+void ia_css_sdis2_horicoef_vmem_encode(
struct sh_css_isp_sdis_hori_coef_tbl *to,
const struct ia_css_dvs2_coefficients *from,
- unsigned size);
+ unsigned int size);
-void ia_css_sdis2_vertcoef_vmem_encode (
+void ia_css_sdis2_vertcoef_vmem_encode(
struct sh_css_isp_sdis_vert_coef_tbl *to,
const struct ia_css_dvs2_coefficients *from,
- unsigned size);
+ unsigned int size);
-void ia_css_sdis2_horiproj_encode (
+void ia_css_sdis2_horiproj_encode(
struct sh_css_isp_sdis_hori_proj_tbl *to,
const struct ia_css_dvs2_coefficients *from,
- unsigned size);
+ unsigned int size);
-void ia_css_sdis2_vertproj_encode (
+void ia_css_sdis2_vertproj_encode(
struct sh_css_isp_sdis_vert_proj_tbl *to,
const struct ia_css_dvs2_coefficients *from,
- unsigned size);
+ unsigned int size);
void ia_css_get_isp_dvs2_coefficients(
struct ia_css_stream *stream,
struct ia_css_isp_dvs_statistics *me);
void ia_css_sdis2_horicoef_debug_dtrace(
- const struct ia_css_dvs2_coefficients *config, unsigned level);
+ const struct ia_css_dvs2_coefficients *config, unsigned int level);
void ia_css_sdis2_vertcoef_debug_dtrace(
- const struct ia_css_dvs2_coefficients *config, unsigned level);
+ const struct ia_css_dvs2_coefficients *config, unsigned int level);
void ia_css_sdis2_horiproj_debug_dtrace(
- const struct ia_css_dvs2_coefficients *config, unsigned level);
+ const struct ia_css_dvs2_coefficients *config, unsigned int level);
void ia_css_sdis2_vertproj_debug_dtrace(
- const struct ia_css_dvs2_coefficients *config, unsigned level);
+ const struct ia_css_dvs2_coefficients *config, unsigned int level);
#endif /* __IA_CSS_SDIS2_HOST_H */
* arrays that contain the coeffients for each type.
*/
struct ia_css_dvs2_coef_types {
- int16_t *odd_real; /** real part of the odd coefficients*/
- int16_t *odd_imag; /** imaginary part of the odd coefficients*/
- int16_t *even_real;/** real part of the even coefficients*/
- int16_t *even_imag;/** imaginary part of the even coefficients*/
+ s16 *odd_real; /** real part of the odd coefficients*/
+ s16 *odd_imag; /** imaginary part of the odd coefficients*/
+ s16 *even_real;/** real part of the even coefficients*/
+ s16 *even_imag;/** imaginary part of the even coefficients*/
};
/* DVS 2.0 Coefficients. This structure describes the coefficients that are needed for the dvs statistics.
- * e.g. hor_coefs.odd_real is the pointer to int16_t[grid.num_hor_coefs] containing the horizontal odd real
+ * e.g. hor_coefs.odd_real is the pointer to int16_t[grid.num_hor_coefs] containing the horizontal odd real
* coefficients.
*/
struct ia_css_dvs2_coefficients {
* arrays that contain the statistics for each type.
*/
struct ia_css_dvs2_stat_types {
- int32_t *odd_real; /** real part of the odd statistics*/
- int32_t *odd_imag; /** imaginary part of the odd statistics*/
- int32_t *even_real;/** real part of the even statistics*/
- int32_t *even_imag;/** imaginary part of the even statistics*/
+ s32 *odd_real; /** real part of the odd statistics*/
+ s32 *odd_imag; /** imaginary part of the odd statistics*/
+ s32 *even_real;/** real part of the even statistics*/
+ s32 *even_imag;/** imaginary part of the even statistics*/
};
/* DVS 2.0 Statistics. This structure describes the statistics that are generated using the provided coefficients.
- * e.g. hor_prod.odd_real is the pointer to int16_t[grid.aligned_height][grid.aligned_width] containing
+ * e.g. hor_prod.odd_real is the pointer to int16_t[grid.aligned_height][grid.aligned_width] containing
* the horizontal odd real statistics. Valid statistics data area is int16_t[0..grid.height-1][0..grid.width-1]
*/
struct ia_css_dvs2_statistics {
#include "ia_css_debug.h"
#include "ia_css_tdf.host.h"
-static const int16_t g_pyramid[8][8] = {
+static const s16 g_pyramid[8][8] = {
{128, 384, 640, 896, 896, 640, 384, 128},
{384, 1152, 1920, 2688, 2688, 1920, 1152, 384},
{640, 1920, 3200, 4480, 4480, 3200, 1920, 640},
const struct ia_css_tdf_config *from,
size_t size)
{
- unsigned i;
+ unsigned int i;
(void)size;
for (i = 0; i < ISP_VEC_NELEMS; i++) {
- to->pyramid[0][i] = g_pyramid[i/8][i%8];
+ to->pyramid[0][i] = g_pyramid[i / 8][i % 8];
to->threshold_flat[0][i] = from->thres_flat_table[i];
to->threshold_detail[0][i] = from->thres_detail_table[i];
}
-
}
void
void
ia_css_tdf_debug_dtrace(
const struct ia_css_tdf_config *config,
- unsigned level)
+ unsigned int level)
{
(void)config;
(void)level;
}
-
void
ia_css_tdf_debug_dtrace(
- const struct ia_css_tdf_config *config, unsigned level)
+ const struct ia_css_tdf_config *config, unsigned int level)
;
#endif /* __IA_CSS_TDF_HOST_H */
};
struct ia_css_isp_tdf_dmem_params {
- int32_t Epsilon_0;
- int32_t Epsilon_1;
- int32_t EpsScaleText;
- int32_t EpsScaleEdge;
- int32_t Sepa_flat;
- int32_t Sepa_Edge;
- int32_t Blend_Flat;
- int32_t Blend_Text;
- int32_t Blend_Edge;
- int32_t Shading_Gain;
- int32_t Shading_baseGain;
- int32_t LocalY_Gain;
- int32_t LocalY_baseGain;
+ s32 Epsilon_0;
+ s32 Epsilon_1;
+ s32 EpsScaleText;
+ s32 EpsScaleEdge;
+ s32 Sepa_flat;
+ s32 Sepa_Edge;
+ s32 Blend_Flat;
+ s32 Blend_Text;
+ s32 Blend_Edge;
+ s32 Shading_Gain;
+ s32 Shading_baseGain;
+ s32 LocalY_Gain;
+ s32 LocalY_baseGain;
};
#endif /* __IA_CSS_TDF_PARAM_H */
* ISP2.6.1: TDF is used.
*/
struct ia_css_tdf_config {
- int32_t thres_flat_table[64]; /** Final optimized strength table of NR for flat region. */
- int32_t thres_detail_table[64]; /** Final optimized strength table of NR for detail region. */
- int32_t epsilon_0; /** Coefficient to control variance for dark area (for flat region). */
- int32_t epsilon_1; /** Coefficient to control variance for bright area (for flat region). */
- int32_t eps_scale_text; /** Epsilon scaling coefficient for texture region. */
- int32_t eps_scale_edge; /** Epsilon scaling coefficient for edge region. */
- int32_t sepa_flat; /** Threshold to judge flat (edge < m_Flat_thre). */
- int32_t sepa_edge; /** Threshold to judge edge (edge > m_Edge_thre). */
- int32_t blend_flat; /** Blending ratio at flat region. */
- int32_t blend_text; /** Blending ratio at texture region. */
- int32_t blend_edge; /** Blending ratio at edge region. */
- int32_t shading_gain; /** Gain of Shading control. */
- int32_t shading_base_gain; /** Base Gain of Shading control. */
- int32_t local_y_gain; /** Gain of local luminance control. */
- int32_t local_y_base_gain; /** Base gain of local luminance control. */
- int32_t rad_x_origin; /** Initial x coord. for radius computation. */
- int32_t rad_y_origin; /** Initial y coord. for radius computation. */
+ s32 thres_flat_table[64]; /** Final optimized strength table of NR for flat region. */
+ s32 thres_detail_table[64]; /** Final optimized strength table of NR for detail region. */
+ s32 epsilon_0; /** Coefficient to control variance for dark area (for flat region). */
+ s32 epsilon_1; /** Coefficient to control variance for bright area (for flat region). */
+ s32 eps_scale_text; /** Epsilon scaling coefficient for texture region. */
+ s32 eps_scale_edge; /** Epsilon scaling coefficient for edge region. */
+ s32 sepa_flat; /** Threshold to judge flat (edge < m_Flat_thre). */
+ s32 sepa_edge; /** Threshold to judge edge (edge > m_Edge_thre). */
+ s32 blend_flat; /** Blending ratio at flat region. */
+ s32 blend_text; /** Blending ratio at texture region. */
+ s32 blend_edge; /** Blending ratio at edge region. */
+ s32 shading_gain; /** Gain of Shading control. */
+ s32 shading_base_gain; /** Base Gain of Shading control. */
+ s32 local_y_gain; /** Gain of local luminance control. */
+ s32 local_y_base_gain; /** Base gain of local luminance control. */
+ s32 rad_x_origin; /** Initial x coord. for radius computation. */
+ s32 rad_y_origin; /** Initial y coord. for radius computation. */
};
#endif /* __IA_CSS_TDF_TYPES_H */
-
ia_css_tnr_encode(
struct sh_css_isp_tnr_params *to,
const struct ia_css_tnr_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->coef =
void
ia_css_tnr_dump(
const struct sh_css_isp_tnr_params *tnr,
- unsigned level)
+ unsigned int level)
{
if (!tnr) return;
ia_css_debug_dtrace(level, "Temporal Noise Reduction:\n");
void
ia_css_tnr_debug_dtrace(
const struct ia_css_tnr_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
- "config.gain=%d, "
- "config.threshold_y=%d, config.threshold_uv=%d\n",
+ "config.gain=%d, config.threshold_y=%d, config.threshold_uv=%d\n",
config->gain,
config->threshold_y, config->threshold_uv);
}
ia_css_tnr_config(
struct sh_css_isp_tnr_isp_config *to,
const struct ia_css_tnr_configuration *from,
- unsigned size)
+ unsigned int size)
{
- unsigned elems_a = ISP_VEC_NELEMS;
- unsigned i;
+ unsigned int elems_a = ISP_VEC_NELEMS;
+ unsigned int i;
(void)size;
ia_css_dma_configure_from_info(&to->port_b, &from->tnr_frames[0]->info);
}
/* Assume divisiblity here, may need to generalize to fixed point. */
- assert (elems_a % to->port_b.elems == 0);
+ assert(elems_a % to->port_b.elems == 0);
}
void
const struct ia_css_frame **frames)
{
struct ia_css_tnr_configuration config;
- unsigned i;
+ unsigned int i;
#ifndef ISP2401
for (i = 0; i < NUM_VIDEO_TNR_FRAMES; i++)
ia_css_tnr_encode(
struct sh_css_isp_tnr_params *to,
const struct ia_css_tnr_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_tnr_dump(
const struct sh_css_isp_tnr_params *tnr,
- unsigned level);
+ unsigned int level);
void
ia_css_tnr_debug_dtrace(
const struct ia_css_tnr_config *config,
- unsigned level);
+ unsigned int level);
void
ia_css_tnr_config(
struct sh_css_isp_tnr_isp_config *to,
const struct ia_css_tnr_configuration *from,
- unsigned size);
+ unsigned int size);
void
ia_css_tnr_configure(
/* TNR (Temporal Noise Reduction) */
struct sh_css_isp_tnr_params {
- int32_t coef;
- int32_t threshold_Y;
- int32_t threshold_C;
+ s32 coef;
+ s32 threshold_Y;
+ s32 threshold_C;
};
struct ia_css_tnr_configuration {
};
struct sh_css_isp_tnr_isp_config {
- uint32_t width_a_over_b;
- uint32_t frame_height;
+ u32 width_a_over_b;
+ u32 frame_height;
struct dma_port_config port_b;
#ifndef ISP2401
hrt_vaddress tnr_frame_addr[NUM_VIDEO_TNR_FRAMES];
/* TNR (temporal noise reduction) */
struct sh_css_isp_tnr_dmem_state {
- uint32_t tnr_in_buf_idx;
- uint32_t tnr_out_buf_idx;
+ u32 tnr_in_buf_idx;
+ u32 tnr_out_buf_idx;
};
#endif /* __IA_CSS_TNR_STATE_H */
* ISP2: TNR1 is used.
*/
-
struct ia_css_tnr_config {
ia_css_u0_16 gain; /** Interpolation ratio of current frame
- and previous frame.
+ and previous frame.
gain=0.0 -> previous frame is outputted.
gain=1.0 -> current frame is outputted.
u0.16, [0,65535],
u0.16, [0,65535], default/ineffective 0 */
};
-
#endif /* __IA_CSS_TNR_TYPES_H */
-
ia_css_vf_config(
struct sh_css_isp_vf_isp_config *to,
const struct ia_css_vf_configuration *from,
- unsigned size)
+ unsigned int size)
{
- unsigned elems_a = ISP_VEC_NELEMS;
+ unsigned int elems_a = ISP_VEC_NELEMS;
(void)size;
to->vf_downscale_bits = from->vf_downscale_bits;
to->dma.width_a_over_b = elems_a / to->dma.port_b.elems;
/* Assume divisiblity here, may need to generalize to fixed point. */
- assert (elems_a % to->dma.port_b.elems == 0);
+ assert(elems_a % to->dma.port_b.elems == 0);
}
}
unsigned int ds_log2 = 0;
unsigned int out_width;
- if ((out_info == NULL) | (vf_info == NULL))
- return IA_CSS_ERR_INVALID_ARGUMENTS;
+ if ((!out_info) | (!vf_info))
+ return IA_CSS_ERR_INVALID_ARGUMENTS;
out_width = out_info->res.width;
if (out_width == 0)
- return IA_CSS_ERR_INVALID_ARGUMENTS;
+ return IA_CSS_ERR_INVALID_ARGUMENTS;
/* downscale until width smaller than the viewfinder width. We don't
* test for the height since the vmem buffers only put restrictions on
ds_log2--;
/* TODO: use actual max input resolution of vf_pp binary */
if ((out_info->res.width >> ds_log2) >= 2 * ia_css_binary_max_vf_width())
- return IA_CSS_ERR_INVALID_ARGUMENTS;
+ return IA_CSS_ERR_INVALID_ARGUMENTS;
*downscale_log2 = ds_log2;
return IA_CSS_SUCCESS;
}
struct ia_css_vf_configuration *config)
{
enum ia_css_err err;
- unsigned vf_log_ds = 0;
+ unsigned int vf_log_ds = 0;
/* First compute value */
if (vf_info) {
err = sh_css_vf_downscale_log2(out_info, vf_info, &vf_log_ds);
- if (err != IA_CSS_SUCCESS)
- return err;
+ if (err != IA_CSS_SUCCESS)
+ return err;
}
vf_log_ds = min(vf_log_ds, info->vf_dec.max_log_downscale);
*downscale_log2 = vf_log_ds;
if (vf_info)
vf_info->raw_bit_depth = info->dma.vfdec_bits_per_pixel;
- ia_css_configure_vf (binary, &config);
+ ia_css_configure_vf(binary, &config);
return IA_CSS_SUCCESS;
}
-
ia_css_vf_config(
struct sh_css_isp_vf_isp_config *to,
const struct ia_css_vf_configuration *from,
- unsigned size);
+ unsigned int size);
enum ia_css_err
ia_css_vf_configure(
/* Viewfinder decimation */
struct sh_css_isp_vf_isp_config {
- uint32_t vf_downscale_bits; /** Log VF downscale value */
- uint32_t enable;
+ u32 vf_downscale_bits; /** Log VF downscale value */
+ u32 enable;
struct ia_css_frame_sp_info info;
struct {
- uint32_t width_a_over_b;
+ u32 width_a_over_b;
struct dma_port_config port_b;
} dma;
};
#include <type_support.h>
struct ia_css_vf_configuration {
- uint32_t vf_downscale_bits; /** Log VF downscale value */
+ u32 vf_downscale_bits; /** Log VF downscale value */
const struct ia_css_frame_info *info;
};
#endif /* __IA_CSS_VF_TYPES_H */
-
ia_css_wb_encode(
struct sh_css_isp_wb_params *to,
const struct ia_css_wb_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->gain_shift =
void
ia_css_wb_dump(
const struct sh_css_isp_wb_params *wb,
- unsigned level)
+ unsigned int level)
{
if (!wb) return;
ia_css_debug_dtrace(level, "White Balance:\n");
void
ia_css_wb_debug_dtrace(
const struct ia_css_wb_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
- "config.integer_bits=%d, "
- "config.gr=%d, config.r=%d, "
- "config.b=%d, config.gb=%d\n",
+ "config.integer_bits=%d, config.gr=%d, config.r=%d, config.b=%d, config.gb=%d\n",
config->integer_bits,
config->gr, config->r,
config->b, config->gb);
}
#endif
-
ia_css_wb_encode(
struct sh_css_isp_wb_params *to,
const struct ia_css_wb_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_wb_dump(
const struct sh_css_isp_wb_params *wb,
- unsigned level);
+ unsigned int level);
void
ia_css_wb_debug_dtrace(
const struct ia_css_wb_config *wb,
- unsigned level);
+ unsigned int level);
#endif /* __IA_CSS_WB_HOST_H */
/* WB (White Balance) */
struct sh_css_isp_wb_params {
- int32_t gain_shift;
- int32_t gain_gr;
- int32_t gain_r;
- int32_t gain_b;
- int32_t gain_gb;
+ s32 gain_shift;
+ s32 gain_gr;
+ s32 gain_r;
+ s32 gain_b;
+ s32 gain_gb;
};
#endif /* __IA_CSS_WB_PARAM_H */
* CSS-API header file for White Balance parameters.
*/
-
/* White Balance configuration (Gain Adjust).
*
* ISP block: WB1
* ISP2: WB1 is used.
*/
struct ia_css_wb_config {
- uint32_t integer_bits; /** Common exponent of gains.
+ u32 integer_bits; /** Common exponent of gains.
u8.0, [0,3],
default 1, ineffective 1 */
- uint32_t gr; /** Significand of Gr gain.
+ u32 gr; /** Significand of Gr gain.
u[integer_bits].[16-integer_bits], [0,65535],
default/ineffective 32768(u1.15, 1.0) */
- uint32_t r; /** Significand of R gain.
+ u32 r; /** Significand of R gain.
u[integer_bits].[16-integer_bits], [0,65535],
default/ineffective 32768(u1.15, 1.0) */
- uint32_t b; /** Significand of B gain.
+ u32 b; /** Significand of B gain.
u[integer_bits].[16-integer_bits], [0,65535],
default/ineffective 32768(u1.15, 1.0) */
- uint32_t gb; /** Significand of Gb gain.
+ u32 gb; /** Significand of Gb gain.
u[integer_bits].[16-integer_bits], [0,65535],
default/ineffective 32768(u1.15, 1.0) */
};
* more details.
*/
-
#include "ia_css_types.h"
#include "sh_css_defs.h"
#include "ia_css_debug.h"
ia_css_xnr_table_vamem_encode(
struct sh_css_isp_xnr_vamem_params *to,
const struct ia_css_xnr_table *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
- memcpy (&to->xnr, &from->data, sizeof(to->xnr));
+ memcpy(&to->xnr, &from->data, sizeof(to->xnr));
}
void
ia_css_xnr_encode(
struct sh_css_isp_xnr_params *to,
const struct ia_css_xnr_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
void
ia_css_xnr_table_debug_dtrace(
const struct ia_css_xnr_table *config,
- unsigned level)
+ unsigned int level)
{
(void)config;
(void)level;
void
ia_css_xnr_debug_dtrace(
const struct ia_css_xnr_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
"config.threshold=%d\n", config->threshold);
ia_css_xnr_table_vamem_encode(
struct sh_css_isp_xnr_vamem_params *to,
const struct ia_css_xnr_table *from,
- unsigned size);
+ unsigned int size);
void
ia_css_xnr_encode(
struct sh_css_isp_xnr_params *to,
const struct ia_css_xnr_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_xnr_table_debug_dtrace(
const struct ia_css_xnr_table *s3a,
- unsigned level);
+ unsigned int level);
void
ia_css_xnr_debug_dtrace(
const struct ia_css_xnr_config *config,
- unsigned level);
+ unsigned int level);
#endif /* __IA_CSS_XNR_HOST_H */
#error "Unknown vamem type"
#endif
-
#else
/* For pipe generation, the size is not relevant */
#define SH_CSS_ISP_XNR_TABLE_SIZE 0
/* This should be vamem_data_t, but that breaks the pipe generator */
struct sh_css_isp_xnr_vamem_params {
- uint16_t xnr[SH_CSS_ISP_XNR_TABLE_SIZE];
+ u16 xnr[SH_CSS_ISP_XNR_TABLE_SIZE];
};
struct sh_css_isp_xnr_params {
* type:u0.16 but actual valid range is:[0,255]
* valid range is dependent on SH_CSS_ISP_YUV_BITS (currently 8bits)
* default: 25 */
- uint16_t threshold;
+ u16 threshold;
};
#endif /* __IA_CSS_XNR_PARAM_H */
static const uint16_t
default_xnr_table_data[IA_CSS_VAMEM_2_XNR_TABLE_SIZE] = {
/* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 */
- 8191>>1, 4096>>1, 2730>>1, 2048>>1, 1638>>1, 1365>>1, 1170>>1, 1024>>1, 910>>1, 819>>1, 744>>1, 682>>1, 630>>1, 585>>1,
- 546>>1, 512>>1,
+ 8191 >> 1, 4096 >> 1, 2730 >> 1, 2048 >> 1, 1638 >> 1, 1365 >> 1, 1170 >> 1, 1024 >> 1, 910 >> 1, 819 >> 1, 744 >> 1, 682 >> 1, 630 >> 1, 585 >> 1,
+ 546 >> 1, 512 >> 1,
/* 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 */
- 481>>1, 455>>1, 431>>1, 409>>1, 390>>1, 372>>1, 356>>1, 341>>1, 327>>1, 315>>1, 303>>1, 292>>1, 282>>1, 273>>1, 264>>1,
- 256>>1,
+ 481 >> 1, 455 >> 1, 431 >> 1, 409 >> 1, 390 >> 1, 372 >> 1, 356 >> 1, 341 >> 1, 327 >> 1, 315 >> 1, 303 >> 1, 292 >> 1, 282 >> 1, 273 >> 1, 264 >> 1,
+ 256 >> 1,
/* 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 */
- 248>>1, 240>>1, 234>>1, 227>>1, 221>>1, 215>>1, 210>>1, 204>>1, 199>>1, 195>>1, 190>>1, 186>>1, 182>>1, 178>>1, 174>>1,
- 170>>1,
+ 248 >> 1, 240 >> 1, 234 >> 1, 227 >> 1, 221 >> 1, 215 >> 1, 210 >> 1, 204 >> 1, 199 >> 1, 195 >> 1, 190 >> 1, 186 >> 1, 182 >> 1, 178 >> 1, 174 >> 1,
+ 170 >> 1,
/* 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 */
- 167>>1, 163>>1, 160>>1, 157>>1, 154>>1, 151>>1, 148>>1, 146>>1, 143>>1, 141>>1, 138>>1, 136>>1, 134>>1, 132>>1, 130>>1, 128>>1
+ 167 >> 1, 163 >> 1, 160 >> 1, 157 >> 1, 154 >> 1, 151 >> 1, 148 >> 1, 146 >> 1, 143 >> 1, 141 >> 1, 138 >> 1, 136 >> 1, 134 >> 1, 132 >> 1, 130 >> 1, 128 >> 1
};
#elif defined(HAS_VAMEM_VERSION_1)
static const uint16_t
default_xnr_table_data[IA_CSS_VAMEM_1_XNR_TABLE_SIZE] = {
/* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 */
- 8191>>1, 4096>>1, 2730>>1, 2048>>1, 1638>>1, 1365>>1, 1170>>1, 1024>>1, 910>>1, 819>>1, 744>>1, 682>>1, 630>>1, 585>>1,
- 546>>1, 512>>1,
+ 8191 >> 1, 4096 >> 1, 2730 >> 1, 2048 >> 1, 1638 >> 1, 1365 >> 1, 1170 >> 1, 1024 >> 1, 910 >> 1, 819 >> 1, 744 >> 1, 682 >> 1, 630 >> 1, 585 >> 1,
+ 546 >> 1, 512 >> 1,
/* 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 */
- 481>>1, 455>>1, 431>>1, 409>>1, 390>>1, 372>>1, 356>>1, 341>>1, 327>>1, 315>>1, 303>>1, 292>>1, 282>>1, 273>>1, 264>>1,
- 256>>1,
+ 481 >> 1, 455 >> 1, 431 >> 1, 409 >> 1, 390 >> 1, 372 >> 1, 356 >> 1, 341 >> 1, 327 >> 1, 315 >> 1, 303 >> 1, 292 >> 1, 282 >> 1, 273 >> 1, 264 >> 1,
+ 256 >> 1,
/* 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 */
- 248>>1, 240>>1, 234>>1, 227>>1, 221>>1, 215>>1, 210>>1, 204>>1, 199>>1, 195>>1, 190>>1, 186>>1, 182>>1, 178>>1, 174>>1,
- 170>>1,
+ 248 >> 1, 240 >> 1, 234 >> 1, 227 >> 1, 221 >> 1, 215 >> 1, 210 >> 1, 204 >> 1, 199 >> 1, 195 >> 1, 190 >> 1, 186 >> 1, 182 >> 1, 178 >> 1, 174 >> 1,
+ 170 >> 1,
/* 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 */
- 167>>1, 163>>1, 160>>1, 157>>1, 154>>1, 151>>1, 148>>1, 146>>1, 143>>1, 141>>1, 138>>1, 136>>1, 134>>1, 132>>1, 130>>1, 128>>1
+ 167 >> 1, 163 >> 1, 160 >> 1, 157 >> 1, 154 >> 1, 151 >> 1, 148 >> 1, 146 >> 1, 143 >> 1, 141 >> 1, 138 >> 1, 136 >> 1, 134 >> 1, 132 >> 1, 130 >> 1, 128 >> 1
};
#else
*
* This table contains coefficients used for division in XNR.
*
- * u0.12, [0,4095],
+ * u0.12, [0,4095],
* {4095, 2048, 1365, .........., 65, 64}
* ({1/1, 1/2, 1/3, ............., 1/63, 1/64})
*
/* Number of elements in the xnr table. */
#define IA_CSS_VAMEM_1_XNR_TABLE_SIZE_LOG2 6
/* Number of elements in the xnr table. */
-#define IA_CSS_VAMEM_1_XNR_TABLE_SIZE (1U<<IA_CSS_VAMEM_1_XNR_TABLE_SIZE_LOG2)
+#define IA_CSS_VAMEM_1_XNR_TABLE_SIZE BIT(IA_CSS_VAMEM_1_XNR_TABLE_SIZE_LOG2)
/* Number of elements in the xnr table. */
#define IA_CSS_VAMEM_2_XNR_TABLE_SIZE_LOG2 6
/* Number of elements in the xnr table. */
-#define IA_CSS_VAMEM_2_XNR_TABLE_SIZE (1U<<IA_CSS_VAMEM_2_XNR_TABLE_SIZE_LOG2)
+#define IA_CSS_VAMEM_2_XNR_TABLE_SIZE BIT(IA_CSS_VAMEM_2_XNR_TABLE_SIZE_LOG2)
/** IA_CSS_VAMEM_TYPE_1(ISP2300) or
IA_CSS_VAMEM_TYPE_2(ISP2400) */
union ia_css_xnr_data {
- uint16_t vamem_1[IA_CSS_VAMEM_1_XNR_TABLE_SIZE];
+ u16 vamem_1[IA_CSS_VAMEM_1_XNR_TABLE_SIZE];
/** Coefficients table on vamem type1. u0.12, [0,4095] */
- uint16_t vamem_2[IA_CSS_VAMEM_2_XNR_TABLE_SIZE];
+ u16 vamem_2[IA_CSS_VAMEM_2_XNR_TABLE_SIZE];
/** Coefficients table on vamem type2. u0.12, [0,4095] */
};
/* XNR threshold.
* type:u0.16 valid range:[0,65535]
* default: 6400 */
- uint16_t threshold;
+ u16 threshold;
};
#endif /* __IA_CSS_XNR_TYPES_H */
-
*/
#define XNR3_LOOK_UP_TABLE_POINTS 16
-static const int16_t x[XNR3_LOOK_UP_TABLE_POINTS] = {
+static const s16 x[XNR3_LOOK_UP_TABLE_POINTS] = {
1024, 1164, 1320, 1492, 1680, 1884, 2108, 2352,
2616, 2900, 3208, 3540, 3896, 4276, 4684, 5120};
-static const int16_t a[XNR3_LOOK_UP_TABLE_POINTS] = {
+static const s16 a[XNR3_LOOK_UP_TABLE_POINTS] = {
-7213, -5580, -4371, -3421, -2722, -2159, -6950, -5585,
-4529, -3697, -3010, -2485, -2070, -1727, -1428, 0};
-static const int16_t b[XNR3_LOOK_UP_TABLE_POINTS] = {
+static const s16 b[XNR3_LOOK_UP_TABLE_POINTS] = {
4096, 3603, 3178, 2811, 2497, 2226, 1990, 1783,
1603, 1446, 1307, 1185, 1077, 981, 895, 819};
-static const int16_t c[XNR3_LOOK_UP_TABLE_POINTS] = {
+static const s16 c[XNR3_LOOK_UP_TABLE_POINTS] = {
1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
/*
static int32_t
compute_alpha(int sigma)
{
- int32_t alpha;
+ s32 alpha;
#if defined(XNR_ATE_ROUNDING_BUG)
- int32_t alpha_unscaled;
+ s32 alpha_unscaled;
#else
int offset = sigma / 2;
#endif
alpha_unscaled = IA_CSS_XNR3_SIGMA_SCALE / sigma;
alpha = alpha_unscaled * XNR_ALPHA_SCALE_FACTOR;
#else
- alpha = ((IA_CSS_XNR3_SIGMA_SCALE * XNR_ALPHA_SCALE_FACTOR) + offset)/ sigma;
+ alpha = ((IA_CSS_XNR3_SIGMA_SCALE * XNR_ALPHA_SCALE_FACTOR) + offset) / sigma;
#endif
if (alpha > XNR_MAX_ALPHA)
static int32_t
compute_coring(int coring)
{
- int32_t isp_coring;
- int32_t isp_scale = XNR_CORING_SCALE_FACTOR;
- int32_t host_scale = IA_CSS_XNR3_CORING_SCALE;
- int32_t offset = host_scale / 2; /* fixed-point 0.5 */
+ s32 isp_coring;
+ s32 isp_scale = XNR_CORING_SCALE_FACTOR;
+ s32 host_scale = IA_CSS_XNR3_CORING_SCALE;
+ s32 offset = host_scale / 2; /* fixed-point 0.5 */
/* Convert from public host-side scale factor to isp-side scale
* factor. Clip to [0, isp_scale-1).
static int32_t
compute_blending(int strength)
{
- int32_t isp_strength;
- int32_t isp_scale = XNR_BLENDING_SCALE_FACTOR;
- int32_t host_scale = IA_CSS_XNR3_BLENDING_SCALE;
- int32_t offset = host_scale / 2; /* fixed-point 0.5 */
+ s32 isp_strength;
+ s32 isp_scale = XNR_BLENDING_SCALE_FACTOR;
+ s32 host_scale = IA_CSS_XNR3_BLENDING_SCALE;
+ s32 offset = host_scale / 2; /* fixed-point 0.5 */
/* Convert from public host-side scale factor to isp-side scale
* factor. The blending factor is positive on the host side, but
ia_css_xnr3_encode(
struct sh_css_isp_xnr3_params *to,
const struct ia_css_xnr3_config *from,
- unsigned size)
+ unsigned int size)
{
int kernel_size = XNR_FILTER_SIZE;
/* The adjust factor is the next power of 2
w.r.t. the kernel size*/
int adjust_factor = ceil_pow2(kernel_size);
- int32_t max_diff = (1 << (ISP_VEC_ELEMBITS - 1)) - 1;
- int32_t min_diff = -(1 << (ISP_VEC_ELEMBITS - 1));
-
- int32_t alpha_y0 = compute_alpha(from->sigma.y0);
- int32_t alpha_y1 = compute_alpha(from->sigma.y1);
- int32_t alpha_u0 = compute_alpha(from->sigma.u0);
- int32_t alpha_u1 = compute_alpha(from->sigma.u1);
- int32_t alpha_v0 = compute_alpha(from->sigma.v0);
- int32_t alpha_v1 = compute_alpha(from->sigma.v1);
- int32_t alpha_ydiff = (alpha_y1 - alpha_y0) * adjust_factor / kernel_size;
- int32_t alpha_udiff = (alpha_u1 - alpha_u0) * adjust_factor / kernel_size;
- int32_t alpha_vdiff = (alpha_v1 - alpha_v0) * adjust_factor / kernel_size;
-
- int32_t coring_u0 = compute_coring(from->coring.u0);
- int32_t coring_u1 = compute_coring(from->coring.u1);
- int32_t coring_v0 = compute_coring(from->coring.v0);
- int32_t coring_v1 = compute_coring(from->coring.v1);
- int32_t coring_udiff = (coring_u1 - coring_u0) * adjust_factor / kernel_size;
- int32_t coring_vdiff = (coring_v1 - coring_v0) * adjust_factor / kernel_size;
-
- int32_t blending = compute_blending(from->blending.strength);
+ s32 max_diff = (1 << (ISP_VEC_ELEMBITS - 1)) - 1;
+ s32 min_diff = -(1 << (ISP_VEC_ELEMBITS - 1));
+
+ s32 alpha_y0 = compute_alpha(from->sigma.y0);
+ s32 alpha_y1 = compute_alpha(from->sigma.y1);
+ s32 alpha_u0 = compute_alpha(from->sigma.u0);
+ s32 alpha_u1 = compute_alpha(from->sigma.u1);
+ s32 alpha_v0 = compute_alpha(from->sigma.v0);
+ s32 alpha_v1 = compute_alpha(from->sigma.v1);
+ s32 alpha_ydiff = (alpha_y1 - alpha_y0) * adjust_factor / kernel_size;
+ s32 alpha_udiff = (alpha_u1 - alpha_u0) * adjust_factor / kernel_size;
+ s32 alpha_vdiff = (alpha_v1 - alpha_v0) * adjust_factor / kernel_size;
+
+ s32 coring_u0 = compute_coring(from->coring.u0);
+ s32 coring_u1 = compute_coring(from->coring.u1);
+ s32 coring_v0 = compute_coring(from->coring.v0);
+ s32 coring_v1 = compute_coring(from->coring.v1);
+ s32 coring_udiff = (coring_u1 - coring_u0) * adjust_factor / kernel_size;
+ s32 coring_vdiff = (coring_v1 - coring_v0) * adjust_factor / kernel_size;
+
+ s32 blending = compute_blending(from->blending.strength);
(void)size;
ia_css_xnr3_vmem_encode(
struct sh_css_isp_xnr3_vmem_params *to,
const struct ia_css_xnr3_config *from,
- unsigned size)
+ unsigned int size)
{
- unsigned i, j, base;
- const unsigned total_blocks = 4;
- const unsigned shuffle_block = 16;
+ unsigned int i, j, base;
+ const unsigned int total_blocks = 4;
+ const unsigned int shuffle_block = 16;
(void)from;
(void)size;
for (j = 1; j < XNR3_LOOK_UP_TABLE_POINTS; j++) {
assert(x[j] >= 0);
assert(x[j] > x[j - 1]);
-
}
/* The implementation of the calulating 1/x is based on the availability
void
ia_css_xnr3_debug_dtrace(
const struct ia_css_xnr3_config *config,
- unsigned level)
+ unsigned int level)
{
(void)config;
(void)level;
ia_css_xnr3_encode(
struct sh_css_isp_xnr3_params *to,
const struct ia_css_xnr3_config *from,
- unsigned size);
+ unsigned int size);
#ifdef ISP2401
void
ia_css_xnr3_vmem_encode(
struct sh_css_isp_xnr3_vmem_params *to,
const struct ia_css_xnr3_config *from,
- unsigned size);
+ unsigned int size);
#endif
void
ia_css_xnr3_debug_dtrace(
const struct ia_css_xnr3_config *config,
- unsigned level);
+ unsigned int level);
#endif /* __IA_CSS_XNR3_HOST_H */
* It must be chosen such that 1/min_sigma still fits in an ISP vector
* element. */
#define XNR_ALPHA_SCALE_LOG2 5
-#define XNR_ALPHA_SCALE_FACTOR (1 << XNR_ALPHA_SCALE_LOG2)
+#define XNR_ALPHA_SCALE_FACTOR BIT(XNR_ALPHA_SCALE_LOG2)
/* Scaling factor of the coring values on the ISP. */
-#define XNR_CORING_SCALE_LOG2 (ISP_VEC_ELEMBITS-1)
-#define XNR_CORING_SCALE_FACTOR (1 << XNR_CORING_SCALE_LOG2)
+#define XNR_CORING_SCALE_LOG2 (ISP_VEC_ELEMBITS - 1)
+#define XNR_CORING_SCALE_FACTOR BIT(XNR_CORING_SCALE_LOG2)
/* Scaling factor of the blending strength on the ISP. */
-#define XNR_BLENDING_SCALE_LOG2 (ISP_VEC_ELEMBITS-1)
-#define XNR_BLENDING_SCALE_FACTOR (1 << XNR_BLENDING_SCALE_LOG2)
+#define XNR_BLENDING_SCALE_LOG2 (ISP_VEC_ELEMBITS - 1)
+#define XNR_BLENDING_SCALE_FACTOR BIT(XNR_BLENDING_SCALE_LOG2)
/* XNR3 filter size. Must be 11x11, 9x9 or 5x5. */
#ifdef FLT_KERNEL_9x9
/* XNR3 alpha (1/sigma) parameters on the ISP, expressed as a base (0) value
* for dark areas, and a scaled diff towards the value for bright areas. */
struct sh_css_xnr3_alpha_params {
- int32_t y0;
- int32_t u0;
- int32_t v0;
- int32_t ydiff;
- int32_t udiff;
- int32_t vdiff;
+ s32 y0;
+ s32 u0;
+ s32 v0;
+ s32 ydiff;
+ s32 udiff;
+ s32 vdiff;
};
/* XNR3 coring parameters on the ISP, expressed as a base (0) value
* for dark areas, and a scaled diff towards the value for bright areas. */
struct sh_css_xnr3_coring_params {
- int32_t u0;
- int32_t v0;
- int32_t udiff;
- int32_t vdiff;
+ s32 u0;
+ s32 v0;
+ s32 udiff;
+ s32 vdiff;
};
/* XNR3 blending strength on the ISP. */
struct sh_css_xnr3_blending_params {
- int32_t strength;
+ s32 strength;
};
/* XNR3 ISP parameters */
VMEM_ARRAY(c, ISP_VEC_NELEMS);
};
-
#endif
#endif /*__IA_CSS_XNR3_PARAM_H */
* \brief Scale of the XNR sigma parameters.
* \details The define specifies which fixed-point value represents 1.0.
*/
-#define IA_CSS_XNR3_SIGMA_SCALE (1 << 10)
+#define IA_CSS_XNR3_SIGMA_SCALE BIT(10)
/**
* \brief Scale of the XNR coring parameters.
* \details The define specifies which fixed-point value represents 1.0.
*/
-#define IA_CSS_XNR3_CORING_SCALE (1 << 15)
+#define IA_CSS_XNR3_CORING_SCALE BIT(15)
/**
* \brief Scale of the XNR blending parameter.
* \details The define specifies which fixed-point value represents 1.0.
*/
-#define IA_CSS_XNR3_BLENDING_SCALE (1 << 11)
-
+#define IA_CSS_XNR3_BLENDING_SCALE BIT(11)
/**
* \brief XNR3 Sigma Parameters.
ia_css_nr_encode(
struct sh_css_isp_ynr_params *to,
const struct ia_css_nr_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
/* YNR (Y Noise Reduction) */
to->threshold =
- uDIGIT_FITTING((unsigned)8192, 16, SH_CSS_BAYER_BITS);
+ uDIGIT_FITTING(8192U, 16, SH_CSS_BAYER_BITS);
to->gain_all =
uDIGIT_FITTING(from->ynr_gain, 16, SH_CSS_YNR_GAIN_SHIFT);
to->gain_dir =
ia_css_yee_encode(
struct sh_css_isp_yee_params *to,
const struct ia_css_yee_config *from,
- unsigned size)
+ unsigned int size)
{
- int asiWk1 = (int) from->ee.gain;
+ int asiWk1 = (int)from->ee.gain;
int asiWk2 = asiWk1 / 8;
int asiWk3 = asiWk1 / 4;
uDIGIT_FITTING(from->ee.detail_gain, 11,
SH_CSS_YEE_DETAIL_GAIN_SHIFT);
to->coring_s =
- (uDIGIT_FITTING((unsigned)56, 16, SH_CSS_BAYER_BITS) *
+ (uDIGIT_FITTING(56U, 16, SH_CSS_BAYER_BITS) *
from->ee.threshold) >> 8;
to->coring_g =
- (uDIGIT_FITTING((unsigned)224, 16, SH_CSS_BAYER_BITS) *
+ (uDIGIT_FITTING(224U, 16, SH_CSS_BAYER_BITS) *
from->ee.threshold) >> 8;
/* 8; // *1.125 ->[s4.8] */
to->scale_plus_s =
to->scale_minus_g =
(asiWk3) >> (11 - SH_CSS_YEE_SCALE_SHIFT);
to->clip_plus_s =
- uDIGIT_FITTING((unsigned)32760, 16, SH_CSS_BAYER_BITS);
+ uDIGIT_FITTING(32760U, 16, SH_CSS_BAYER_BITS);
to->clip_plus_g = 0;
to->clip_minus_s =
- uDIGIT_FITTING((unsigned)504, 16, SH_CSS_BAYER_BITS);
+ uDIGIT_FITTING(504U, 16, SH_CSS_BAYER_BITS);
to->clip_minus_g =
- uDIGIT_FITTING((unsigned)32256, 16, SH_CSS_BAYER_BITS);
+ uDIGIT_FITTING(32256U, 16, SH_CSS_BAYER_BITS);
to->Yclip = SH_CSS_BAYER_MAXVAL;
}
void
ia_css_nr_dump(
const struct sh_css_isp_ynr_params *ynr,
- unsigned level)
+ unsigned int level)
{
if (!ynr) return;
ia_css_debug_dtrace(level,
void
ia_css_yee_dump(
const struct sh_css_isp_yee_params *yee,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
"Y Edge Enhancement:\n");
void
ia_css_nr_debug_dtrace(
const struct ia_css_nr_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
- "config.direction=%d, "
- "config.bnr_gain=%d, config.ynr_gain=%d, "
- "config.threshold_cb=%d, config.threshold_cr=%d\n",
+ "config.direction=%d, config.bnr_gain=%d, config.ynr_gain=%d, config.threshold_cb=%d, config.threshold_cr=%d\n",
config->direction,
config->bnr_gain, config->ynr_gain,
config->threshold_cb, config->threshold_cr);
void
ia_css_ee_debug_dtrace(
const struct ia_css_ee_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
"config.threshold=%d, config.gain=%d, config.detail_gain=%d\n",
void
ia_css_init_ynr_state(
- void/*struct sh_css_isp_ynr_vmem_state*/ *state,
+ void/*struct sh_css_isp_ynr_vmem_state*/ * state,
size_t size)
{
memset(state, 0, size);
ia_css_nr_encode(
struct sh_css_isp_ynr_params *to,
const struct ia_css_nr_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_yee_encode(
struct sh_css_isp_yee_params *to,
const struct ia_css_yee_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_nr_dump(
const struct sh_css_isp_ynr_params *ynr,
- unsigned level);
+ unsigned int level);
void
ia_css_yee_dump(
const struct sh_css_isp_yee_params *yee,
- unsigned level);
+ unsigned int level);
void
ia_css_nr_debug_dtrace(
const struct ia_css_nr_config *config,
- unsigned level);
+ unsigned int level);
void
ia_css_ee_debug_dtrace(
const struct ia_css_ee_config *config,
- unsigned level);
+ unsigned int level);
void
ia_css_init_ynr_state(
- void/*struct sh_css_isp_ynr_vmem_state*/ *state,
+ void/*struct sh_css_isp_ynr_vmem_state*/ * state,
size_t size);
#endif /* __IA_CSS_YNR_HOST_H */
/* YNR (Y Noise Reduction) */
struct sh_css_isp_ynr_params {
- int32_t threshold;
- int32_t gain_all;
- int32_t gain_dir;
- int32_t threshold_cb;
- int32_t threshold_cr;
+ s32 threshold;
+ s32 gain_all;
+ s32 gain_dir;
+ s32 threshold_cb;
+ s32 threshold_cr;
};
/* YEE (Y Edge Enhancement) */
struct sh_css_isp_yee_params {
- int32_t dirthreshold_s;
- int32_t dirthreshold_g;
- int32_t dirthreshold_width_log2;
- int32_t dirthreshold_width;
- int32_t detailgain;
- int32_t coring_s;
- int32_t coring_g;
- int32_t scale_plus_s;
- int32_t scale_plus_g;
- int32_t scale_minus_s;
- int32_t scale_minus_g;
- int32_t clip_plus_s;
- int32_t clip_plus_g;
- int32_t clip_minus_s;
- int32_t clip_minus_g;
- int32_t Yclip;
+ s32 dirthreshold_s;
+ s32 dirthreshold_g;
+ s32 dirthreshold_width_log2;
+ s32 dirthreshold_width;
+ s32 detailgain;
+ s32 coring_s;
+ s32 coring_g;
+ s32 scale_plus_s;
+ s32 scale_plus_g;
+ s32 scale_minus_s;
+ s32 scale_minus_g;
+ s32 clip_plus_s;
+ s32 clip_plus_g;
+ s32 clip_minus_s;
+ s32 clip_minus_g;
+ s32 Yclip;
};
#endif /* __IA_CSS_YNR_PARAM_H */
/* YNR (luminance noise reduction) */
struct sh_css_isp_ynr_vmem_state {
- VMEM_ARRAY(ynr_buf[4], MAX_VECTORS_PER_BUF_LINE*ISP_NWAY);
+ VMEM_ARRAY(ynr_buf[4], MAX_VECTORS_PER_BUF_LINE * ISP_NWAY);
};
#endif /* __IA_CSS_YNR_STATE_H */
};
#endif /* __IA_CSS_YNR_TYPES_H */
-
(1 << (ISP_VEC_ELEMBITS - 2)), /* 0.5 */
(1 << (ISP_VEC_ELEMBITS - 1)) - 1, /* 1 */
(1 << (ISP_VEC_ELEMBITS - 1)) - 1, /* 1 */
- (int16_t)- (1 << (ISP_VEC_ELEMBITS - 1)), /* -1 */
- (int16_t)- (1 << (ISP_VEC_ELEMBITS - 1)), /* -1 */
+ (int16_t)-(1 << (ISP_VEC_ELEMBITS - 1)), /* -1 */
+ (int16_t)-(1 << (ISP_VEC_ELEMBITS - 1)), /* -1 */
};
void
ia_css_ynr_encode(
struct sh_css_isp_yee2_params *to,
const struct ia_css_ynr_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->edge_sense_gain_0 = from->edge_sense_gain_0;
ia_css_fc_encode(
struct sh_css_isp_fc_params *to,
const struct ia_css_fc_config *from,
- unsigned size)
+ unsigned int size)
{
(void)size;
to->gain_exp = from->gain_exp;
void
ia_css_ynr_dump(
const struct sh_css_isp_yee2_params *yee2,
- unsigned level);
+ unsigned int level);
void
ia_css_fc_dump(
const struct sh_css_isp_fc_params *fc,
- unsigned level);
+ unsigned int level);
void
ia_css_fc_debug_dtrace(
const struct ia_css_fc_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
- "config.gain_exp=%d, "
- "config.coring_pos_0=%d, config.coring_pos_1=%d, "
- "config.coring_neg_0=%d, config.coring_neg_1=%d, "
- "config.gain_pos_0=%d, config.gain_pos_1=%d, "
- "config.gain_neg_0=%d, config.gain_neg_1=%d, "
- "config.crop_pos_0=%d, config.crop_pos_1=%d, "
- "config.crop_neg_0=%d, config.crop_neg_1=%d\n",
+ "config.gain_exp=%d, config.coring_pos_0=%d, config.coring_pos_1=%d, config.coring_neg_0=%d, config.coring_neg_1=%d, config.gain_pos_0=%d, config.gain_pos_1=%d, config.gain_neg_0=%d, config.gain_neg_1=%d, config.crop_pos_0=%d, config.crop_pos_1=%d, config.crop_neg_0=%d, config.crop_neg_1=%d\n",
config->gain_exp,
config->coring_pos_0, config->coring_pos_1,
config->coring_neg_0, config->coring_neg_1,
void
ia_css_ynr_debug_dtrace(
const struct ia_css_ynr_config *config,
- unsigned level)
+ unsigned int level)
{
ia_css_debug_dtrace(level,
- "config.edge_sense_gain_0=%d, config.edge_sense_gain_1=%d, "
- "config.corner_sense_gain_0=%d, config.corner_sense_gain_1=%d\n",
+ "config.edge_sense_gain_0=%d, config.edge_sense_gain_1=%d, config.corner_sense_gain_0=%d, config.corner_sense_gain_1=%d\n",
config->edge_sense_gain_0, config->edge_sense_gain_1,
config->corner_sense_gain_0, config->corner_sense_gain_1);
}
ia_css_ynr_encode(
struct sh_css_isp_yee2_params *to,
const struct ia_css_ynr_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_fc_encode(
struct sh_css_isp_fc_params *to,
const struct ia_css_fc_config *from,
- unsigned size);
+ unsigned int size);
void
ia_css_ynr_dump(
const struct sh_css_isp_yee2_params *yee2,
- unsigned level);
+ unsigned int level);
void
ia_css_fc_dump(
const struct sh_css_isp_fc_params *fc,
- unsigned level);
+ unsigned int level);
void
ia_css_fc_debug_dtrace(
const struct ia_css_fc_config *config,
- unsigned level);
+ unsigned int level);
void
ia_css_ynr_debug_dtrace(
const struct ia_css_ynr_config *config,
- unsigned level);
+ unsigned int level);
#endif /* __IA_CSS_YNR2_HOST_H */
/* YNR (Y Noise Reduction), YEE (Y Edge Enhancement) */
struct sh_css_isp_yee2_params {
- int32_t edge_sense_gain_0;
- int32_t edge_sense_gain_1;
- int32_t corner_sense_gain_0;
- int32_t corner_sense_gain_1;
+ s32 edge_sense_gain_0;
+ s32 edge_sense_gain_1;
+ s32 corner_sense_gain_0;
+ s32 corner_sense_gain_1;
};
/* Fringe Control */
struct sh_css_isp_fc_params {
- int32_t gain_exp;
- uint16_t coring_pos_0;
- uint16_t coring_pos_1;
- uint16_t coring_neg_0;
- uint16_t coring_neg_1;
- int32_t gain_pos_0;
- int32_t gain_pos_1;
- int32_t gain_neg_0;
- int32_t gain_neg_1;
- int32_t crop_pos_0;
- int32_t crop_pos_1;
- int32_t crop_neg_0;
- int32_t crop_neg_1;
+ s32 gain_exp;
+ u16 coring_pos_0;
+ u16 coring_pos_1;
+ u16 coring_neg_0;
+ u16 coring_neg_1;
+ s32 gain_pos_0;
+ s32 gain_pos_1;
+ s32 gain_neg_0;
+ s32 gain_neg_1;
+ s32 crop_pos_0;
+ s32 crop_pos_1;
+ s32 crop_neg_0;
+ s32 crop_neg_1;
};
#endif /* __IA_CSS_YNR2_PARAM_H */
* ISP2: YNR2 and YEE2 are used for Still.
*/
struct ia_css_ynr_config {
- uint16_t edge_sense_gain_0; /** Sensitivity of edge in dark area.
+ u16 edge_sense_gain_0; /** Sensitivity of edge in dark area.
u13.0, [0,8191],
default 1000, ineffective 0 */
- uint16_t edge_sense_gain_1; /** Sensitivity of edge in bright area.
+ u16 edge_sense_gain_1; /** Sensitivity of edge in bright area.
u13.0, [0,8191],
default 1000, ineffective 0 */
- uint16_t corner_sense_gain_0; /** Sensitivity of corner in dark area.
+ u16 corner_sense_gain_0; /** Sensitivity of corner in dark area.
u13.0, [0,8191],
default 1000, ineffective 0 */
- uint16_t corner_sense_gain_1; /** Sensitivity of corner in bright area.
+ u16 corner_sense_gain_1; /** Sensitivity of corner in bright area.
u13.0, [0,8191],
default 1000, ineffective 0 */
};
* ISP2: FC2 is used for Still.
*/
struct ia_css_fc_config {
- uint8_t gain_exp; /** Common exponent of gains.
+ u8 gain_exp; /** Common exponent of gains.
u8.0, [0,13],
default 1, ineffective 0 */
- uint16_t coring_pos_0; /** Coring threshold for positive edge in dark area.
+ u16 coring_pos_0; /** Coring threshold for positive edge in dark area.
u0.13, [0,8191],
default 0(0), ineffective 0 */
- uint16_t coring_pos_1; /** Coring threshold for positive edge in bright area.
+ u16 coring_pos_1; /** Coring threshold for positive edge in bright area.
u0.13, [0,8191],
default 0(0), ineffective 0 */
- uint16_t coring_neg_0; /** Coring threshold for negative edge in dark area.
+ u16 coring_neg_0; /** Coring threshold for negative edge in dark area.
u0.13, [0,8191],
default 0(0), ineffective 0 */
- uint16_t coring_neg_1; /** Coring threshold for negative edge in bright area.
+ u16 coring_neg_1; /** Coring threshold for negative edge in bright area.
u0.13, [0,8191],
default 0(0), ineffective 0 */
- uint16_t gain_pos_0; /** Gain for positive edge in dark area.
+ u16 gain_pos_0; /** Gain for positive edge in dark area.
u0.13, [0,8191],
default 4096(0.5), ineffective 0 */
- uint16_t gain_pos_1; /** Gain for positive edge in bright area.
+ u16 gain_pos_1; /** Gain for positive edge in bright area.
u0.13, [0,8191],
default 4096(0.5), ineffective 0 */
- uint16_t gain_neg_0; /** Gain for negative edge in dark area.
+ u16 gain_neg_0; /** Gain for negative edge in dark area.
u0.13, [0,8191],
default 4096(0.5), ineffective 0 */
- uint16_t gain_neg_1; /** Gain for negative edge in bright area.
+ u16 gain_neg_1; /** Gain for negative edge in bright area.
u0.13, [0,8191],
default 4096(0.5), ineffective 0 */
- uint16_t crop_pos_0; /** Limit for positive edge in dark area.
+ u16 crop_pos_0; /** Limit for positive edge in dark area.
u0.13, [0,8191],
default/ineffective 8191(almost 1.0) */
- uint16_t crop_pos_1; /** Limit for positive edge in bright area.
+ u16 crop_pos_1; /** Limit for positive edge in bright area.
u0.13, [0,8191],
default/ineffective 8191(almost 1.0) */
- int16_t crop_neg_0; /** Limit for negative edge in dark area.
+ s16 crop_neg_0; /** Limit for negative edge in dark area.
s0.13, [-8192,0],
default/ineffective -8192(-1.0) */
- int16_t crop_neg_1; /** Limit for negative edge in bright area.
+ s16 crop_neg_1; /** Limit for negative edge in bright area.
s0.13, [-8192,0],
default/ineffective -8192(-1.0) */
};
#endif /* __IA_CSS_YNR2_TYPES_H */
-
/* Binary independent constants */
#ifndef NO_HOIST
-# define NO_HOIST HIVE_ATTRIBUTE (( no_hoist ))
+# define NO_HOIST HIVE_ATTRIBUTE((no_hoist))
#endif
-#define NO_HOIST_CSE HIVE_ATTRIBUTE ((no_hoist, no_cse))
+#define NO_HOIST_CSE HIVE_ATTRIBUTE((no_hoist, no_cse))
#define UNION struct /* Union constructors not allowed in C++ */
#endif
#define XMEM_WIDTH_BITS HIVE_ISP_DDR_WORD_BITS
-#define XMEM_SHORTS_PER_WORD (HIVE_ISP_DDR_WORD_BITS/16)
-#define XMEM_INTS_PER_WORD (HIVE_ISP_DDR_WORD_BITS/32)
+#define XMEM_SHORTS_PER_WORD (HIVE_ISP_DDR_WORD_BITS / 16)
+#define XMEM_INTS_PER_WORD (HIVE_ISP_DDR_WORD_BITS / 32)
#define XMEM_POW2_BYTES_PER_WORD HIVE_ISP_DDR_WORD_BYTES
#define BITS8_ELEMENTS_PER_XMEM_ADDR CEIL_DIV(XMEM_WIDTH_BITS, 8)
#define ISP_LEFT_PADDING_VECS_CONT CEIL_DIV(ISP_LEFT_PADDING_CONT, ISP_VEC_NELEMS)
#define CEIL_ROUND_DIV_STRIPE(width, stripe, padding) \
- CEIL_MUL(padding + CEIL_DIV(width - padding, stripe), ((ENABLE_RAW_BINNING || ENABLE_FIXED_BAYER_DS)?4:2))
+ CEIL_MUL(padding + CEIL_DIV(width - padding, stripe), ((ENABLE_RAW_BINNING || ENABLE_FIXED_BAYER_DS) ? 4 : 2))
/* output (Y,U,V) image, 4:2:0 */
#define MAX_VECTORS_PER_LINE \
ISP_NUM_STRIPES, \
ISP_LEFT_PADDING_VECS)
-
/* Add 2 for left croppping */
#define MAX_SP_RAW_COPY_VECTORS_PER_INPUT_LINE (CEIL_DIV(ISP_MAX_INPUT_WIDTH, ISP_VEC_NELEMS) + 2)
#define MAX_VECTORS_PER_CHUNK \
(NO_CHUNKING ? MAX_VECTORS_PER_LINE \
- : 2*CEIL_DIV(MAX_VECTORS_PER_LINE, \
- 2*OUTPUT_NUM_CHUNKS))
+ : 2 * CEIL_DIV(MAX_VECTORS_PER_LINE, \
+ 2 * OUTPUT_NUM_CHUNKS))
#define MAX_C_VECTORS_PER_CHUNK \
- (MAX_VECTORS_PER_CHUNK/2)
+ (MAX_VECTORS_PER_CHUNK / 2)
/* should be even */
#define MAX_VECTORS_PER_OUTPUT_CHUNK \
(NO_CHUNKING ? MAX_VECTORS_PER_OUTPUT_LINE \
- : 2*CEIL_DIV(MAX_VECTORS_PER_OUTPUT_LINE, \
- 2*OUTPUT_NUM_CHUNKS))
+ : 2 * CEIL_DIV(MAX_VECTORS_PER_OUTPUT_LINE, \
+ 2 * OUTPUT_NUM_CHUNKS))
#define MAX_C_VECTORS_PER_OUTPUT_CHUNK \
- (MAX_VECTORS_PER_OUTPUT_CHUNK/2)
-
-
+ (MAX_VECTORS_PER_OUTPUT_CHUNK / 2)
/* should be even */
#define MAX_VECTORS_PER_INPUT_CHUNK \
(INPUT_NUM_CHUNKS == 1 ? MAX_VECTORS_PER_INPUT_STRIPE \
- : 2*CEIL_DIV(MAX_VECTORS_PER_INPUT_STRIPE, \
- 2*OUTPUT_NUM_CHUNKS))
+ : 2 * CEIL_DIV(MAX_VECTORS_PER_INPUT_STRIPE, \
+ 2 * OUTPUT_NUM_CHUNKS))
#define DEFAULT_C_SUBSAMPLING 2
#define RAW_BUF_STRIDE \
(BINARY_ID == SH_CSS_BINARY_ID_POST_ISP ? MAX_VECTORS_PER_INPUT_CHUNK : \
- ISP_NUM_STRIPES > 1 ? MAX_VECTORS_PER_INPUT_STRIPE+_ISP_EXTRA_PADDING_VECS : \
+ ISP_NUM_STRIPES > 1 ? MAX_VECTORS_PER_INPUT_STRIPE + _ISP_EXTRA_PADDING_VECS : \
!ENABLE_CONTINUOUS ? MAX_VECTORS_PER_INPUT_LINE : \
MAX_VECTORS_PER_INPUT_CHUNK)
struct isp_uds_config {
int hive_dx;
int hive_dy;
- unsigned hive_woix;
- unsigned hive_bpp; /* gdc_bits_per_pixel */
- unsigned hive_bci;
+ unsigned int hive_woix;
+ unsigned int hive_bpp; /* gdc_bits_per_pixel */
+ unsigned int hive_bci;
};
struct s_isp_gdcac_config {
- unsigned nbx;
- unsigned nby;
+ unsigned int nbx;
+ unsigned int nby;
};
/* output.hive.c request information */
} output_channel_type;
typedef struct s_output_dma_info {
- unsigned cond; /* Condition for transfer */
+ unsigned int cond; /* Condition for transfer */
output_channel_type channel_type;
dma_channel channel;
- unsigned width_a;
- unsigned width_b;
- unsigned stride;
- unsigned v_delta; /* Offset for v address to do cropping */
+ unsigned int width_a;
+ unsigned int width_b;
+ unsigned int stride;
+ unsigned int v_delta; /* Offset for v address to do cropping */
char *x_base; /* X base address */
} output_dma_info_type;
#endif
#include "memory_access.h"
static bool realloc_isp_css_mm_buf(
- hrt_vaddress *curr_buf,
+ hrt_vaddress * curr_buf,
size_t *curr_size,
size_t needed_size,
bool force,
enum ia_css_err *err,
uint16_t mmgr_attribute);
-
bool reallocate_buffer(
- hrt_vaddress *curr_buf,
+ hrt_vaddress * curr_buf,
size_t *curr_size,
size_t needed_size,
bool force,
enum ia_css_err *err)
{
bool ret;
- uint16_t mmgr_attribute = MMGR_ATTRIBUTE_DEFAULT;
+ u16 mmgr_attribute = MMGR_ATTRIBUTE_DEFAULT;
IA_CSS_ENTER_PRIVATE("void");
}
static bool realloc_isp_css_mm_buf(
- hrt_vaddress *curr_buf,
+ hrt_vaddress * curr_buf,
size_t *curr_size,
size_t needed_size,
bool force,
enum ia_css_err *err,
uint16_t mmgr_attribute)
{
- int32_t id;
+ s32 id;
*err = IA_CSS_SUCCESS;
/* Possible optimization: add a function sh_css_isp_css_mm_realloc()
struct ia_css_resolution *binary_dvs_env)
{
if (info->enable.dvs_envelope) {
- assert(dvs_env != NULL);
+ assert(dvs_env);
binary_dvs_env->width = max(dvs_env->width, SH_CSS_MIN_DVS_ENVELOPE);
binary_dvs_env->height = max(dvs_env->height, SH_CSS_MIN_DVS_ENVELOPE);
}
ia_css_binary_dvs_env(info, dvs_env, &binary_dvs_env);
if (binary_supports_yuv_ds) {
- if (in_info != NULL) {
+ if (in_info) {
isp_tmp_internal_width = in_info->res.width
+ info->pipeline.left_cropping + binary_dvs_env.width;
isp_tmp_internal_height = in_info->res.height
+ info->pipeline.top_cropping + binary_dvs_env.height;
}
- } else if ((bds_out_info != NULL) && (out_info != NULL) &&
+ } else if ((bds_out_info) && (out_info) &&
/* TODO: hack to make video_us case work. this should be reverted after
a nice solution in ISP */
(bds_out_info->res.width >= out_info->res.width)) {
isp_tmp_internal_width = bds_out_info->padded_width;
isp_tmp_internal_height = bds_out_info->res.height;
} else {
- if (out_info != NULL) {
+ if (out_info) {
isp_tmp_internal_width = out_info->padded_width;
isp_tmp_internal_height = out_info->res.height;
}
#ifndef ISP2401
/* Computation results of the origin coordinate of bayer on the shading table. */
struct sh_css_shading_table_bayer_origin_compute_results {
- uint32_t bayer_scale_hor_ratio_in; /* Horizontal ratio (in) of bayer scaling. */
- uint32_t bayer_scale_hor_ratio_out; /* Horizontal ratio (out) of bayer scaling. */
- uint32_t bayer_scale_ver_ratio_in; /* Vertical ratio (in) of bayer scaling. */
- uint32_t bayer_scale_ver_ratio_out; /* Vertical ratio (out) of bayer scaling. */
- uint32_t sc_bayer_origin_x_bqs_on_shading_table; /* X coordinate (in bqs) of bayer origin on shading table. */
- uint32_t sc_bayer_origin_y_bqs_on_shading_table; /* Y coordinate (in bqs) of bayer origin on shading table. */
+ u32 bayer_scale_hor_ratio_in; /* Horizontal ratio (in) of bayer scaling. */
+ u32 bayer_scale_hor_ratio_out; /* Horizontal ratio (out) of bayer scaling. */
+ u32 bayer_scale_ver_ratio_in; /* Vertical ratio (in) of bayer scaling. */
+ u32 bayer_scale_ver_ratio_out; /* Vertical ratio (out) of bayer scaling. */
+ u32 sc_bayer_origin_x_bqs_on_shading_table; /* X coordinate (in bqs) of bayer origin on shading table. */
+ u32 sc_bayer_origin_y_bqs_on_shading_table; /* Y coordinate (in bqs) of bayer origin on shading table. */
#else
/* Requirements for the shading correction. */
struct sh_css_binary_sc_requirements {
/* Bayer scaling factor, for the scaling which is applied before shading correction. */
- uint32_t bayer_scale_hor_ratio_in; /* Horizontal ratio (in) of scaling applied BEFORE shading correction. */
- uint32_t bayer_scale_hor_ratio_out; /* Horizontal ratio (out) of scaling applied BEFORE shading correction. */
- uint32_t bayer_scale_ver_ratio_in; /* Vertical ratio (in) of scaling applied BEFORE shading correction. */
- uint32_t bayer_scale_ver_ratio_out; /* Vertical ratio (out) of scaling applied BEFORE shading correction. */
+ u32 bayer_scale_hor_ratio_in; /* Horizontal ratio (in) of scaling applied BEFORE shading correction. */
+ u32 bayer_scale_hor_ratio_out; /* Horizontal ratio (out) of scaling applied BEFORE shading correction. */
+ u32 bayer_scale_ver_ratio_in; /* Vertical ratio (in) of scaling applied BEFORE shading correction. */
+ u32 bayer_scale_ver_ratio_out; /* Vertical ratio (out) of scaling applied BEFORE shading correction. */
/* ISP internal frame is composed of the real sensor data and the padding data. */
- uint32_t sensor_data_origin_x_bqs_on_internal; /* X origin (in bqs) of sensor data on internal frame
+ u32 sensor_data_origin_x_bqs_on_internal; /* X origin (in bqs) of sensor data on internal frame
at shading correction. */
- uint32_t sensor_data_origin_y_bqs_on_internal; /* Y origin (in bqs) of sensor data on internal frame
+ u32 sensor_data_origin_y_bqs_on_internal; /* Y origin (in bqs) of sensor data on internal frame
at shading correction. */
#endif
};
int top_padding_bqsxfrac_acc = (top_cropping_bqs * factor - top_cropping_bqs * bds_frac_acc)
+ (2 * bds_frac_acc - factor); /* top padding by fixed-point (in bqs) */
- top_padding_bqs = (unsigned int)((top_padding_bqsxfrac_acc + bds_frac_acc/2 - 1) / bds_frac_acc);
+ top_padding_bqs = (unsigned int)((top_padding_bqsxfrac_acc + bds_frac_acc / 2 - 1) / bds_frac_acc);
}
IA_CSS_LOG("top_cropping=%d, top_padding_bqs=%d", binary->info->sp.pipeline.top_cropping, top_padding_bqs);
located on the shading table during the shading correction. */
res->sc_bayer_origin_x_bqs_on_shading_table
= ((left_padding_adjusted_bqs + bad_bqs_on_left_before_bs)
- * bs_hor_ratio_out + bs_hor_ratio_in/2) / bs_hor_ratio_in
+ * bs_hor_ratio_out + bs_hor_ratio_in / 2) / bs_hor_ratio_in
+ bad_bqs_on_left_after_bs;
/* "+ bs_hor_ratio_in/2": rounding for division by bs_hor_ratio_in */
res->sc_bayer_origin_y_bqs_on_shading_table
= (bad_bqs_on_top_before_bs
- * bs_ver_ratio_out + bs_ver_ratio_in/2) / bs_ver_ratio_in
+ * bs_ver_ratio_out + bs_ver_ratio_in / 2) / bs_ver_ratio_in
+ bad_bqs_on_top_after_bs;
/* "+ bs_ver_ratio_in/2": rounding for division by bs_ver_ratio_in */
bs_out = bs_hor_ratio_out * bs_frac;
bs_in = bs_hor_ratio_in * bs_frac;
sensor_data_origin_x_bqs_on_internal
- = ((left_padding_adjusted_bqs + right_shift_bqs_before_bs) * bs_out + bs_in/2) / bs_in
+ = ((left_padding_adjusted_bqs + right_shift_bqs_before_bs) * bs_out + bs_in / 2) / bs_in
+ right_shift_bqs_after_bs; /* "+ bs_in/2": rounding */
bs_out = bs_ver_ratio_out * bs_frac;
bs_in = bs_ver_ratio_in * bs_frac;
sensor_data_origin_y_bqs_on_internal
- = ((top_padding_bqs + down_shift_bqs_before_bs) * bs_out + bs_in/2) / bs_in
+ = ((top_padding_bqs + down_shift_bqs_before_bs) * bs_out + bs_in / 2) / bs_in
+ down_shift_bqs_after_bs; /* "+ bs_in/2": rounding */
}
#endif
#ifndef ISP2401
- assert(binary != NULL);
- assert(info != NULL);
+ assert(binary);
+ assert(info);
#else
- uint32_t in_width_bqs, in_height_bqs, internal_width_bqs, internal_height_bqs;
- uint32_t num_hor_grids, num_ver_grids, bqs_per_grid_cell, tbl_width_bqs, tbl_height_bqs;
- uint32_t sensor_org_x_bqs_on_internal, sensor_org_y_bqs_on_internal, sensor_width_bqs, sensor_height_bqs;
- uint32_t sensor_center_x_bqs_on_internal, sensor_center_y_bqs_on_internal;
- uint32_t left, right, upper, lower;
- uint32_t adjust_left, adjust_right, adjust_upper, adjust_lower, adjust_width_bqs, adjust_height_bqs;
- uint32_t internal_org_x_bqs_on_tbl, internal_org_y_bqs_on_tbl;
- uint32_t sensor_org_x_bqs_on_tbl, sensor_org_y_bqs_on_tbl;
+ u32 in_width_bqs, in_height_bqs, internal_width_bqs, internal_height_bqs;
+ u32 num_hor_grids, num_ver_grids, bqs_per_grid_cell, tbl_width_bqs, tbl_height_bqs;
+ u32 sensor_org_x_bqs_on_internal, sensor_org_y_bqs_on_internal, sensor_width_bqs, sensor_height_bqs;
+ u32 sensor_center_x_bqs_on_internal, sensor_center_y_bqs_on_internal;
+ u32 left, right, upper, lower;
+ u32 adjust_left, adjust_right, adjust_upper, adjust_lower, adjust_width_bqs, adjust_height_bqs;
+ u32 internal_org_x_bqs_on_tbl, internal_org_y_bqs_on_tbl;
+ u32 sensor_org_x_bqs_on_tbl, sensor_org_y_bqs_on_tbl;
#endif
#ifndef ISP2401
info->type = IA_CSS_SHADING_CORRECTION_TYPE_1;
#else
- assert(binary != NULL);
- assert(stream_config != NULL);
- assert(shading_info != NULL);
- assert(pipe_config != NULL);
+ assert(binary);
+ assert(stream_config);
+ assert(shading_info);
+ assert(pipe_config);
#endif
#ifndef ISP2401
bs_out = scr.bayer_scale_hor_ratio_out * bs_frac;
bs_in = scr.bayer_scale_hor_ratio_in * bs_frac;
- sensor_width_bqs = (in_width_bqs * bs_out + bs_in/2) / bs_in; /* "+ bs_in/2": rounding */
+ sensor_width_bqs = (in_width_bqs * bs_out + bs_in / 2) / bs_in; /* "+ bs_in/2": rounding */
bs_out = scr.bayer_scale_ver_ratio_out * bs_frac;
bs_in = scr.bayer_scale_ver_ratio_in * bs_frac;
- sensor_height_bqs = (in_height_bqs * bs_out + bs_in/2) / bs_in; /* "+ bs_in/2": rounding */
+ sensor_height_bqs = (in_height_bqs * bs_out + bs_in / 2) / bs_in; /* "+ bs_in/2": rounding */
}
/* Center of the sensor data on the internal frame at shading correction. */
{
enum ia_css_err err;
- assert(binary != NULL);
+ assert(binary);
#ifndef ISP2401
- assert(info != NULL);
+ assert(info);
#else
- assert(shading_info != NULL);
+ assert(shading_info);
IA_CSS_ENTER_PRIVATE("binary=%p, type=%d, required_bds_factor=%d, stream_config=%p",
binary, type, required_bds_factor, stream_config);
static void sh_css_binary_common_grid_info(const struct ia_css_binary *binary,
struct ia_css_grid_info *info)
{
- assert(binary != NULL);
- assert(info != NULL);
+ assert(binary);
+ assert(info);
info->isp_in_width = binary->internal_frame_info.res.width;
info->isp_in_height = binary->internal_frame_info.res.height;
struct ia_css_dvs_grid_info *dvs_info;
(void)pipe;
- assert(binary != NULL);
- assert(info != NULL);
+ assert(binary);
+ assert(info);
dvs_info = &info->dvs_grid.dvs_grid_info;
IA_CSS_ENTER_PRIVATE("binary=%p, info=%p, pipe=%p",
binary, info, pipe);
- assert(binary != NULL);
- assert(info != NULL);
+ assert(binary);
+ assert(info);
s3a_info = &info->s3a_grid;
-
/* 3A statistics grid */
s3a_info->enable = binary->info->sp.enable.s3a;
s3a_info->width = binary->s3atbl_width;
static void
binary_init_pc_histogram(struct sh_css_pc_histogram *histo)
{
- assert(histo != NULL);
+ assert(histo);
histo->length = 0;
histo->run = NULL;
binary_init_metrics(struct sh_css_binary_metrics *metrics,
const struct ia_css_binary_info *info)
{
- assert(metrics != NULL);
- assert(info != NULL);
+ assert(metrics);
+ assert(info);
metrics->mode = info->pipeline.mode;
metrics->id = info->id;
{
int i;
- assert(info != NULL);
+ assert(info);
for (i = 0; i < info->num_output_formats; i++) {
if (info->output_formats[i] == format)
binary_supports_input_format(const struct ia_css_binary_xinfo *info,
enum atomisp_input_format format)
{
-
- assert(info != NULL);
+ assert(info);
(void)format;
return true;
{
int i;
- assert(info != NULL);
+ assert(info);
for (i = 0; i < info->num_vf_formats; i++) {
if (info->vf_formats[i] == format)
/* move to host part of bds module */
static bool
-supports_bds_factor(uint32_t supported_factors,
+supports_bds_factor(u32 supported_factors,
uint32_t bds_factor)
{
return ((supported_factors & PACK_BDS_FACTOR(bds_factor)) != 0);
bool *binary_found)
{
const unsigned char *blob = sh_css_blob_info[i].blob;
- unsigned size = sh_css_blob_info[i].header.blob.size;
+ unsigned int size = sh_css_blob_info[i].header.blob.size;
- if ((info == NULL) || (binary_found == NULL))
+ if ((!info) || (!binary_found))
return IA_CSS_ERR_INVALID_ARGUMENTS;
*info = sh_css_blob_info[i].header.info.isp;
- *binary_found = blob != NULL;
+ *binary_found = blob;
info->blob_index = i;
/* we don't have this binary, skip it */
if (!size)
all_binaries = sh_css_malloc(num_of_isp_binaries *
sizeof(*all_binaries));
- if (all_binaries == NULL)
+ if (!all_binaries)
return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
for (i = 0; i < num_of_isp_binaries; i++) {
nr_of_left_paddings = 0;
#else
/* in other cases, the left padding pixels are always 128 */
- nr_of_left_paddings = 2*ISP_VEC_NELEMS;
+ nr_of_left_paddings = 2 * ISP_VEC_NELEMS;
#endif
if (need_scaling) {
/* In SDV use-case, we need to match left-padding of
/* Different than before, we do left&right padding. */
rval =
CEIL_MUL(in_frame_width + nr_of_left_paddings,
- 2*ISP_VEC_NELEMS);
+ 2 * ISP_VEC_NELEMS);
} else {
/* Different than before, we do left&right padding. */
in_frame_width += dvs_env_width;
rval =
CEIL_MUL(in_frame_width +
(left_cropping ? nr_of_left_paddings : 0),
- 2*ISP_VEC_NELEMS);
+ 2 * ISP_VEC_NELEMS);
}
} else {
rval = isp_internal_width;
return rval;
}
-
enum ia_css_err
ia_css_binary_fill_info(const struct ia_css_binary_xinfo *xinfo,
bool online,
unsigned int i;
const struct ia_css_frame_info *bin_out_info = NULL;
- assert(info != NULL);
- assert(binary != NULL);
+ assert(info);
+ assert(binary);
binary->info = xinfo;
if (!accelerator) {
break;
}
}
- if (in_info != NULL && bin_out_info != NULL) {
+ if (in_info && bin_out_info) {
need_scaling = (in_info->res.width != bin_out_info->res.width) ||
(in_info->res.height != bin_out_info->res.height);
}
-
/* binary_dvs_env has to be equal or larger than SH_CSS_MIN_DVS_ENVELOPE */
binary_dvs_env.width = 0;
binary_dvs_env.height = 0;
isp_internal_height = internal_res.height;
/* internal frame info */
- if (bin_out_info != NULL) /* { */
+ if (bin_out_info) /* { */
binary->internal_frame_info.format = bin_out_info->format;
/* } */
binary->internal_frame_info.res.width = isp_internal_width;
- binary->internal_frame_info.padded_width = CEIL_MUL(isp_internal_width, 2*ISP_VEC_NELEMS);
+ binary->internal_frame_info.padded_width = CEIL_MUL(isp_internal_width, 2 * ISP_VEC_NELEMS);
binary->internal_frame_info.res.height = isp_internal_height;
binary->internal_frame_info.raw_bit_depth = bits_per_pixel;
- if (in_info != NULL) {
+ if (in_info) {
binary->effective_in_frame_res.width = in_info->res.width;
binary->effective_in_frame_res.height = in_info->res.height;
binary->in_frame_info.raw_bit_depth = bits_per_pixel;
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
- if (out_info[i] != NULL) {
+ if (out_info[i]) {
binary->out_frame_info[i].res.width = out_info[i]->res.width;
binary->out_frame_info[i].res.height = out_info[i]->res.height;
binary->out_frame_info[i].padded_width = out_info[i]->padded_width;
binary->input_format = stream_format;
/* viewfinder output info */
- if ((vf_info != NULL) && (vf_info->res.width != 0)) {
+ if ((vf_info) && (vf_info->res.width != 0)) {
unsigned int vf_out_vecs, vf_out_width, vf_out_height;
+
binary->vf_frame_info.format = vf_info->format;
- if (bin_out_info == NULL)
+ if (!bin_out_info)
return IA_CSS_ERR_INTERNAL_ERROR;
vf_out_vecs = __ISP_VF_OUTPUT_WIDTH_VECS(bin_out_info->padded_width,
vf_log_ds);
sc_3a_dis_width = binary->in_frame_info.res.width;
sc_3a_dis_padded_width = binary->in_frame_info.padded_width;
sc_3a_dis_height = binary->in_frame_info.res.height;
- if (bds_out_info != NULL && in_info != NULL &&
+ if (bds_out_info && in_info &&
bds_out_info->res.width != in_info->res.width) {
/* TODO: Next, "internal_frame_info" should be derived from
* bds_out. So this part will change once it is in place! */
sc_3a_dis_height = isp_internal_height;
}
-
s3a_isp_width = _ISP_S3A_ELEMS_ISP_WIDTH(sc_3a_dis_padded_width,
info->pipeline.left_cropping);
if (info->s3a.fixed_s3a_deci_log) {
struct ia_css_resolution dvs_env, internal_res;
unsigned int i;
- assert(descr != NULL);
+ assert(descr);
/* MW: used after an error check, may accept NULL, but doubtfull */
- assert(binary != NULL);
+ assert(binary);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_binary_find() enter: descr=%p, (mode=%d), binary=%p\n",
if (req_out_info[i] && (req_out_info[i]->res.width != 0))
req_bin_out_info = req_out_info[i];
}
- if (req_bin_out_info == NULL)
+ if (!req_bin_out_info)
return IA_CSS_ERR_INTERNAL_ERROR;
#ifndef ISP2401
req_vf_info = descr->vf_info;
#else
- if ((descr->vf_info != NULL) && (descr->vf_info->res.width == 0))
+ if ((descr->vf_info) && (descr->vf_info->res.width == 0))
/* width==0 means that there is no vf pin (e.g. in SkyCam preview case) */
req_vf_info = NULL;
else
internal_res.width = 0;
internal_res.height = 0;
-
if (mode == IA_CSS_BINARY_MODE_VIDEO) {
dvs_env = descr->dvs_env;
need_dz = descr->enable_dz;
need_dz = false;
/* when we require vf output, we need to have vf_veceven */
- if ((req_vf_info != NULL) && !(candidate->enable.vf_veceven ||
+ if ((req_vf_info) && !(candidate->enable.vf_veceven ||
/* or variable vf vec even */
candidate->vf_dec.is_variable ||
/* or more than one output pin. */
continue;
}
- if(!candidate->enable.tnr && need_tnr) {
+ if (!candidate->enable.tnr && need_tnr) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_binary_find() [%d] continue: !%d && %d\n",
__LINE__, candidate->enable.tnr,
ia_css_binary_get_isp_binaries(struct ia_css_binary_xinfo **binaries,
uint32_t *num_isp_binaries)
{
- assert(binaries != NULL);
+ assert(binaries);
if (num_isp_binaries)
*num_isp_binaries = 0;
#include "ia_css_err.h"
#define BUFQ_EVENT_SIZE 4
-
/**
* @brief Query the internal frame ID.
*
enum sh_css_queue_id *val
);
-
/**
* @brief Map buffer type to a internal queue id.
*
bool map
);
-
/**
* @brief Initialize buffer type to a queue id mapping
* @return none
*/
void ia_css_queue_map_init(void);
-
/**
* @brief initializes bufq module
* It create instances of
*/
void ia_css_bufq_init(void);
-
/**
* @brief Enqueues an item into host to SP buffer queue
*
*
*/
enum ia_css_err ia_css_bufq_enqueue_psys_event(
- uint8_t evt_id,
- uint8_t evt_payload_0,
- uint8_t evt_payload_1,
+ u8 evt_id,
+ u8 evt_payload_0,
+ u8 evt_payload_1,
uint8_t evt_payload_2
);
*
*/
enum ia_css_err ia_css_bufq_dequeue_psys_event(
- uint8_t item[BUFQ_EVENT_SIZE]
+ u8 item[BUFQ_EVENT_SIZE]
+
);
/**
*
*/
enum ia_css_err ia_css_bufq_dequeue_isys_event(
- uint8_t item[BUFQ_EVENT_SIZE]);
+ u8 item[BUFQ_EVENT_SIZE]);
/**
* @brief Enqueue a tagger command item into tagger command queue..
#endif
#if defined(HAS_NO_INPUT_SYSTEM) || defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401)
-#define SH_CSS_MAX_NUM_QUEUES (SH_CSS_QUEUE_H_ID+1)
+#define SH_CSS_MAX_NUM_QUEUES (SH_CSS_QUEUE_H_ID + 1)
#else
-#define SH_CSS_MAX_NUM_QUEUES (SH_CSS_QUEUE_G_ID+1)
+#define SH_CSS_MAX_NUM_QUEUES (SH_CSS_QUEUE_G_ID + 1)
#endif
};
{
IA_CSS_ENTER("buf_type=%d, thread_id=%d, val = %p", buf_type, thread_id, val);
- if ((val == NULL) || (thread_id >= SH_CSS_MAX_SP_THREADS) || (buf_type >= IA_CSS_NUM_DYNAMIC_BUFFER_TYPE)) {
+ if ((!val) || (thread_id >= SH_CSS_MAX_SP_THREADS) || (buf_type >= IA_CSS_NUM_DYNAMIC_BUFFER_TYPE)) {
IA_CSS_LEAVE("return_val = false");
return false;
}
queue_availability[thread_id][queue_id] = true;
}
-
static ia_css_queue_t *bufq_get_qhandle(
enum sh_css_queue_type type,
enum sh_css_queue_id id,
q = bufq_get_qhandle(sh_css_host2sp_buffer_queue,
queue_id,
thread_index);
- if (q != NULL) {
+ if (q) {
error = ia_css_queue_enqueue(q, item);
return_err = ia_css_convert_errno(error);
} else {
ia_css_queue_t *q;
IA_CSS_ENTER_PRIVATE("queue_id=%d", queue_id);
- if ((item == NULL) ||
+ if ((!item) ||
(queue_id <= SH_CSS_INVALID_QUEUE_ID) ||
(queue_id >= SH_CSS_MAX_NUM_QUEUES)
)
q = bufq_get_qhandle(sh_css_sp2host_buffer_queue,
queue_id,
-1);
- if (q != NULL) {
+ if (q) {
error = ia_css_queue_dequeue(q, item);
return_err = ia_css_convert_errno(error);
} else {
}
enum ia_css_err ia_css_bufq_enqueue_psys_event(
- uint8_t evt_id,
- uint8_t evt_payload_0,
- uint8_t evt_payload_1,
+ u8 evt_id,
+ u8 evt_payload_0,
+ u8 evt_payload_1,
uint8_t evt_payload_2)
{
enum ia_css_err return_err;
IA_CSS_ENTER_PRIVATE("evt_id=%d", evt_id);
q = bufq_get_qhandle(sh_css_host2sp_psys_event_queue, -1, -1);
- if (NULL == q) {
+ if (!q) {
IA_CSS_ERROR("queue is not initialized");
return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE;
}
}
enum ia_css_err ia_css_bufq_dequeue_psys_event(
- uint8_t item[BUFQ_EVENT_SIZE])
+ u8 item[BUFQ_EVENT_SIZE])
{
enum ia_css_err;
int error = 0;
/* No ENTER/LEAVE in this function since this is polled
* by some test apps. Enablign logging here floods the log
* files which may cause timeouts. */
- if (item == NULL)
+ if (!item)
return IA_CSS_ERR_INVALID_ARGUMENTS;
q = bufq_get_qhandle(sh_css_sp2host_psys_event_queue, -1, -1);
- if (NULL == q) {
+ if (!q) {
IA_CSS_ERROR("queue is not initialized");
return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE;
}
error = ia_css_eventq_recv(q, item);
return ia_css_convert_errno(error);
-
}
enum ia_css_err ia_css_bufq_dequeue_isys_event(
- uint8_t item[BUFQ_EVENT_SIZE])
+ u8 item[BUFQ_EVENT_SIZE])
{
#if !defined(HAS_NO_INPUT_SYSTEM)
enum ia_css_err;
/* No ENTER/LEAVE in this function since this is polled
* by some test apps. Enablign logging here floods the log
* files which may cause timeouts. */
- if (item == NULL)
+ if (!item)
return IA_CSS_ERR_INVALID_ARGUMENTS;
q = bufq_get_qhandle(sh_css_sp2host_isys_event_queue, -1, -1);
- if (q == NULL) {
+ if (!q) {
IA_CSS_ERROR("queue is not initialized");
return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE;
}
IA_CSS_ENTER_PRIVATE("event_id=%d", evt_id);
q = bufq_get_qhandle(sh_css_host2sp_isys_event_queue, -1, -1);
- if (q == NULL) {
+ if (!q) {
IA_CSS_ERROR("queue is not initialized");
return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE;
}
IA_CSS_ENTER_PRIVATE("item=%d", item);
q = bufq_get_qhandle(sh_css_host2sp_tag_cmd_queue, -1, -1);
- if (NULL == q) {
+ if (!q) {
IA_CSS_ERROR("queue is not initialized");
return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE;
}
static void bufq_dump_queue_info(const char *prefix, ia_css_queue_t *qhandle)
{
- uint32_t free = 0, used = 0;
- assert(prefix != NULL && qhandle != NULL);
+ u32 free = 0, used = 0;
+
+ assert(prefix && qhandle);
ia_css_queue_get_used_space(qhandle, &used);
ia_css_queue_get_free_space(qhandle, &free);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s: used=%u free=%u\n",
prefix, used, free);
-
}
void ia_css_bufq_dump_queue_info(void)
}
__printf(2, 3)
-extern void ia_css_debug_dtrace(unsigned int level, const char *fmt, ...);
+void ia_css_debug_dtrace(unsigned int level, const char *fmt, ...);
/*! @brief Dump sp thread's stack contents
* SP thread's stack contents are set to 0xcafecafe. This function dumps the
void ia_css_debug_dump_pipe_config(
const struct ia_css_pipe_config *config);
-
/*! @brief Dump the stream config source info to the trace output
* Dumps the stream config source info to the trace output.
* @param[in] config pointer to struct ia_css_stream_config
*
* @return None
*/
-extern void ia_css_debug_pipe_graph_dump_prologue(void);
+void ia_css_debug_pipe_graph_dump_prologue(void);
/**
* @brief Internal debug support for constructing a pipe graph.
*
* @return None
*/
-extern void ia_css_debug_pipe_graph_dump_epilogue(void);
+void ia_css_debug_pipe_graph_dump_epilogue(void);
/**
* @brief Internal debug support for constructing a pipe graph.
*
* @return None
*/
-extern void ia_css_debug_pipe_graph_dump_stage(
+void ia_css_debug_pipe_graph_dump_stage(
struct ia_css_pipeline_stage *stage,
enum ia_css_pipe_id id);
*
* @return None
*/
-extern void ia_css_debug_pipe_graph_dump_sp_raw_copy(
+void ia_css_debug_pipe_graph_dump_sp_raw_copy(
struct ia_css_frame *out_frame);
-
/**
* @brief Internal debug support for constructing a pipe graph.
* @param[in] stream_config info about sensor and input formatter.
*
* @return None
*/
-extern void ia_css_debug_pipe_graph_dump_stream_config(
+void ia_css_debug_pipe_graph_dump_stream_config(
const struct ia_css_stream_config *stream_config);
#endif /* _IA_CSS_DEBUG_PIPE_H_ */
#define ENABLE_LINE_MAX_LENGTH (25)
#ifdef ISP2401
-#define DBG_EXT_CMD_TRACE_PNTS_DUMP (1 << 8)
-#define DBG_EXT_CMD_PUB_CFG_DUMP (1 << 9)
-#define DBG_EXT_CMD_GAC_REG_DUMP (1 << 10)
-#define DBG_EXT_CMD_GAC_ACB_REG_DUMP (1 << 11)
-#define DBG_EXT_CMD_FIFO_DUMP (1 << 12)
-#define DBG_EXT_CMD_QUEUE_DUMP (1 << 13)
-#define DBG_EXT_CMD_DMA_DUMP (1 << 14)
+#define DBG_EXT_CMD_TRACE_PNTS_DUMP BIT(8)
+#define DBG_EXT_CMD_PUB_CFG_DUMP BIT(9)
+#define DBG_EXT_CMD_GAC_REG_DUMP BIT(10)
+#define DBG_EXT_CMD_GAC_ACB_REG_DUMP BIT(11)
+#define DBG_EXT_CMD_FIFO_DUMP BIT(12)
+#define DBG_EXT_CMD_QUEUE_DUMP BIT(13)
+#define DBG_EXT_CMD_DMA_DUMP BIT(14)
#define DBG_EXT_CMD_MASK 0xAB0000CD
#endif
/* [IA_CSS_PIPE_ID_ACC] =*/ "accelerator"
};
-static char dot_id_input_bin[SH_CSS_MAX_BINARY_NAME+10];
+static char dot_id_input_bin[SH_CSS_MAX_BINARY_NAME + 10];
static char ring_buffer[200];
void ia_css_debug_dtrace(unsigned int level, const char *fmt, ...)
static void debug_dump_long_array_formatted(
const sp_ID_t sp_id,
hrt_address stack_sp_addr,
- unsigned stack_size)
+ unsigned int stack_size)
{
unsigned int i;
- uint32_t val;
- uint32_t addr = (uint32_t) stack_sp_addr;
- uint32_t stack_size_words = CEIL_DIV(stack_size, sizeof(uint32_t));
+ u32 val;
+ u32 addr = (uint32_t)stack_sp_addr;
+ u32 stack_size_words = CEIL_DIV(stack_size, sizeof(uint32_t));
/* When size is not multiple of four, last word is only relevant for
* remaining bytes */
for (i = 0; i < stack_size_words; i++) {
val = sp_dmem_load_uint32(sp_id, (hrt_address)addr);
- if ((i%8) == 0)
+ if ((i % 8) == 0)
ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\n");
ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "0x%08x ", val);
const struct ia_css_fw_info *fw;
unsigned int HIVE_ADDR_sp_threads_stack;
unsigned int HIVE_ADDR_sp_threads_stack_size;
- uint32_t stack_sizes[MAX_THREAD_NUM];
- uint32_t stack_sp_addr[MAX_THREAD_NUM];
+ u32 stack_sizes[MAX_THREAD_NUM];
+ u32 stack_sp_addr[MAX_THREAD_NUM];
unsigned int i;
fw = &sh_css_sp_fw;
fw->info.sp.threads_stack_size == 0)
return;
- (void) HIVE_ADDR_sp_threads_stack;
- (void) HIVE_ADDR_sp_threads_stack_size;
+ (void)HIVE_ADDR_sp_threads_stack;
+ (void)HIVE_ADDR_sp_threads_stack_size;
sp_dmem_load(sp_id,
(unsigned int)sp_address_of(sp_threads_stack),
debug_dump_sp_stack_info(SP0_ID);
}
-
void ia_css_debug_set_dtrace_level(const unsigned int trace_level)
{
ia_css_debug_trace_level = trace_level;
static const char *debug_frame_format2str(const enum ia_css_frame_format frame_format)
{
switch (frame_format) {
-
case IA_CSS_FRAME_FORMAT_NV11:
return "NV11";
case IA_CSS_FRAME_FORMAT_NV12:
static void debug_print_sp_state(const sp_state_t *state, const char *cell)
{
- assert(cell != NULL);
- assert(state != NULL);
+ assert(cell);
+ assert(state);
ia_css_debug_dtrace(2, "%s state:\n", cell);
ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc);
static void debug_print_isp_state(const isp_state_t *state, const char *cell)
{
- assert(state != NULL);
- assert(cell != NULL);
+ assert(state);
+ assert(cell);
ia_css_debug_dtrace(2, "%s state:\n", cell);
ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc);
{
sp_state_t state;
sp_stall_t stall;
+
sp_get_state(SP0_ID, &state, &stall);
debug_print_sp_state(&state, "SP");
if (state.is_stalling) {
static void debug_print_fifo_channel_state(const fifo_channel_state_t *state,
const char *descr)
{
- assert(state != NULL);
- assert(descr != NULL);
+ assert(state);
+ assert(descr);
ia_css_debug_dtrace(2, "FIFO channel: %s\n", descr);
ia_css_debug_dtrace(2, "\t%-32s: %d\n", "source valid",
void ia_css_debug_dump_pif_a_isp_fifo_state(void)
{
fifo_channel_state_t pif_to_isp, isp_to_pif;
+
fifo_channel_get_state(FIFO_MONITOR0_ID,
FIFO_CHANNEL_IF0_TO_ISP0, &pif_to_isp);
fifo_channel_get_state(FIFO_MONITOR0_ID,
void ia_css_debug_dump_pif_b_isp_fifo_state(void)
{
fifo_channel_state_t pif_to_isp, isp_to_pif;
+
fifo_channel_get_state(FIFO_MONITOR0_ID,
FIFO_CHANNEL_IF1_TO_ISP0, &pif_to_isp);
fifo_channel_get_state(FIFO_MONITOR0_ID,
void ia_css_debug_dump_str2mem_sp_fifo_state(void)
{
fifo_channel_state_t s2m_to_sp, sp_to_s2m;
+
fifo_channel_get_state(FIFO_MONITOR0_ID,
FIFO_CHANNEL_STREAM2MEM0_TO_SP0, &s2m_to_sp);
fifo_channel_get_state(FIFO_MONITOR0_ID,
int st_allow_fifo_overflow = state->allow_fifo_overflow;
int st_block_fifo_when_no_req = state->block_fifo_when_no_req;
- assert(state != NULL);
+ assert(state);
ia_css_debug_dtrace(2, "InputFormatter State (%s):\n", id);
ia_css_debug_dtrace(2, "\tConfiguration:\n");
state.write_width);
for (i = 0; i < HIVE_ISP_NUM_DMA_CONNS; i++) {
- dma_port_state_t *port = &(state.port_states[i]);
+ dma_port_state_t *port = &state.port_states[i];
+
ia_css_debug_dtrace(2, "\tDMA device interface %d\n", i);
ia_css_debug_dtrace(2, "\t\tDMA internal side state\n");
ia_css_debug_dtrace(2,
}
for (i = 0; i < HIVE_DMA_NUM_CHANNELS; i++) {
- dma_channel_state_t *ch = &(state.channel_states[i]);
+ dma_channel_state_t *ch = &state.channel_states[i];
+
ia_css_debug_dtrace(2, "\t%-32s: %d\n", "DMA channel register",
i);
ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Connection",
void ia_css_debug_dump_dma_sp_fifo_state(void)
{
fifo_channel_state_t dma_to_sp, sp_to_dma;
+
fifo_channel_get_state(FIFO_MONITOR0_ID,
FIFO_CHANNEL_DMA0_TO_SP0, &dma_to_sp);
fifo_channel_get_state(FIFO_MONITOR0_ID,
void ia_css_debug_dump_dma_isp_fifo_state(void)
{
fifo_channel_state_t dma_to_isp, isp_to_dma;
+
fifo_channel_get_state(FIFO_MONITOR0_ID,
FIFO_CHANNEL_DMA0_TO_ISP0, &dma_to_isp);
fifo_channel_get_state(FIFO_MONITOR0_ID,
void ia_css_debug_dump_isp_sp_fifo_state(void)
{
fifo_channel_state_t sp_to_isp, isp_to_sp;
+
fifo_channel_get_state(FIFO_MONITOR0_ID,
FIFO_CHANNEL_SP0_TO_ISP0, &sp_to_isp);
fifo_channel_get_state(FIFO_MONITOR0_ID,
{
int i;
fifo_monitor_state_t state;
+
fifo_monitor_get_state(FIFO_MONITOR0_ID, &state);
for (i = 0; i < N_FIFO_CHANNEL; i++)
- debug_print_fifo_channel_state(&(state.fifo_channels[i]),
+ debug_print_fifo_channel_state(&state.fifo_channels[i],
"squepfstqkt");
return;
}
static void debug_binary_info_print(const struct ia_css_binary_xinfo *info)
{
- assert(info != NULL);
+ assert(info);
ia_css_debug_dtrace(2, "id = %d\n", info->sp.id);
ia_css_debug_dtrace(2, "mode = %d\n", info->sp.pipeline.mode);
ia_css_debug_dtrace(2, "max_input_width = %d\n", info->sp.input.max_width);
void ia_css_debug_binary_print(const struct ia_css_binary *bi)
{
unsigned int i;
+
debug_binary_info_print(bi->info);
ia_css_debug_dtrace(2,
"input: %dx%d, format = %d, padded width = %d\n",
{
char *data = NULL;
- assert(frame != NULL);
- assert(descr != NULL);
+ assert(frame);
+ assert(descr);
data = (char *)HOST_ADDRESS(frame->data);
ia_css_debug_dtrace(2, "frame %s (%p):\n", descr, frame);
void ia_css_debug_print_sp_debug_state(const struct sh_css_sp_debug_state
*state)
{
-
#endif
#if SP_DEBUG == SP_DEBUG_DUMP
- assert(state != NULL);
+ assert(state);
ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
"current SP software counter: %d\n",
state->debug[0]);
int sp_index = state->index;
int n;
- assert(state != NULL);
+ assert(state);
if (sp_index < last_index) {
/* SP has been reset */
last_index = 0;
if (last_index == 0) {
ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
- "copy-trace init: sp_dbg_if_start_line=%d, "
- "sp_dbg_if_start_column=%d, "
- "sp_dbg_if_cropped_height=%d, "
- "sp_debg_if_cropped_width=%d\n",
+ "copy-trace init: sp_dbg_if_start_line=%d, sp_dbg_if_start_column=%d, sp_dbg_if_cropped_height=%d, sp_debg_if_cropped_width=%d\n",
state->if_start_line,
state->if_start_column,
state->if_cropped_height,
for (n = last_index; n < sp_index; n++) {
int i = n % SH_CSS_SP_DBG_TRACE_DEPTH;
+
if (state->trace[i].frame != 0) {
ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
- "copy-trace: frame=%d, line=%d, "
- "pixel_distance=%d, "
- "mipi_used_dword=%d, "
- "sp_index=%d\n",
+ "copy-trace: frame=%d, line=%d, pixel_distance=%d, mipi_used_dword=%d, sp_index=%d\n",
state->trace[i].frame,
state->trace[i].line,
state->trace[i].pixel_distance,
static int host_index_last[SH_CSS_SP_DBG_NR_OF_TRACES] = { 0 };
int t, n;
- assert(state != NULL);
+ assert(state);
for (t = 0; t < SH_CSS_SP_DBG_NR_OF_TRACES; t++) {
int sp_index_last = state->index_last[t];
/* last index can be multiple rounds behind */
/* while trace size is only SH_CSS_SP_DBG_TRACE_DEPTH */
ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
- "Warning: trace %s has gap of %d "
- "traces\n",
+ "Warning: trace %s has gap of %d traces\n",
trace_name[t],
(sp_index_last -
(host_index_last[t] +
if (ts) {
ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
- "%05d trace=%s, file=%s:%d, "
- "data=0x%08x\n",
+ "%05d trace=%s, file=%s:%d, data=0x%08x\n",
ts,
trace_name[t],
id2filename[fid], l,
int limit = SH_CSS_NUM_SP_DEBUG;
int step = 1;
- assert(state != NULL);
+ assert(state);
for (i = base; i < limit; i += step) {
ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
int i;
unsigned int bits, infos;
- assert(state != NULL);
+ assert(state);
bits = state->irq_status;
infos = ia_css_isys_rx_translate_irq_infos(bits);
{
int i;
- assert(state != NULL);
+ assert(state);
ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
"compression_scheme0", state->comp_scheme0);
{
int i;
- assert(state != NULL);
+ assert(state);
ia_css_debug_dtrace(2, "CSI Receiver State:\n");
ia_css_debug_dtrace(2, "\tConfiguration:\n");
#if defined(USE_INPUT_SYSTEM_VERSION_2)
static void debug_print_isys_capture_unit_state(capture_unit_state_t *state)
{
- assert(state != NULL);
+ assert(state);
ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
"Packet_Length", state->Packet_Length);
static void debug_print_isys_acquisition_unit_state(
acquisition_unit_state_t *state)
{
- assert(state != NULL);
+ assert(state);
ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
"Received_Short_Packets",
static void debug_print_isys_ctrl_unit_state(ctrl_unit_state_t *state)
{
- assert(state != NULL);
+ assert(state);
ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "last_cmd", state->last_cmd);
ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "next_cmd", state->next_cmd);
{
int i;
- assert(state != NULL);
+ assert(state);
ia_css_debug_dtrace(2, "InputSystem State:\n");
/* configuration */
void ia_css_debug_dump_debug_info(const char *context)
{
- if (context == NULL)
+ if (!context)
context = "No Context provided";
ia_css_debug_dtrace(2, "CSS Debug Info dump [Context = %s]\n", context);
{
irq_controller_state_t state;
+
irq_controller_get_state(IRQ2_ID, &state);
ia_css_debug_dtrace(2, "\t%-32s:\n",
sp_dmem_store_uint32(SP0_ID,
(unsigned int)sp_address_of(sp_sleep_mode),
- (uint32_t) mode);
+ (uint32_t)mode);
}
void ia_css_debug_wake_up_sp(void)
findf_dmem_params(struct ia_css_stream *stream, short idx)
{
int i;
+
for (i = 0; i < stream->num_pipes; i++) {
struct ia_css_pipe *pipe = stream->pipes[i];
struct ia_css_pipeline *pipeline = ia_css_pipe_get_pipeline(pipe);
struct ia_css_pipeline_stage *stage;
+
for (stage = pipeline->stages; stage; stage = stage->next) {
struct ia_css_binary *binary = stage->binary;
short *offsets = (short *)&binary->info->mem_offsets.offsets.param->dmem;
(void)stream;
#else
- assert(stream != NULL);
+ assert(stream);
if ((enable & IA_CSS_DEBUG_DUMP_FPN)
|| (enable & IA_CSS_DEBUG_DUMP_ALL)) {
ia_css_fpn_dump(FIND_DMEM_PARAMS(stream, fpn), IA_CSS_DEBUG_VERBOSE);
{
const struct ia_css_fw_info *fw;
unsigned int HIVE_ADDR_raw_copy_line_count;
- int32_t raw_copy_line_count;
- static int32_t prev_raw_copy_line_count = -1;
+ s32 raw_copy_line_count;
+ static s32 prev_raw_copy_line_count = -1;
fw = &sh_css_sp_fw;
HIVE_ADDR_raw_copy_line_count =
/* only indicate if copy loop is active */
if (reduced)
- raw_copy_line_count = (raw_copy_line_count < 0)?raw_copy_line_count:1;
+ raw_copy_line_count = (raw_copy_line_count < 0) ? raw_copy_line_count : 1;
/* do the handling */
if (prev_raw_copy_line_count != raw_copy_line_count) {
ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
- "sh_css_dump_sp_raw_copy_linecount() "
- "line_count=%d\n",
+ "sh_css_dump_sp_raw_copy_linecount() line_count=%d\n",
raw_copy_line_count);
prev_raw_copy_line_count = raw_copy_line_count;
}
{
const struct ia_css_fw_info *fw;
unsigned int HIVE_ADDR_pipeline_sp_curr_binary_id;
- uint32_t curr_binary_id;
- static uint32_t prev_binary_id = 0xFFFFFFFF;
- static uint32_t sample_count;
+ u32 curr_binary_id;
+ static u32 prev_binary_id = 0xFFFFFFFF;
+ static u32 sample_count;
fw = &sh_css_sp_fw;
HIVE_ADDR_pipeline_sp_curr_binary_id = fw->info.sp.curr_binary_id;
sample_count++;
if (prev_binary_id != curr_binary_id) {
ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
- "sh_css_dump_isp_binary() "
- "pipe_id=%d, binary_id=%d, sample_count=%d\n",
+ "sh_css_dump_isp_binary() pipe_id=%d, binary_id=%d, sample_count=%d\n",
(curr_binary_id >> 16),
(curr_binary_id & 0x0ffff),
sample_count);
const struct ia_css_fw_info *fw;
int i;
unsigned int HIVE_ADDR_ia_css_isys_sp_error_cnt;
- int32_t ia_css_sp_input_system_error_cnt[N_MIPI_PORT_ID + 1]; /* 3 Capture Units and 1 Acquire Unit. */
+ s32 ia_css_sp_input_system_error_cnt[N_MIPI_PORT_ID + 1]; /* 3 Capture Units and 1 Acquire Unit. */
ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "Input System Error Counters:\n");
bool ia_css_debug_mode_init(void)
{
bool rc;
+
rc = sh_css_sp_init_dma_sw_reg(0);
return rc;
}
{
va_list ap;
- assert(fmt != NULL);
+ assert(fmt);
va_start(ap, fmt);
ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_START);
ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_END);
va_end(ap);
}
+
#ifdef HAS_WATCHDOG_SP_THREAD_DEBUG
void sh_css_dump_thread_wait_info(void)
{
const struct ia_css_fw_info *fw;
int i;
unsigned int HIVE_ADDR_sp_thread_wait;
- int32_t sp_thread_wait[MAX_THREAD_NUM];
+ s32 sp_thread_wait[MAX_THREAD_NUM];
+
ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "SEM WAITS:\n");
fw = &sh_css_sp_fw;
"\twait[%d] = 0x%X\n",
i, sp_thread_wait[i]);
}
-
}
void sh_css_dump_pipe_stage_info(void)
const struct ia_css_fw_info *fw;
int i;
unsigned int HIVE_ADDR_sp_pipe_stage;
- int32_t sp_pipe_stage[MAX_THREAD_NUM];
+ s32 sp_pipe_stage[MAX_THREAD_NUM];
+
ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "PIPE STAGE:\n");
fw = &sh_css_sp_fw;
"\tstage[%d] = %d\n",
i, sp_pipe_stage[i]);
}
-
}
void sh_css_dump_pipe_stripe_info(void)
const struct ia_css_fw_info *fw;
int i;
unsigned int HIVE_ADDR_sp_pipe_stripe;
- int32_t sp_pipe_stripe[MAX_THREAD_NUM];
+ s32 sp_pipe_stripe[MAX_THREAD_NUM];
+
ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "PIPE STRIPE:\n");
fw = &sh_css_sp_fw;
"\tstripe[%d] = %d\n",
i, sp_pipe_stripe[i]);
}
-
}
#endif
queue_id_to_str[frame->dynamic_queue_id]);
}
dtrace_dot(
- "node [shape = box, "
- "fixedsize=true, width=2, height=0.7]; \"%p\" "
- "[label = \"%s\\n%d(%d) x %d, %dbpp\\n%s\"];",
+ "node [shape = box, fixedsize=true, width=2, height=0.7]; \"%p\" [label = \"%s\\n%d(%d) x %d, %dbpp\\n%s\"];",
frame,
debug_frame_format2str(frame->info.format),
frame->info.res.width,
if (in_frame) {
dtrace_dot(
- "\"%p\"->\"%s(pipe%d)\" "
- "[label = %s_frame];",
+ "\"%p\"->\"%s(pipe%d)\" [label = %s_frame];",
frame,
blob_name, id, frame_name);
} else {
dtrace_dot(
- "\"%s(pipe%d)\"->\"%p\" "
- "[label = %s_frame];",
+ "\"%s(pipe%d)\"->\"%p\" [label = %s_frame];",
blob_name, id,
frame,
frame_name);
dtrace_dot("rankdir=LR;");
dtrace_dot("fontsize=9;");
- dtrace_dot("label = \"\\nEnable options: rp=reduced pipe, vfve=vf_veceven, "
- "dvse=dvs_envelope, dvs6=dvs_6axis, bo=block_out, "
- "fbds=fixed_bayer_ds, bf6=bayer_fir_6db, "
- "rawb=raw_binning, cont=continuous, disc=dis_crop\\n"
- "dp2a=dp_2adjacent, outp=output, outt=out_table, "
- "reff=ref_frame, par=params, gam=gamma, "
- "cagdc=ca_gdc, ispa=isp_addresses, inf=in_frame, "
- "outf=out_frame, hs=high_speed, inpc=input_chunking\"");
+ dtrace_dot("label = \"\\nEnable options: rp=reduced pipe, vfve=vf_veceven, dvse=dvs_envelope, dvs6=dvs_6axis, bo=block_out, fbds=fixed_bayer_ds, bf6=bayer_fir_6db, rawb=raw_binning, cont=continuous, disc=dis_crop\\n"
+ "dp2a=dp_2adjacent, outp=output, outt=out_table, reff=ref_frame, par=params, gam=gamma, cagdc=ca_gdc, ispa=isp_addresses, inf=in_frame, outf=out_frame, hs=high_speed, inpc=input_chunking\"");
}
void ia_css_debug_pipe_graph_dump_epilogue(void)
{
-
if (strlen(ring_buffer) > 0) {
dtrace_dot(ring_buffer);
}
-
if (pg_inst.stream_format != N_ATOMISP_INPUT_FORMAT) {
/* An input stream format has been set so assume we have
* an input system and sensor
*/
-
dtrace_dot(
- "node [shape = doublecircle, "
- "fixedsize=true, width=2.5]; \"input_system\" "
- "[label = \"Input system\"];");
+ "node [shape = doublecircle, fixedsize=true, width=2.5]; \"input_system\" [label = \"Input system\"];");
dtrace_dot(
- "\"input_system\"->\"%s\" "
- "[label = \"%s\"];",
+ "\"input_system\"->\"%s\" [label = \"%s\"];",
dot_id_input_bin, debug_stream_format2str(pg_inst.stream_format));
dtrace_dot(
- "node [shape = doublecircle, "
- "fixedsize=true, width=2.5]; \"sensor\" "
- "[label = \"Sensor\"];");
+ "node [shape = doublecircle, fixedsize=true, width=2.5]; \"sensor\" [label = \"Sensor\"];");
dtrace_dot(
- "\"sensor\"->\"input_system\" "
- "[label = \"%s\\n%d x %d\\n(%d x %d)\"];",
+ "\"sensor\"->\"input_system\" [label = \"%s\\n%d x %d\\n(%d x %d)\"];",
debug_stream_format2str(pg_inst.stream_format),
pg_inst.width, pg_inst.height,
pg_inst.eff_width, pg_inst.eff_height);
struct ia_css_pipeline_stage *stage,
enum ia_css_pipe_id id)
{
- char blob_name[SH_CSS_MAX_BINARY_NAME+10] = "<unknown type>";
+ char blob_name[SH_CSS_MAX_BINARY_NAME + 10] = "<unknown type>";
char const *bin_type = "<unknown type>";
int i;
- assert(stage != NULL);
+ assert(stage);
if (stage->sp_func != IA_CSS_PIPELINE_NO_FUNC)
return;
}
/* Guard in case of binaries that don't have any binary_info */
- if (stage->binary_info != NULL) {
+ if (stage->binary_info) {
char enable_info1[100];
char enable_info2[100];
char enable_info3[100];
l = strlen(ei);
/* Replace last ',' with \0 if present */
- if (l && enable_info[l-1] == ',')
+ if (l && enable_info[l - 1] == ',')
enable_info[--l] = '\0';
if (l > ENABLE_LINE_MAX_LENGTH) {
ei, p);
enable_info1[p] = '\0';
- ei += p+1;
+ ei += p + 1;
l = strlen(ei);
if (l <= ENABLE_LINE_MAX_LENGTH) {
sizeof(enable_info2),
ei, p);
enable_info2[p] = '\0';
- ei += p+1;
+ ei += p + 1;
l = strlen(ei);
if (l <= ENABLE_LINE_MAX_LENGTH) {
sizeof(enable_info3),
ei, p);
enable_info3[p] = '\0';
- ei += p+1;
+ ei += p + 1;
strcpy_s(enable_info3,
sizeof(enable_info3), ei);
snprintf(enable_info, sizeof(enable_info),
}
}
- dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, "
- "label=\"%s\\n%s\\n\\n%s\"]; \"%s(pipe%d)\"",
+ dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, label=\"%s\\n%s\\n\\n%s\"]; \"%s(pipe%d)\"",
bin_type, blob_name, enable_info, blob_name, id);
-
- }
- else {
- dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, "
- "label=\"%s\\n%s\\n\"]; \"%s(pipe%d)\"",
+ } else {
+ dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, label=\"%s\\n%s\\n\"]; \"%s(pipe%d)\"",
bin_type, blob_name, blob_name, id);
}
ia_css_debug_pipe_graph_dump_sp_raw_copy(
struct ia_css_frame *out_frame)
{
- assert(out_frame != NULL);
+ assert(out_frame);
if (pg_inst.do_init) {
ia_css_debug_pipe_graph_dump_prologue();
pg_inst.do_init = false;
}
- dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, "
- "label=\"%s\\n%s\"]; \"%s(pipe%d)\"",
+ dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, label=\"%s\\n%s\"]; \"%s(pipe%d)\"",
"sp-binary", "sp_raw_copy", "sp_raw_copy", 1);
snprintf(ring_buffer, sizeof(ring_buffer),
- "node [shape = box, "
- "fixedsize=true, width=2, height=0.7]; \"%p\" "
- "[label = \"%s\\n%d(%d) x %d\\nRingbuffer\"];",
+ "node [shape = box, fixedsize=true, width=2, height=0.7]; \"%p\" [label = \"%s\\n%d(%d) x %d\\nRingbuffer\"];",
out_frame,
debug_frame_format2str(out_frame->info.format),
out_frame->info.res.width,
dtrace_dot(ring_buffer);
dtrace_dot(
- "\"%s(pipe%d)\"->\"%p\" "
- "[label = out_frame];",
+ "\"%s(pipe%d)\"->\"%p\" [label = out_frame];",
"sp_raw_copy", 1, out_frame);
snprintf(dot_id_input_bin, sizeof(dot_id_input_bin), "%s(pipe%d)", "sp_raw_copy", 1);
#endif
{
#if defined(HAS_TRACER_V2)
- uint32_t start_addr;
- uint32_t start_addr_data;
- uint32_t item_size;
+ u32 start_addr;
+ u32 start_addr_data;
+ u32 item_size;
#ifndef ISP2401
- uint32_t tmp;
+ u32 tmp;
#else
- uint8_t tid_val;
+ u8 tid_val;
enum TRACE_DUMP_FORMAT dump_format;
#endif
int i, j, max_trace_points, point_num, limit = -1;
/* using a static buffer here as the driver has issues allocating memory */
- static uint32_t trace_read_buf[TRACE_BUFF_SIZE] = {0};
+ static u32 trace_read_buf[TRACE_BUFF_SIZE] = {0};
#ifdef ISP2401
static struct trace_header_t header;
- uint8_t *header_arr;
+ u8 *header_arr;
#endif
/* read the header and parse it */
return;
}
/* no overrun: start from 0 */
- if ((limit == point_num-1) || /* first 0 is at the end - border case */
- (trace_read_buf[limit+1] == 0)) /* did not make a full cycle after the memset */
+ if ((limit == point_num - 1) || /* first 0 is at the end - border case */
+ (trace_read_buf[limit + 1] == 0)) /* did not make a full cycle after the memset */
limit = 0;
/* overrun: limit is the first non-zero after the first zero */
else
ia_css_debug_dtrace(2, "\t tagger frame[%d]: exp_id=%d, marked=%d, locked=%d\n",
i, tbuf_frames[i].exp_id, tbuf_frames[i].mark, tbuf_frames[i].lock);
}
-
}
#endif /* defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) */
unsigned int pc;
unsigned int i;
hrt_data sc = sp_ctrl_load(id, SP_SC_REG);
+
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d Status reg: 0x%X\n", id, sc);
sc = sp_ctrl_load(id, SP_CTRL_SINK_REG);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d Stall reg: 0x%X\n", id, sc);
#include "sw_event_global.h" /*event macros.TODO : Change File Name..???*/
bool ia_css_event_encode(
- uint8_t *in,
- uint8_t nr,
+ u8 *in,
+ u8 nr,
uint32_t *out);
void ia_css_event_decode(
- uint32_t event,
+ u32 event,
uint8_t *payload);
#endif /*_IA_CSS_EVENT_H*/
* Refer to "sw_event_public.h" for details.
*/
bool ia_css_event_encode(
- uint8_t *in,
- uint8_t nr,
+ u8 *in,
+ u8 nr,
uint32_t *out)
{
bool ret;
- uint32_t nr_of_bits;
- uint32_t i;
- assert(in != NULL);
- assert(out != NULL);
+ u32 nr_of_bits;
+ u32 i;
+
+ assert(in);
+ assert(out);
OP___assert(nr > 0 && nr <= MAX_NR_OF_PAYLOADS_PER_SW_EVENT);
/* initialize the output */
}
void ia_css_event_decode(
- uint32_t event,
+ u32 event,
uint8_t *payload)
{
assert(payload[1] == 0);
*/
int ia_css_eventq_send(
ia_css_queue_t *eventq_handle,
- uint8_t evt_id,
- uint8_t evt_payload_0,
- uint8_t evt_payload_1,
+ u8 evt_id,
+ u8 evt_payload_0,
+ u8 evt_payload_1,
uint8_t evt_payload_2);
#endif /* _IA_CSS_EVENTQ_H */
ia_css_queue_t *eventq_handle,
uint8_t *payload)
{
- uint32_t sp_event;
+ u32 sp_event;
int error;
/* dequeue the IRQ event */
*/
int ia_css_eventq_send(
ia_css_queue_t *eventq_handle,
- uint8_t evt_id,
- uint8_t evt_payload_0,
- uint8_t evt_payload_1,
+ u8 evt_id,
+ u8 evt_payload_0,
+ u8 evt_payload_1,
uint8_t evt_payload_2)
{
- uint8_t tmp[4];
- uint32_t sw_event;
+ u8 tmp[4];
+ u32 sw_event;
int error = ENOSYS;
/*
/* queue the software event (busy-waiting) */
for ( ; ; ) {
error = ia_css_queue_enqueue(eventq_handle, sw_event);
- if (ENOBUFS != error) {
+ if (error != ENOBUFS) {
/* We were able to successfully send the event
or had a real failure. return the status*/
break;
};
struct ia_css_sp_resolution {
- uint16_t width; /* width of valid data in pixels */
- uint16_t height; /* Height of valid data in lines */
+ u16 width; /* width of valid data in pixels */
+ u16 height; /* Height of valid data in lines */
};
/*
*/
struct ia_css_frame_sp_info {
struct ia_css_sp_resolution res;
- uint16_t padded_width; /* stride of line in memory
+ u16 padded_width; /* stride of line in memory
(in pixels) */
unsigned char format; /* format of the frame data */
unsigned char raw_bit_depth; /* number of valid bits per pixel,
const struct ia_css_resolution *info);
#endif /*__IA_CSS_FRAME_COMM_H__*/
-
#include "sh_css_internal.h"
#include "memory_access.h"
-
#define NV12_TILEY_TILE_WIDTH 128
#define NV12_TILEY_TILE_HEIGHT 32
void ia_css_frame_zero(struct ia_css_frame *frame)
{
- assert(frame != NULL);
+ assert(frame);
mmgr_clear(frame->data, frame->data_bytes);
}
const struct ia_css_frame_info *info)
{
enum ia_css_err err = IA_CSS_SUCCESS;
- if (frame == NULL || info == NULL)
+
+ if (!frame || !info)
return IA_CSS_ERR_INVALID_ARGUMENTS;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_frame_allocate_from_info() enter:\n");
{
enum ia_css_err err = IA_CSS_SUCCESS;
- if (frame == NULL || width == 0 || height == 0)
+ if (!frame || width == 0 || height == 0)
return IA_CSS_ERR_INVALID_ARGUMENTS;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_frame_allocate() leave: frame=%p\n", *frame);
#else
- if ((*frame != NULL) && err == IA_CSS_SUCCESS)
+ if ((*frame) && err == IA_CSS_SUCCESS)
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_frame_allocate() leave: frame=%p, data(DDR address)=0x%x\n", *frame, (*frame)->data);
else
enum ia_css_err ia_css_frame_map(struct ia_css_frame **frame,
const struct ia_css_frame_info *info,
const void __user *data,
- uint16_t attribute,
+ u16 attribute,
void *context)
{
enum ia_css_err err = IA_CSS_SUCCESS;
struct ia_css_frame *me;
- assert(frame != NULL);
+
+ assert(frame);
/* Create the frame structure */
err = ia_css_frame_create_from_info(&me, info);
{
enum ia_css_err err = IA_CSS_SUCCESS;
struct ia_css_frame *me;
+
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_frame_create_from_info() enter:\n");
- if (frame == NULL || info == NULL) {
+ if (!frame || !info) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
- "ia_css_frame_create_from_info() leave:"
- " invalid arguments\n");
+ "ia_css_frame_create_from_info() leave: invalid arguments\n");
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
info->raw_bit_depth,
false,
false);
- if (me == NULL) {
+ if (!me) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
- "ia_css_frame_create_from_info() leave:"
- " frame create failed\n");
+ "ia_css_frame_create_from_info() leave: frame create failed\n");
return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
}
size_t data_bytes)
{
enum ia_css_err err = IA_CSS_SUCCESS;
+
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_frame_set_data() enter:\n");
- if (frame == NULL) {
+ if (!frame) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_frame_set_data() leave: NULL frame\n");
return IA_CSS_ERR_INVALID_ARGUMENTS;
const struct ia_css_frame_info *info)
{
enum ia_css_err err = IA_CSS_SUCCESS;
- assert(frame != NULL);
+
+ assert(frame);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_frame_allocate_contiguous_from_info() enter:\n");
err = ia_css_frame_allocate_contiguous(frame,
{
IA_CSS_ENTER_PRIVATE("frame = %p", frame);
- if (frame != NULL) {
+ if (frame) {
hmm_free(frame->data);
sh_css_free(frame);
}
enum ia_css_err ia_css_frame_check_info(const struct ia_css_frame_info *info)
{
- assert(info != NULL);
+ assert(info);
if (info->res.width == 0 || info->res.height == 0)
return IA_CSS_ERR_INVALID_ARGUMENTS;
return IA_CSS_SUCCESS;
enum ia_css_err ia_css_frame_init_planes(struct ia_css_frame *frame)
{
- assert(frame != NULL);
+ assert(frame);
switch (frame->info.format) {
case IA_CSS_FRAME_FORMAT_MIPI:
IA_CSS_ENTER_PRIVATE("info = %p,width = %d, minimum padded width = %d",
info, width, min_padded_width);
- if (info == NULL) {
+ if (!info) {
IA_CSS_ERROR("NULL input parameter");
IA_CSS_LEAVE_PRIVATE("");
return;
void ia_css_frame_info_set_format(struct ia_css_frame_info *info,
enum ia_css_frame_format format)
{
- assert(info != NULL);
+ assert(info);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_frame_info_set_format() enter:\n");
info->format = format;
{
IA_CSS_ENTER_PRIVATE("info = %p, width = %d, height = %d, format = %d, aligned = %d",
info, width, height, format, aligned);
- if (info == NULL) {
+ if (!info) {
IA_CSS_ERROR("NULL input parameter");
IA_CSS_LEAVE_PRIVATE("");
return;
struct ia_css_frame **frames_array)
{
unsigned int i;
+
for (i = 0; i < num_frames; i++) {
if (frames_array[i]) {
ia_css_frame_free(frames_array[i]);
IA_CSS_FRAME_FORMAT_NUM,/* Not valid format yet */
0, 0, contiguous, false);
- if (me == NULL)
+ if (!me)
return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
/* Get the data size */
struct dma_port_config *config,
const struct ia_css_frame_info *info)
{
- unsigned is_raw_packed = info->format == IA_CSS_FRAME_FORMAT_RAW_PACKED;
- unsigned bits_per_pixel = is_raw_packed ? info->raw_bit_depth : ia_css_elems_bytes_from_info(info)*8;
- unsigned pix_per_ddrword = HIVE_ISP_DDR_WORD_BITS / bits_per_pixel;
- unsigned words_per_line = CEIL_DIV(info->padded_width, pix_per_ddrword);
- unsigned elems_b = pix_per_ddrword;
+ unsigned int is_raw_packed = info->format == IA_CSS_FRAME_FORMAT_RAW_PACKED;
+ unsigned int bits_per_pixel = is_raw_packed ? info->raw_bit_depth : ia_css_elems_bytes_from_info(info) * 8;
+ unsigned int pix_per_ddrword = HIVE_ISP_DDR_WORD_BITS / bits_per_pixel;
+ unsigned int words_per_line = CEIL_DIV(info->padded_width, pix_per_ddrword);
+ unsigned int elems_b = pix_per_ddrword;
config->stride = HIVE_ISP_DDR_WORD_BYTES * words_per_line;
config->elems = (uint8_t)elems_b;
unsigned int bits_per_pixel)
{
unsigned int stride;
- assert(frame != NULL);
+
+ assert(frame);
stride = HIVE_ISP_DDR_WORD_BYTES *
CEIL_DIV(subpixels_per_line,
uv_width = 2 * (y_width / horizontal_decimation);
uv_height = y_height / vertical_decimation;
- if (IA_CSS_FRAME_FORMAT_NV12_TILEY == frame->info.format) {
+ if (frame->info.format == IA_CSS_FRAME_FORMAT_NV12_TILEY) {
y_width = CEIL_MUL(y_width, NV12_TILEY_TILE_WIDTH);
uv_width = CEIL_MUL(uv_width, NV12_TILEY_TILE_WIDTH);
y_height = CEIL_MUL(y_height, NV12_TILEY_TILE_HEIGHT);
contiguous,
true);
- if (me == NULL)
+ if (!me)
return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
err = ia_css_frame_init_planes(me);
{
struct ia_css_frame *me = sh_css_malloc(sizeof(*me));
- if (me == NULL)
+ if (!me)
return NULL;
memset(me, 0, sizeof(*me));
if (info->format == IA_CSS_FRAME_FORMAT_RAW
|| (info->format == IA_CSS_FRAME_FORMAT_RAW_PACKED)) {
if (info->raw_bit_depth)
- return CEIL_DIV(info->raw_bit_depth,8);
+ return CEIL_DIV(info->raw_bit_depth, 8);
else
return 2; /* bytes per pixel */
}
to->width = (uint16_t)from->width;
to->height = (uint16_t)from->height;
}
+
#ifdef ISP2401
enum ia_css_err
const struct ia_css_resolution *out_res,
struct ia_css_resolution *crop_res)
{
- uint32_t wd_even_ceil, ht_even_ceil;
- uint32_t in_ratio, out_ratio;
+ u32 wd_even_ceil, ht_even_ceil;
+ u32 in_ratio, out_ratio;
- if ((in_res == NULL) || (out_res == NULL) || (crop_res == NULL))
+ if ((!in_res) || (!out_res) || (!crop_res))
return IA_CSS_ERR_INVALID_ARGUMENTS;
IA_CSS_ENTER_PRIVATE("in(%ux%u) -> out(%ux%u)", in_res->width,
unsigned int ia_css_ifmtr_lines_needed_for_bayer_order(
const struct ia_css_stream_config *config)
{
- assert(config != NULL);
- if ((IA_CSS_BAYER_ORDER_BGGR == config->input_config.bayer_order)
- || (IA_CSS_BAYER_ORDER_GBRG == config->input_config.bayer_order))
+ assert(config);
+ if ((config->input_config.bayer_order == IA_CSS_BAYER_ORDER_BGGR)
+ || (config->input_config.bayer_order == IA_CSS_BAYER_ORDER_GBRG))
return 1;
return 0;
unsigned int ia_css_ifmtr_columns_needed_for_bayer_order(
const struct ia_css_stream_config *config)
{
- assert(config != NULL);
- if ((IA_CSS_BAYER_ORDER_RGGB == config->input_config.bayer_order)
- || (IA_CSS_BAYER_ORDER_GBRG == config->input_config.bayer_order))
+ assert(config);
+ if ((config->input_config.bayer_order == IA_CSS_BAYER_ORDER_RGGB)
+ || (config->input_config.bayer_order == IA_CSS_BAYER_ORDER_GBRG))
return 1;
return 0;
input_formatter_cfg_t if_a_config, if_b_config;
enum atomisp_input_format input_format;
enum ia_css_err err = IA_CSS_SUCCESS;
- uint8_t if_config_index;
+ u8 if_config_index;
/* Determine which input formatter config set is targeted. */
/* Index is equal to the CSI-2 port used. */
if (config->mode == IA_CSS_INPUT_MODE_SENSOR
|| config->mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) {
port = config->source.port.port;
- if_config_index = (uint8_t) (port - MIPI_PORT0_ID);
+ if_config_index = (uint8_t)(port - MIPI_PORT0_ID);
} else if (config->mode == IA_CSS_INPUT_MODE_MEMORY) {
if_config_index = SH_CSS_IF_CONFIG_NOT_NEEDED;
} else {
else
left_padding = binary->left_padding;
else
- left_padding = 2*ISP_VEC_NELEMS - config->left_padding;
-
+ left_padding = 2 * ISP_VEC_NELEMS - config->left_padding;
if (left_padding) {
num_vectors = CEIL_DIV(cropped_width + left_padding,
case ATOMISP_INPUT_FORMAT_RAW_12:
if (two_ppc) {
int crop_col = (start_column % 2) == 1;
+
vmem_increment = 2;
deinterleaving = 1;
width_a = width_b = cropped_width / 2;
if_b_config.block_no_reqs =
(config->mode != IA_CSS_INPUT_MODE_SENSOR);
- if (SH_CSS_IF_CONFIG_NOT_NEEDED != if_config_index) {
+ if (if_config_index != SH_CSS_IF_CONFIG_NOT_NEEDED) {
assert(if_config_index <= SH_CSS_MAX_IF_CONFIGS);
ifmtr_set_if_blocking_mode(&if_a_config, &if_b_config);
if_config_index);
}
} else {
- if (SH_CSS_IF_CONFIG_NOT_NEEDED != if_config_index) {
+ if (if_config_index != SH_CSS_IF_CONFIG_NOT_NEEDED) {
assert(if_config_index <= SH_CSS_MAX_IF_CONFIGS);
ifmtr_set_if_blocking_mode(&if_a_config, NULL);
{
int i;
bool block[] = { false, false, false, false };
+
assert(N_INPUT_FORMATTER_ID <= (ARRAY_SIZE(block)));
#if !defined(IS_ISP_2400_SYSTEM)
#endif
block[INPUT_FORMATTER0_ID] = (bool)config_a->block_no_reqs;
- if (NULL != config_b)
+ if (config_b)
block[INPUT_FORMATTER1_ID] = (bool)config_b->block_no_reqs;
/* TODO: next could cause issues when streams are started after
if (ifmtr_set_if_blocking_mode_reset) {
ifmtr_set_if_blocking_mode_reset = false;
for (i = 0; i < N_INPUT_FORMATTER_ID; i++) {
- input_formatter_ID_t id = (input_formatter_ID_t) i;
+ input_formatter_ID_t id = (input_formatter_ID_t)i;
+
input_formatter_rst(id);
input_formatter_set_fifo_blocking_mode(id, block[id]);
}
inputfifo_mipi_data_type_yuv420_legacy,
inputfifo_mipi_data_type_rgb,
};
+
#if !defined(HAS_NO_INPUT_SYSTEM)
static unsigned int inputfifo_curr_ch_id, inputfifo_curr_fmt_type;
#endif
unsigned int fmt_type;
enum inputfifo_mipi_data_type type;
};
+
#if !defined(HAS_NO_INPUT_SYSTEM)
/*
* Maintain a basic streaming to Mipi administration with ch_id as index
inputfifo_inst_admin[INPUTFIFO_NR_OF_S2M_CHANNELS];
/* Streaming to MIPI */
-static unsigned inputfifo_wrap_marker(
+static unsigned int inputfifo_wrap_marker(
/* static inline unsigned inputfifo_wrap_marker( */
- unsigned marker)
+ unsigned int marker)
{
return marker |
(inputfifo_curr_ch_id << HIVE_STR_TO_MIPI_CH_ID_LSB) |
}
static inline void
-_sh_css_fifo_snd(unsigned token)
+_sh_css_fifo_snd(unsigned int token)
{
while (!can_event_send_token(STR2MIPI_EVENT_ID))
hrt_sleep();
return;
}
-
-
static void inputfifo_send_data_b(
/* static inline void inputfifo_send_data_b( */
unsigned int data)
return;
}
-
-
static void inputfifo_send_data(
/* static inline void inputfifo_send_data( */
unsigned int a,
return;
}
-
-
static void inputfifo_send_sol(void)
/* static inline void inputfifo_send_sol(void) */
{
return;
}
-
-
static void inputfifo_send_eol(void)
/* static inline void inputfifo_send_eol(void) */
{
return;
}
-
-
static void inputfifo_send_sof(void)
/* static inline void inputfifo_send_sof(void) */
{
return;
}
-
-
static void inputfifo_send_eof(void)
/* static inline void inputfifo_send_eof(void) */
{
return;
}
-
-
#ifdef __ON__
static void inputfifo_send_ch_id(
/* static inline void inputfifo_send_ch_id( */
unsigned int ch_id)
{
hrt_data token;
+
inputfifo_curr_ch_id = ch_id & _HIVE_ISP_CH_ID_MASK;
/* we send an zero marker, this will wrap the ch_id and
* fmt_type automatically.
unsigned int fmt_type)
{
hrt_data token;
+
inputfifo_curr_fmt_type = fmt_type & _HIVE_ISP_FMT_TYPE_MASK;
/* we send an zero marker, this will wrap the ch_id and
* fmt_type automatically.
}
#endif /* __ON__ */
-
-
static void inputfifo_send_ch_id_and_fmt_type(
/* static inline
void inputfifo_send_ch_id_and_fmt_type( */
unsigned int fmt_type)
{
hrt_data token;
+
inputfifo_curr_ch_id = ch_id & _HIVE_ISP_CH_ID_MASK;
inputfifo_curr_fmt_type = fmt_type & _HIVE_ISP_FMT_TYPE_MASK;
/* we send an zero marker, this will wrap the ch_id and
return;
}
-
-
static void inputfifo_send_empty_token(void)
/* static inline void inputfifo_send_empty_token(void) */
{
hrt_data token = inputfifo_wrap_marker(0);
+
_sh_css_fifo_snd(token);
return;
}
-
-
static void inputfifo_start_frame(
/* static inline void inputfifo_start_frame( */
unsigned int ch_id,
return;
}
-
-
static void inputfifo_end_frame(
unsigned int marker_cycles)
{
unsigned int i;
+
for (i = 0; i < marker_cycles; i++)
inputfifo_send_empty_token();
inputfifo_send_eof();
return;
}
-
-
static void inputfifo_send_line2(
const unsigned short *data,
unsigned int width,
{
unsigned int i, is_rgb = 0, is_legacy = 0;
- assert(data != NULL);
- assert((data2 != NULL) || (width2 == 0));
+ assert(data);
+ assert((data2) || (width2 == 0));
if (type == inputfifo_mipi_data_type_rgb)
is_rgb = 1;
* we only send 1 pixel, to data[0].
*/
unsigned int send_two_pixels = two_ppc;
+
if ((is_rgb || is_legacy) && (i % 3 == 2))
send_two_pixels = 0;
if (send_two_pixels) {
* we only send 1 pixel, to data2[0].
*/
unsigned int send_two_pixels = two_ppc;
+
if ((is_rgb || is_legacy) && (i % 3 == 2))
send_two_pixels = 0;
if (send_two_pixels) {
return;
}
-
-
static void
inputfifo_send_line(const unsigned short *data,
unsigned int width,
unsigned int two_ppc,
enum inputfifo_mipi_data_type type)
{
- assert(data != NULL);
+ assert(data);
inputfifo_send_line2(data, width, NULL, 0,
hblank_cycles,
marker_cycles,
type);
}
-
/* Send a frame of data into the input network via the GP FIFO.
* Parameters:
* - data: array of 16 bit values that contains all data for the frame.
{
unsigned int i;
- assert(data != NULL);
+ assert(data);
inputfifo_start_frame(ch_id, fmt_type);
for (i = 0; i < height; i++) {
return;
}
-
-
static enum inputfifo_mipi_data_type inputfifo_determine_type(
enum atomisp_input_format input_format)
{
return type;
}
-
-
static struct inputfifo_instance *inputfifo_get_inst(
unsigned int ch_id)
{
unsigned int fmt_type, hblank_cycles, marker_cycles;
enum inputfifo_mipi_data_type type;
- assert(data != NULL);
+ assert(data);
hblank_cycles = HBLANK_CYCLES;
marker_cycles = MARKER_CYCLES;
ia_css_isys_convert_stream_format_to_mipi_format(input_format,
two_ppc, type);
}
-
-
void ia_css_inputfifo_start_frame(
unsigned int ch_id,
enum atomisp_input_format input_format,
bool two_ppc)
{
struct inputfifo_instance *s2mi;
+
s2mi = inputfifo_get_inst(ch_id);
s2mi->ch_id = ch_id;
return;
}
-
-
void ia_css_inputfifo_send_line(
unsigned int ch_id,
const unsigned short *data,
{
struct inputfifo_instance *s2mi;
- assert(data != NULL);
- assert((data2 != NULL) || (width2 == 0));
+ assert(data);
+ assert((data2) || (width2 == 0));
s2mi = inputfifo_get_inst(ch_id);
-
/* Set global variables that indicate channel_id and format_type */
inputfifo_curr_ch_id = (s2mi->ch_id) & _HIVE_ISP_CH_ID_MASK;
inputfifo_curr_fmt_type = (s2mi->fmt_type) & _HIVE_ISP_FMT_TYPE_MASK;
s2mi->type);
}
-
void ia_css_inputfifo_send_embedded_line(
unsigned int ch_id,
enum atomisp_input_format data_type,
struct inputfifo_instance *s2mi;
unsigned int fmt_type;
- assert(data != NULL);
+ assert(data);
s2mi = inputfifo_get_inst(ch_id);
ia_css_isys_convert_stream_format_to_mipi_format(data_type,
MIPI_PREDICTOR_NONE, &fmt_type);
s2mi->two_ppc, inputfifo_mipi_data_type_regular);
}
-
void ia_css_inputfifo_end_frame(
unsigned int ch_id)
{
struct inputfifo_instance *s2mi;
+
s2mi = inputfifo_get_inst(ch_id);
/* Set global variables that indicate channel_id and format_type */
struct ia_css_isp_param_isp_segments *mem_init,
enum ia_css_param_class pclass,
enum ia_css_isp_memories mem,
- uint32_t address, size_t size);
+ u32 address, size_t size);
/* Get functions for parameter memory descriptors */
const struct ia_css_host_data*
IA_CSS_PARAM_CLASS_FRAME = 3, /* Frame time parameters, like output buffer */
#endif
};
+
#define IA_CSS_NUM_PARAM_CLASSES (IA_CSS_PARAM_CLASS_STATE + 1)
/* ISP parameter descriptor */
struct ia_css_isp_parameter {
- uint32_t offset; /* Offset in isp_<mem>)parameters, etc. */
- uint32_t size; /* Disabled if 0 */
+ u32 offset; /* Offset in isp_<mem>)parameters, etc. */
+ u32 size; /* Disabled if 0 */
};
-
/* Address/size of each parameter class in each isp memory, host memory pointers */
struct ia_css_isp_param_host_segments {
struct ia_css_host_data params[IA_CSS_NUM_PARAM_CLASSES][IA_CSS_NUM_MEMORIES];
/* Memory offsets in binary info */
struct ia_css_isp_param_memory_offsets {
- uint32_t offsets[IA_CSS_NUM_PARAM_CLASSES]; /** offset wrt hdr in bytes */
+ u32 offsets[IA_CSS_NUM_PARAM_CLASSES]; /** offset wrt hdr in bytes */
};
/* Offsets for ISP kernel parameters per isp memory.
};
#endif /* _IA_CSS_ISP_PARAM_TYPES_H_ */
-
struct ia_css_isp_param_isp_segments *mem_init,
enum ia_css_param_class pclass,
enum ia_css_isp_memories mem,
- uint32_t address, size_t size)
+ u32 address, size_t size)
{
mem_init->params[pclass][mem].address = address;
mem_init->params[pclass][mem].size = (uint32_t)size;
const struct ia_css_isp_param_host_segments *mem_params,
const struct ia_css_isp_param_css_segments *css_params)
{
- unsigned pclass, mem;
+ unsigned int pclass, mem;
+
for (pclass = 0; pclass < IA_CSS_NUM_PARAM_CLASSES; pclass++) {
memset(isp_mem_if->params[pclass], 0, sizeof(isp_mem_if->params[pclass]));
for (mem = 0; mem < IA_CSS_NUM_MEMORIES; mem++) {
const struct ia_css_isp_param_isp_segments *mem_initializers)
{
enum ia_css_err err = IA_CSS_SUCCESS;
- unsigned mem, pclass;
+ unsigned int mem, pclass;
pclass = IA_CSS_PARAM_CLASS_PARAM;
for (mem = 0; mem < IA_CSS_NUM_MEMORIES; mem++) {
for (pclass = 0; pclass < IA_CSS_NUM_PARAM_CLASSES; pclass++) {
- uint32_t size = 0;
+ u32 size = 0;
+
if (mem_initializers)
size = mem_initializers->params[pclass][mem].size;
mem_params->params[pclass][mem].size = size;
struct ia_css_isp_param_host_segments *mem_params,
struct ia_css_isp_param_css_segments *css_params)
{
- unsigned mem, pclass;
+ unsigned int mem, pclass;
for (mem = 0; mem < IA_CSS_NUM_MEMORIES; mem++) {
for (pclass = 0; pclass < IA_CSS_NUM_PARAM_CLASSES; pclass++) {
const struct ia_css_isp_param_memory_offsets *memory_offsets,
bool init)
{
- unsigned pclass;
+ unsigned int pclass;
+
for (pclass = 0; pclass < IA_CSS_NUM_PARAM_CLASSES; pclass++) {
mem_offsets->array[pclass].ptr = NULL;
if (init)
const struct ia_css_isp_param_host_segments *host,
enum ia_css_param_class pclass)
{
- unsigned mem;
+ unsigned int mem;
for (mem = 0; mem < N_IA_CSS_ISP_MEMORIES; mem++) {
size_t size = host->params[pclass][mem].size;
hrt_vaddress ddr_mem_ptr = ddr->params[pclass][mem].address;
char *host_mem_ptr = host->params[pclass][mem].address;
+
if (size != ddr->params[pclass][mem].size)
return IA_CSS_ERR_INTERNAL_ERROR;
if (!size)
*(uint32_t *)&mem_params->params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM0].address[dmem_offset] = 0x0;
}
-
-
/**
* Virtual Input System. (Input System 2401)
*/
-extern ia_css_isys_error_t ia_css_isys_stream_create(
+ia_css_isys_error_t ia_css_isys_stream_create(
ia_css_isys_descr_t *isys_stream_descr,
ia_css_isys_stream_h isys_stream,
uint32_t isys_stream_id);
-extern void ia_css_isys_stream_destroy(
+void ia_css_isys_stream_destroy(
ia_css_isys_stream_h isys_stream);
-extern ia_css_isys_error_t ia_css_isys_stream_calculate_cfg(
+ia_css_isys_error_t ia_css_isys_stream_calculate_cfg(
ia_css_isys_stream_h isys_stream,
ia_css_isys_descr_t *isys_stream_descr,
ia_css_isys_stream_cfg_t *isys_stream_cfg);
-extern void ia_css_isys_csi_rx_lut_rmgr_init(void);
+void ia_css_isys_csi_rx_lut_rmgr_init(void);
-extern void ia_css_isys_csi_rx_lut_rmgr_uninit(void);
+void ia_css_isys_csi_rx_lut_rmgr_uninit(void);
-extern bool ia_css_isys_csi_rx_lut_rmgr_acquire(
+bool ia_css_isys_csi_rx_lut_rmgr_acquire(
csi_rx_backend_ID_t backend,
csi_mipi_packet_type_t packet_type,
csi_rx_backend_lut_entry_t *entry);
-extern void ia_css_isys_csi_rx_lut_rmgr_release(
+void ia_css_isys_csi_rx_lut_rmgr_release(
csi_rx_backend_ID_t backend,
csi_mipi_packet_type_t packet_type,
csi_rx_backend_lut_entry_t *entry);
+void ia_css_isys_ibuf_rmgr_init(void);
-extern void ia_css_isys_ibuf_rmgr_init(void);
+void ia_css_isys_ibuf_rmgr_uninit(void);
-extern void ia_css_isys_ibuf_rmgr_uninit(void);
-
-extern bool ia_css_isys_ibuf_rmgr_acquire(
- uint32_t size,
+bool ia_css_isys_ibuf_rmgr_acquire(
+ u32 size,
uint32_t *start_addr);
-extern void ia_css_isys_ibuf_rmgr_release(
+void ia_css_isys_ibuf_rmgr_release(
uint32_t *start_addr);
-extern void ia_css_isys_dma_channel_rmgr_init(void);
+void ia_css_isys_dma_channel_rmgr_init(void);
-extern void ia_css_isys_dma_channel_rmgr_uninit(void);
+void ia_css_isys_dma_channel_rmgr_uninit(void);
-extern bool ia_css_isys_dma_channel_rmgr_acquire(
+bool ia_css_isys_dma_channel_rmgr_acquire(
isys2401_dma_ID_t dma_id,
isys2401_dma_channel *channel);
-extern void ia_css_isys_dma_channel_rmgr_release(
+void ia_css_isys_dma_channel_rmgr_release(
isys2401_dma_ID_t dma_id,
isys2401_dma_channel *channel);
-extern void ia_css_isys_stream2mmio_sid_rmgr_init(void);
+void ia_css_isys_stream2mmio_sid_rmgr_init(void);
-extern void ia_css_isys_stream2mmio_sid_rmgr_uninit(void);
+void ia_css_isys_stream2mmio_sid_rmgr_uninit(void);
-extern bool ia_css_isys_stream2mmio_sid_rmgr_acquire(
+bool ia_css_isys_stream2mmio_sid_rmgr_acquire(
stream2mmio_ID_t stream2mmio,
stream2mmio_sid_ID_t *sid);
-extern void ia_css_isys_stream2mmio_sid_rmgr_release(
+void ia_css_isys_stream2mmio_sid_rmgr_release(
stream2mmio_ID_t stream2mmio,
stream2mmio_sid_ID_t *sid);
typedef bool ia_css_isys_error_t;
static inline uint32_t ia_css_isys_generate_stream_id(
- uint32_t sp_thread_id,
+ u32 sp_thread_id,
uint32_t stream_id)
{
return sp_thread_id * IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH + stream_id;
csi_rx_backend_lut_entry_t *entry)
{
bool retval = false;
- uint32_t max_num_packets_of_type;
- uint32_t num_active_of_type;
+ u32 max_num_packets_of_type;
+ u32 num_active_of_type;
isys_csi_rx_rsrc_t *cur_rsrc = NULL;
- uint16_t i;
+ u16 i;
assert(backend < N_CSI_RX_BACKEND_ID);
assert((packet_type == CSI_MIPI_PACKET_TYPE_LONG) || (packet_type == CSI_MIPI_PACKET_TYPE_SHORT));
- assert(entry != NULL);
+ assert(entry);
- if ((backend < N_CSI_RX_BACKEND_ID) && (entry != NULL)) {
+ if ((backend < N_CSI_RX_BACKEND_ID) && (entry)) {
cur_rsrc = &isys_csi_rx_rsrc[backend];
if (packet_type == CSI_MIPI_PACKET_TYPE_LONG) {
max_num_packets_of_type = N_LONG_PACKET_LUT_ENTRIES[backend];
csi_mipi_packet_type_t packet_type,
csi_rx_backend_lut_entry_t *entry)
{
- uint32_t max_num_packets;
+ u32 max_num_packets;
isys_csi_rx_rsrc_t *cur_rsrc = NULL;
- uint32_t packet_entry = 0;
+ u32 packet_entry = 0;
assert(backend < N_CSI_RX_BACKEND_ID);
- assert(entry != NULL);
+ assert(entry);
assert((packet_type >= CSI_MIPI_PACKET_TYPE_LONG) || (packet_type <= CSI_MIPI_PACKET_TYPE_SHORT));
- if ((backend < N_CSI_RX_BACKEND_ID) && (entry != NULL)) {
+ if ((backend < N_CSI_RX_BACKEND_ID) && (entry)) {
if (packet_type == CSI_MIPI_PACKET_TYPE_LONG) {
max_num_packets = N_LONG_PACKET_LUT_ENTRIES[backend];
packet_entry = entry->long_packet_entry;
if ((port < N_INPUT_SYSTEM_CSI_PORT) &&
(isys_stream_id < SH_CSS_MAX_ISYS_CHANNEL_NODES)) {
struct sh_css_sp_pipeline_io_status *pipe_io_status;
+
pipe_io_status = ia_css_pipeline_get_pipe_io_status();
if (bitop_getbit(pipe_io_status->active[port], isys_stream_id) == 0) {
bitop_setbit(pipe_io_status->active[port], isys_stream_id);
if ((port < N_INPUT_SYSTEM_CSI_PORT) &&
(isys_stream_id < SH_CSS_MAX_ISYS_CHANNEL_NODES)) {
struct sh_css_sp_pipeline_io_status *pipe_io_status;
+
pipe_io_status = ia_css_pipeline_get_pipe_io_status();
if (bitop_getbit(pipe_io_status->active[port], isys_stream_id) == 1) {
bitop_clearbit(pipe_io_status->active[port], isys_stream_id);
typedef struct isys_csi_rx_rsrc_s isys_csi_rx_rsrc_t;
struct isys_csi_rx_rsrc_s {
- uint32_t active_table;
- uint32_t num_active;
- uint16_t num_long_packets;
- uint16_t num_short_packets;
+ u32 active_table;
+ u32 num_active;
+ u16 num_long_packets;
+ u16 num_short_packets;
};
#endif /* __CSI_RX_RMGR_H_INCLUDED__ */
-
}
bool ia_css_isys_ibuf_rmgr_acquire(
- uint32_t size,
+ u32 size,
uint32_t *start_addr)
{
bool retval = false;
bool input_buffer_found = false;
- uint32_t aligned_size;
+ u32 aligned_size;
ibuf_handle_t *handle = NULL;
- uint16_t i;
+ u16 i;
- assert(start_addr != NULL);
+ assert(start_addr);
assert(size > 0);
aligned_size = (size + (IBUF_ALIGN - 1)) & ~(IBUF_ALIGN - 1);
void ia_css_isys_ibuf_rmgr_release(
uint32_t *start_addr)
{
- uint16_t i;
+ u16 i;
ibuf_handle_t *handle = NULL;
- assert(start_addr != NULL);
+ assert(start_addr);
for (i = 0; i < ibuf_rsrc.num_allocated; i++) {
handle = getHandle(i);
typedef struct ibuf_handle_s ibuf_handle_t;
struct ibuf_handle_s {
- uint32_t start_addr;
- uint32_t size;
+ u32 start_addr;
+ u32 size;
bool active;
};
typedef struct ibuf_rsrc_s ibuf_rsrc_t;
struct ibuf_rsrc_s {
- uint32_t free_start_addr;
- uint32_t free_size;
- uint16_t num_active;
- uint16_t num_allocated;
+ u32 free_start_addr;
+ u32 free_size;
+ u16 num_active;
+ u16 num_allocated;
ibuf_handle_t handles[MAX_IBUF_HANDLES];
};
#endif /* __IBUF_CTRL_RMGR_H_INCLUDED */
-
isys_dma_rsrc_t *cur_rsrc = NULL;
assert(dma_id < N_ISYS2401_DMA_ID);
- assert(channel != NULL);
+ assert(channel);
max_dma_channel = N_ISYS2401_DMA_CHANNEL_PROCS[dma_id];
cur_rsrc = &isys_dma_rsrc[dma_id];
isys_dma_rsrc_t *cur_rsrc = NULL;
assert(dma_id < N_ISYS2401_DMA_ID);
- assert(channel != NULL);
+ assert(channel);
max_dma_channel = N_ISYS2401_DMA_CHANNEL_PROCS[dma_id];
cur_rsrc = &isys_dma_rsrc[dma_id];
typedef struct isys_dma_rsrc_s isys_dma_rsrc_t;
struct isys_dma_rsrc_s {
- uint32_t active_table;
- uint16_t num_active;
+ u32 active_table;
+ u16 num_active;
};
#endif /* __ISYS_DMA_RMGR_H_INCLUDED__ */
-
backend_channel_cfg_t backend_ch1;
target_cfg2400_t targetB;
target_cfg2400_t targetC;
- uint32_t acq_mem_region_size = 24;
- uint32_t acq_nof_mem_regions = 2;
+ u32 acq_mem_region_size = 24;
+ u32 acq_nof_mem_regions = 2;
input_system_error_t error = INPUT_SYSTEM_ERR_NO_ERROR;
memset(&backend_ch0, 0, sizeof(backend_channel_cfg_t));
stream2mmio_sid_ID_t i;
assert(stream2mmio < N_STREAM2MMIO_ID);
- assert(sid != NULL);
+ assert(sid);
- if ((stream2mmio < N_STREAM2MMIO_ID) && (sid != NULL)) {
+ if ((stream2mmio < N_STREAM2MMIO_ID) && (sid)) {
max_sid = N_STREAM2MMIO_SID_PROCS[stream2mmio];
cur_rsrc = &isys_stream2mmio_rsrc[stream2mmio];
isys_stream2mmio_rsrc_t *cur_rsrc = NULL;
assert(stream2mmio < N_STREAM2MMIO_ID);
- assert(sid != NULL);
+ assert(sid);
- if ((stream2mmio < N_STREAM2MMIO_ID) && (sid != NULL)) {
+ if ((stream2mmio < N_STREAM2MMIO_ID) && (sid)) {
max_sid = N_STREAM2MMIO_SID_PROCS[stream2mmio];
cur_rsrc = &isys_stream2mmio_rsrc[stream2mmio];
if ((*sid < max_sid) && (cur_rsrc->num_active > 0)) {
typedef struct isys_stream2mmio_rsrc_s isys_stream2mmio_rsrc_t;
struct isys_stream2mmio_rsrc_s {
- uint32_t active_table;
- uint16_t num_active;
+ u32 active_table;
+ u16 num_active;
};
#endif /* __ISYS_STREAM2MMIO_RMGR_H_INCLUDED__ */
-
unsigned int *irq_infos)
{
enum mipi_port_id port = ia_css_isys_port_to_mipi_port(api_port);
+
ia_css_isys_rx_get_irq_info(port, irq_infos);
}
{
unsigned int bits;
- assert(irq_infos != NULL);
+ assert(irq_infos);
bits = ia_css_isys_rx_get_interrupt_reg(port);
*irq_infos = ia_css_isys_rx_translate_irq_infos(bits);
}
void ia_css_rx_port_clear_irq_info(enum mipi_port_id api_port, unsigned int irq_infos)
{
enum mipi_port_id port = ia_css_isys_port_to_mipi_port(api_port);
+
ia_css_isys_rx_clear_irq_info(port, irq_infos);
}
mipi_predictor_t compression,
unsigned int *fmt_type)
{
- assert(fmt_type != NULL);
+ assert(fmt_type);
/*
* Custom (user defined) modes. Used for compressed
* MIPI transfers
}
return IA_CSS_SUCCESS;
}
+
#if defined(USE_INPUT_SYSTEM_VERSION_2401)
static mipi_predictor_t sh_css_csi2_compression_type_2_mipi_predictor(enum ia_css_csi2_compression_type type)
{
switch (type) {
case IA_CSS_CSI2_COMPRESSION_TYPE_1:
- predictor = MIPI_PREDICTOR_TYPE1-1;
+ predictor = MIPI_PREDICTOR_TYPE1 - 1;
break;
case IA_CSS_CSI2_COMPRESSION_TYPE_2:
- predictor = MIPI_PREDICTOR_TYPE2-1;
+ predictor = MIPI_PREDICTOR_TYPE2 - 1;
default:
break;
}
return predictor;
}
+
enum ia_css_err ia_css_isys_convert_compressed_format(
struct ia_css_csi2_compression *comp,
struct input_system_cfg_s *cfg)
{
enum ia_css_err err = IA_CSS_SUCCESS;
- assert(comp != NULL);
- assert(cfg != NULL);
+
+ assert(comp);
+ assert(cfg);
if (comp->type != IA_CSS_CSI2_COMPRESSION_TYPE_NONE) {
/* compression register bit slicing
bool any_port_enabled = false;
enum mipi_port_id port;
- if ((config == NULL)
+ if ((!config)
|| (config->mode >= N_RX_MODE)
|| (config->port >= N_MIPI_PORT_ID)) {
assert(0);
return;
}
- for (port = (enum mipi_port_id) 0; port < N_MIPI_PORT_ID; port++) {
+ for (port = (enum mipi_port_id)0; port < N_MIPI_PORT_ID; port++) {
if (is_receiver_port_enabled(RX0_ID, port))
any_port_enabled = true;
}
port_enabled[port] = true;
if (input_mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR) {
-
/* MW: A bit of a hack, straight wiring of the capture
* units,assuming they are linearly enumerated. */
input_system_sub_system_reg_store(INPUT_SYSTEM0_ID,
input_system_sub_system_reg_store(INPUT_SYSTEM0_ID,
GPREGS_UNIT0_ID,
HIVE_ISYS_GPREG_MUX_IDX,
- (input_system_multiplex_t) port);
+ (input_system_multiplex_t)port);
} else {
/*
* AM: A bit of a hack, wiring the input system.
void ia_css_isys_rx_disable(void)
{
enum mipi_port_id port;
- for (port = (enum mipi_port_id) 0; port < N_MIPI_PORT_ID; port++) {
+
+ for (port = (enum mipi_port_id)0; port < N_MIPI_PORT_ID; port++) {
receiver_port_reg_store(RX0_ID, port,
_HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX,
false);
return;
}
#endif /* if !defined(USE_INPUT_SYSTEM_VERSION_2401) */
-
stream2mmio_sid_ID_t *sid);
static bool acquire_ib_buffer(
- int32_t bits_per_pixel,
- int32_t pixels_per_line,
- int32_t lines_per_frame,
- int32_t align_in_bytes,
+ s32 bits_per_pixel,
+ s32 pixels_per_line,
+ s32 lines_per_frame,
+ s32 align_in_bytes,
bool online,
ib_buffer_t *buf);
int32_t data_type);
static int32_t calculate_stride(
- int32_t bits_per_pixel,
- int32_t pixels_per_line,
+ s32 bits_per_pixel,
+ s32 pixels_per_line,
bool raw_packed,
int32_t align_in_bytes);
{
ia_css_isys_error_t rc;
- if (isys_stream_descr == NULL || isys_stream == NULL ||
+ if (!isys_stream_descr || !isys_stream ||
isys_stream_id >= SH_CSS_MAX_ISYS_CHANNEL_NODES)
return false;
isys_stream->id = isys_stream_id;
isys_stream->linked_isys_stream_id = isys_stream_descr->linked_isys_stream_id;
- rc = create_input_system_input_port(isys_stream_descr, &(isys_stream->input_port));
+ rc = create_input_system_input_port(isys_stream_descr, &isys_stream->input_port);
if (rc == false)
return false;
- rc = create_input_system_channel(isys_stream_descr, false, &(isys_stream->channel));
+ rc = create_input_system_channel(isys_stream_descr, false, &isys_stream->channel);
if (rc == false) {
destroy_input_system_input_port(&isys_stream->input_port);
return false;
ia_css_isys_stream_h isys_stream)
{
destroy_input_system_input_port(&isys_stream->input_port);
- destroy_input_system_channel(&(isys_stream->channel));
+ destroy_input_system_channel(&isys_stream->channel);
if (isys_stream->enable_metadata) {
/* Destroy metadata channel only if its allocated*/
destroy_input_system_channel(&isys_stream->md_channel);
{
ia_css_isys_error_t rc;
- if (isys_stream_cfg == NULL ||
- isys_stream_descr == NULL ||
- isys_stream == NULL)
+ if (!isys_stream_cfg ||
+ !isys_stream_descr ||
+ !isys_stream)
return false;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"ia_css_isys_stream_calculate_cfg() enter:\n");
rc = calculate_input_system_channel_cfg(
- &(isys_stream->channel),
- &(isys_stream->input_port),
+ &isys_stream->channel,
+ &isys_stream->input_port,
isys_stream_descr,
- &(isys_stream_cfg->channel_cfg),
+ &isys_stream_cfg->channel_cfg,
false);
if (rc == false)
return false;
}
rc = calculate_input_system_input_port_cfg(
- &(isys_stream->channel),
- &(isys_stream->input_port),
+ &isys_stream->channel,
+ &isys_stream->input_port,
isys_stream_descr,
- &(isys_stream_cfg->input_port_cfg));
+ &isys_stream_cfg->input_port_cfg);
if (rc == false)
return false;
if (!rc)
return false;
- if (!acquire_sid(me->stream2mmio_id, &(me->stream2mmio_sid_id))) {
+ if (!acquire_sid(me->stream2mmio_id, &me->stream2mmio_sid_id)) {
return false;
}
metadata ? cfg->metadata.lines_per_frame : cfg->input_port_resolution.lines_per_frame,
metadata ? cfg->metadata.align_req_in_bytes : cfg->input_port_resolution.align_req_in_bytes,
cfg->online,
- &(me->ib_buffer))) {
- release_sid(me->stream2mmio_id, &(me->stream2mmio_sid_id));
+ &me->ib_buffer)) {
+ release_sid(me->stream2mmio_id, &me->stream2mmio_sid_id);
return false;
}
- if (!acquire_dma_channel(me->dma_id, &(me->dma_channel))) {
- release_sid(me->stream2mmio_id, &(me->stream2mmio_sid_id));
- release_ib_buffer(&(me->ib_buffer));
+ if (!acquire_dma_channel(me->dma_id, &me->dma_channel)) {
+ release_sid(me->stream2mmio_id, &me->stream2mmio_sid_id);
+ release_ib_buffer(&me->ib_buffer);
return false;
}
input_system_channel_t *me)
{
release_sid(me->stream2mmio_id,
- &(me->stream2mmio_sid_id));
+ &me->stream2mmio_sid_id);
- release_ib_buffer(&(me->ib_buffer));
+ release_ib_buffer(&me->ib_buffer);
- release_dma_channel(me->dma_id, &(me->dma_channel));
+ release_dma_channel(me->dma_id, &me->dma_channel);
}
static bool create_input_system_input_port(
rc = acquire_be_lut_entry(
me->csi_rx.backend_id,
packet_type,
- &(me->csi_rx.backend_lut_entry));
+ &me->csi_rx.backend_lut_entry);
break;
case INPUT_SYSTEM_PIXELGEN_PORT0_ID:
me->pixelgen.pixelgen_id = PIXELGEN0_ID;
rc = acquire_be_lut_entry(
me->csi_rx.backend_id,
packet_type,
- &(me->csi_rx.backend_lut_entry));
+ &me->csi_rx.backend_lut_entry);
break;
case INPUT_SYSTEM_PIXELGEN_PORT1_ID:
me->pixelgen.pixelgen_id = PIXELGEN1_ID;
rc = acquire_be_lut_entry(
me->csi_rx.backend_id,
packet_type,
- &(me->csi_rx.backend_lut_entry));
+ &me->csi_rx.backend_lut_entry);
break;
case INPUT_SYSTEM_PIXELGEN_PORT2_ID:
me->pixelgen.pixelgen_id = PIXELGEN2_ID;
bool rc;
rc = calculate_stream2mmio_cfg(isys_cfg, metadata,
- &(channel_cfg->stream2mmio_cfg));
+ &channel_cfg->stream2mmio_cfg);
if (!rc)
return false;
channel,
input_port,
isys_cfg,
- &(channel_cfg->ibuf_ctrl_cfg));
+ &channel_cfg->ibuf_ctrl_cfg);
if (!rc)
return false;
if (metadata)
rc = calculate_isys2401_dma_cfg(
channel,
isys_cfg,
- &(channel_cfg->dma_cfg));
+ &channel_cfg->dma_cfg);
if (!rc)
return false;
isys_cfg,
false,
metadata,
- &(channel_cfg->dma_src_port_cfg));
+ &channel_cfg->dma_src_port_cfg);
if (!rc)
return false;
isys_cfg,
isys_cfg->raw_packed,
metadata,
- &(channel_cfg->dma_dest_port_cfg));
+ &channel_cfg->dma_dest_port_cfg);
if (!rc)
return false;
case INPUT_SYSTEM_SOURCE_TYPE_SENSOR:
rc = calculate_fe_cfg(
isys_cfg,
- &(input_port_cfg->csi_rx_cfg.frontend_cfg));
+ &input_port_cfg->csi_rx_cfg.frontend_cfg);
rc &= calculate_be_cfg(
input_port,
isys_cfg,
false,
- &(input_port_cfg->csi_rx_cfg.backend_cfg));
+ &input_port_cfg->csi_rx_cfg.backend_cfg);
if (rc && isys_cfg->metadata.enable)
rc &= calculate_be_cfg(input_port, isys_cfg, true,
channel,
input_port,
isys_cfg,
- &(input_port_cfg->pixelgen_cfg.tpg_cfg));
+ &input_port_cfg->pixelgen_cfg.tpg_cfg);
break;
case INPUT_SYSTEM_SOURCE_TYPE_PRBS:
rc = calculate_prbs_cfg(
channel,
input_port,
isys_cfg,
- &(input_port_cfg->pixelgen_cfg.prbs_cfg));
+ &input_port_cfg->pixelgen_cfg.prbs_cfg);
break;
default:
rc = false;
/* See also: ia_css_dma_configure_from_info() */
static int32_t calculate_stride(
- int32_t bits_per_pixel,
- int32_t pixels_per_line,
+ s32 bits_per_pixel,
+ s32 pixels_per_line,
bool raw_packed,
int32_t align_in_bytes)
{
- int32_t bytes_per_line;
- int32_t pixels_per_word;
- int32_t words_per_line;
- int32_t pixels_per_line_padded;
+ s32 bytes_per_line;
+ s32 pixels_per_word;
+ s32 words_per_line;
+ s32 pixels_per_line_padded;
pixels_per_line_padded = CEIL_MUL(pixels_per_line, align_in_bytes);
}
static bool acquire_ib_buffer(
- int32_t bits_per_pixel,
- int32_t pixels_per_line,
- int32_t lines_per_frame,
- int32_t align_in_bytes,
+ s32 bits_per_pixel,
+ s32 pixels_per_line,
+ s32 lines_per_frame,
+ s32 align_in_bytes,
bool online,
ib_buffer_t *buf)
{
memcpy_s(
(void *)cfg,
sizeof(pixelgen_tpg_cfg_t),
- (void *)(&(isys_cfg->tpg_port_attr)),
+ (void *)(&isys_cfg->tpg_port_attr),
sizeof(pixelgen_tpg_cfg_t));
return true;
}
memcpy_s(
(void *)cfg,
sizeof(pixelgen_prbs_cfg_t),
- (void *)(&(isys_cfg->prbs_port_attr)),
+ (void *)(&isys_cfg->prbs_port_attr),
sizeof(pixelgen_prbs_cfg_t));
return true;
}
bool metadata,
csi_rx_backend_cfg_t *cfg)
{
-
memcpy_s(
(void *)(&cfg->lut_entry),
sizeof(csi_rx_backend_lut_entry_t),
cfg->csi_mipi_packet_type = get_csi_mipi_packet_type(isys_cfg->metadata.fmt_type);
cfg->csi_mipi_cfg.comp_enable = false;
cfg->csi_mipi_cfg.data_type = isys_cfg->metadata.fmt_type;
- }
- else {
+ } else {
cfg->csi_mipi_packet_type = get_csi_mipi_packet_type(isys_cfg->csi_port_attr.fmt_type);
cfg->csi_mipi_cfg.data_type = isys_cfg->csi_port_attr.fmt_type;
cfg->csi_mipi_cfg.comp_enable = isys_cfg->csi_port_attr.comp_enable;
const input_system_cfg_t *isys_cfg,
ibuf_ctrl_cfg_t *cfg)
{
- const int32_t bits_per_byte = 8;
- int32_t bits_per_pixel;
- int32_t bytes_per_pixel;
- int32_t left_padding;
+ const s32 bits_per_byte = 8;
+ s32 bits_per_pixel;
+ s32 bytes_per_pixel;
+ s32 left_padding;
(void)input_port;
cfg->stores_per_frame = isys_cfg->input_port_resolution.lines_per_frame;
-
cfg->stream2mmio_cfg.sync_cmd = _STREAM2MMIO_CMD_TOKEN_SYNC_FRAME;
/* TODO: Define conditions as when to use store words vs store packets */
bool metadata,
isys2401_dma_port_cfg_t *cfg)
{
- int32_t bits_per_pixel;
- int32_t pixels_per_line;
- int32_t align_req_in_bytes;
+ s32 bits_per_pixel;
+ s32 pixels_per_line;
+ s32 align_req_in_bytes;
/* TODO: Move metadata away from isys_cfg to application layer */
if (metadata) {
return packet_type;
}
+
/* end of Private Methods */
#endif
#define _STREAM2MMIO_CMD_TOKEN_SYNC_FRAME 2
#endif /* __VIRTUAL_ISYS_H_INCLUDED__ */
-
#define IA_CSS_PIPELINE_NUM_MAX (20)
-
/* Pipeline stage to be executed on SP/ISP */
struct ia_css_pipeline_stage {
unsigned int stage_num;
const struct ia_css_fw_info *firmware; /* acceleration binary */
/* SP function for SP stage */
enum ia_css_pipeline_stage_sp_func sp_func;
- unsigned max_input_width; /* For SP raw copy */
+ unsigned int max_input_width; /* For SP raw copy */
struct sh_css_binary_args args;
int mode;
bool out_frame_allocated[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
/* Pipeline of n stages to be executed on SP/ISP per stage */
struct ia_css_pipeline {
enum ia_css_pipe_id pipe_id;
- uint8_t pipe_num;
+ u8 pipe_num;
bool stop_requested;
struct ia_css_pipeline_stage *stages;
struct ia_css_pipeline_stage *current_stage;
- unsigned num_stages;
+ unsigned int num_stages;
struct ia_css_frame in_frame;
struct ia_css_frame out_frame[IA_CSS_PIPE_MAX_OUTPUT_STAGE];
struct ia_css_frame vf_frame[IA_CSS_PIPE_MAX_OUTPUT_STAGE];
unsigned int dvs_frame_delay;
- unsigned inout_port_config;
+ unsigned int inout_port_config;
int num_execs;
bool acquire_isp_each_stage;
- uint32_t pipe_qos_config;
+ u32 pipe_qos_config;
};
#define DEFAULT_PIPELINE \
struct ia_css_binary *binary;
const struct ia_css_fw_info *firmware;
enum ia_css_pipeline_stage_sp_func sp_func;
- unsigned max_input_width;
+ unsigned int max_input_width;
unsigned int mode;
struct ia_css_frame *in_frame;
struct ia_css_frame *out_frame[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
*/
void ia_css_pipeline_destroy(struct ia_css_pipeline *pipeline);
-
/* @brief Starts a pipeline
*
* @param[in] pipe_id
*
*/
enum ia_css_err ia_css_pipeline_get_stage_from_fw(struct ia_css_pipeline *pipeline,
- uint32_t fw_handle,
+ u32 fw_handle,
struct ia_css_pipeline_stage **stage);
/* @brief Gets the Firmware handle corresponding the stage num from the pipeline
*
*/
enum ia_css_err ia_css_pipeline_get_fw_from_stage(struct ia_css_pipeline *pipeline,
- uint32_t stage_num,
+ u32 stage_num,
uint32_t *fw_handle);
/* @brief gets the output stage from the pipeline
IA_CSS_PIPELINE_ISYS_COPY = 2,
IA_CSS_PIPELINE_NO_FUNC = 3,
};
+
#define IA_CSS_PIPELINE_NUM_STAGE_FUNCS 3
#endif /*__IA_CSS_PIPELINE_COMMON_H__*/
#define PIPELINE_SP_THREAD_EMPTY_TOKEN (0x0)
#define PIPELINE_SP_THREAD_RESERVED_TOKEN (0x1)
-
/*******************************************************
*** Static variables
********************************************************/
unsigned int pipe_num,
unsigned int dvs_frame_delay)
{
- assert(pipeline != NULL);
+ assert(pipeline);
IA_CSS_ENTER_PRIVATE("pipeline = %p, pipe_id = %d, pipe_num = %d, dvs_frame_delay = %d",
pipeline, pipe_id, pipe_num, dvs_frame_delay);
- if (pipeline == NULL) {
+ if (!pipeline) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
*/
void ia_css_pipeline_destroy(struct ia_css_pipeline *pipeline)
{
- assert(pipeline != NULL);
+ assert(pipeline);
IA_CSS_ENTER_PRIVATE("pipeline = %p", pipeline);
- if (pipeline == NULL) {
+ if (!pipeline) {
IA_CSS_ERROR("NULL input parameter");
IA_CSS_LEAVE_PRIVATE("void");
return;
void ia_css_pipeline_start(enum ia_css_pipe_id pipe_id,
struct ia_css_pipeline *pipeline)
{
- uint8_t pipe_num = 0;
+ u8 pipe_num = 0;
unsigned int thread_id;
- assert(pipeline != NULL);
+ assert(pipeline);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_pipeline_start() enter: pipe_id=%d, pipeline=%p\n",
pipe_id, pipeline);
#endif
#if !defined(HAS_NO_INPUT_SYSTEM)
#ifndef ISP2401
- , (enum mipi_port_id) 0
+ , (enum mipi_port_id)0
#else
- (enum mipi_port_id) 0,
+ (enum mipi_port_id)0,
#endif
#endif
#ifndef ISP2401
*/
bool ia_css_pipeline_get_sp_thread_id(unsigned int key, unsigned int *val)
{
-
IA_CSS_ENTER("key=%d, val=%p", key, val);
- if ((val == NULL) || (key >= IA_CSS_PIPELINE_NUM_MAX) || (key >= IA_CSS_PIPE_ID_NUM)) {
+ if ((!val) || (key >= IA_CSS_PIPELINE_NUM_MAX) || (key >= IA_CSS_PIPE_ID_NUM)) {
IA_CSS_LEAVE("return value = false");
return false;
}
*val = pipeline_num_to_sp_thread_map[key];
- if (*val == (unsigned)PIPELINE_NUM_UNMAPPED) {
+ if (*val == (unsigned int)PIPELINE_NUM_UNMAPPED) {
IA_CSS_LOG("unmapped pipeline number");
IA_CSS_LEAVE("return value = false");
return false;
void ia_css_pipeline_dump_thread_map_info(void)
{
unsigned int i;
+
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"pipeline_num_to_sp_thread_map:\n");
for (i = 0; i < IA_CSS_PIPELINE_NUM_MAX; i++) {
enum ia_css_err err = IA_CSS_SUCCESS;
unsigned int thread_id;
- assert(pipeline != NULL);
+ assert(pipeline);
- if (pipeline == NULL)
+ if (!pipeline)
return IA_CSS_ERR_INVALID_ARGUMENTS;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
{
struct ia_css_pipeline_stage *s;
- assert(pipeline != NULL);
+ assert(pipeline);
IA_CSS_ENTER_PRIVATE("pipeline = %p", pipeline);
- if (pipeline == NULL) {
+ if (!pipeline) {
IA_CSS_ERROR("NULL input parameter");
IA_CSS_LEAVE_PRIVATE("void");
return;
while (s) {
struct ia_css_pipeline_stage *next = s->next;
+
pipeline_stage_destroy(s);
s = next;
}
enum ia_css_err err;
/* other arguments can be NULL */
- assert(pipeline != NULL);
- assert(stage_desc != NULL);
+ assert(pipeline);
+ assert(stage_desc);
last = pipeline->stages;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
if (!stage_desc->binary && !stage_desc->firmware
&& (stage_desc->sp_func == IA_CSS_PIPELINE_NO_FUNC)) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
- "ia_css_pipeline_create_and_add_stage() done:"
- " Invalid args\n");
+ "ia_css_pipeline_create_and_add_stage() done: Invalid args\n");
return IA_CSS_ERR_INTERNAL_ERROR;
}
&& (!stage_desc->in_frame)
&& (!stage_desc->firmware)
&& (!stage_desc->binary->online)) {
-
/* Do this only for ISP stages*/
if (last && last->args.out_frame[0])
stage_desc->in_frame = last->args.out_frame[0];
err = pipeline_stage_create(stage_desc, &new_stage);
if (err != IA_CSS_SUCCESS) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
- "ia_css_pipeline_create_and_add_stage() done:"
- " stage_create_failed\n");
+ "ia_css_pipeline_create_and_add_stage() done: stage_create_failed\n");
return err;
}
void ia_css_pipeline_finalize_stages(struct ia_css_pipeline *pipeline,
bool continuous)
{
- unsigned i = 0;
+ unsigned int i = 0;
struct ia_css_pipeline_stage *stage;
- assert(pipeline != NULL);
+ assert(pipeline);
for (stage = pipeline->stages; stage; stage = stage->next) {
stage->stage_num = i;
i++;
struct ia_css_pipeline_stage **stage)
{
struct ia_css_pipeline_stage *s;
- assert(pipeline != NULL);
- assert(stage != NULL);
+
+ assert(pipeline);
+ assert(stage);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_pipeline_get_stage() enter:\n");
for (s = pipeline->stages; s; s = s->next) {
}
enum ia_css_err ia_css_pipeline_get_stage_from_fw(struct ia_css_pipeline *pipeline,
- uint32_t fw_handle,
+ u32 fw_handle,
struct ia_css_pipeline_stage **stage)
{
struct ia_css_pipeline_stage *s;
- assert(pipeline != NULL);
- assert(stage != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,"%s() \n",__func__);
+
+ assert(pipeline);
+ assert(stage);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__);
for (s = pipeline->stages; s; s = s->next) {
if ((s->firmware) && (s->firmware->handle == fw_handle)) {
*stage = s;
}
enum ia_css_err ia_css_pipeline_get_fw_from_stage(struct ia_css_pipeline *pipeline,
- uint32_t stage_num,
+ u32 stage_num,
uint32_t *fw_handle)
{
struct ia_css_pipeline_stage *s;
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,"%s() \n",__func__);
- if ((pipeline == NULL) || (fw_handle == NULL))
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__);
+ if ((!pipeline) || (!fw_handle))
return IA_CSS_ERR_INVALID_ARGUMENTS;
for (s = pipeline->stages; s; s = s->next) {
- if((s->stage_num == stage_num) && (s->firmware)) {
+ if ((s->stage_num == stage_num) && (s->firmware)) {
*fw_handle = s->firmware->handle;
return IA_CSS_SUCCESS;
}
struct ia_css_pipeline_stage **stage)
{
struct ia_css_pipeline_stage *s;
- assert(pipeline != NULL);
- assert(stage != NULL);
+
+ assert(pipeline);
+ assert(stage);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_pipeline_get_output_stage() enter:\n");
return false;
}
- ret = (bool)(pipeline_num_to_sp_thread_map[key] != (unsigned)PIPELINE_NUM_UNMAPPED);
+ ret = (bool)(pipeline_num_to_sp_thread_map[key] != (unsigned int)PIPELINE_NUM_UNMAPPED);
IA_CSS_LEAVE_PRIVATE("return = %d", ret);
return ret;
static void pipeline_stage_destroy(struct ia_css_pipeline_stage *stage)
{
unsigned int i;
+
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
if (stage->out_frame_allocated[i]) {
ia_css_frame_free(stage->args.out_frame[i]);
/* pipe is not mapped to any thread */
assert(pipeline_num_to_sp_thread_map[pipe_num]
- == (unsigned)PIPELINE_NUM_UNMAPPED);
+ == (unsigned int)PIPELINE_NUM_UNMAPPED);
for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++) {
if (pipeline_sp_thread_list[i] ==
static void pipeline_unmap_num_to_sp_thread(unsigned int pipe_num)
{
unsigned int thread_id;
+
assert(pipeline_num_to_sp_thread_map[pipe_num]
- != (unsigned)PIPELINE_NUM_UNMAPPED);
+ != (unsigned int)PIPELINE_NUM_UNMAPPED);
thread_id = pipeline_num_to_sp_thread_map[pipe_num];
pipeline_num_to_sp_thread_map[pipe_num] = PIPELINE_NUM_UNMAPPED;
}
stage = sh_css_malloc(sizeof(*stage));
- if (stage == NULL) {
+ if (!stage) {
err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
goto ERR;
}
*new_stage = stage;
return err;
ERR:
- if (stage != NULL)
+ if (stage)
pipeline_stage_destroy(stage);
return err;
}
struct ia_css_pipeline_stage *stage = NULL;
enum ia_css_err err = IA_CSS_SUCCESS;
- assert(pipeline != NULL);
+ assert(pipeline);
if (pipeline->pipe_id == IA_CSS_PIPE_ID_PREVIEW) {
/* in preview pipeline, vf_pp stage should do zoom */
err = ia_css_pipeline_get_stage(pipeline, IA_CSS_BINARY_MODE_VF_PP, &stage);
ia_css_circbuf_desc_t *cb_desc; /*Circbuf desc for local queues*/
ia_css_circbuf_elem_t *cb_elems; /*Circbuf elements*/
};
+
typedef struct ia_css_queue_local ia_css_queue_local_t;
/* Handle for queue object*/
typedef struct ia_css_queue ia_css_queue_t;
-
/*****************************************************************************
* Queue Public APIs
*****************************************************************************/
* @return EINVAL - Invalid argument.
*
*/
-extern int ia_css_queue_local_init(
+int ia_css_queue_local_init(
ia_css_queue_t *qhandle,
ia_css_queue_local_t *desc);
* @return 0 - Successful init of remote queue instance.
* @return EINVAL - Invalid argument.
*/
-extern int ia_css_queue_remote_init(
+int ia_css_queue_remote_init(
ia_css_queue_t *qhandle,
ia_css_queue_remote_t *desc);
* @return 0 - Successful uninit.
*
*/
-extern int ia_css_queue_uninit(
+int ia_css_queue_uninit(
ia_css_queue_t *qhandle);
/* @brief Enqueue an item in the queue instance
* @return ENOBUFS - Queue is full.
*
*/
-extern int ia_css_queue_enqueue(
+int ia_css_queue_enqueue(
ia_css_queue_t *qhandle,
uint32_t item);
* @return ENODATA - Queue is empty.
*
*/
-extern int ia_css_queue_dequeue(
+int ia_css_queue_dequeue(
ia_css_queue_t *qhandle,
uint32_t *item);
* @return ENOSYS - Function not implemented.
*
*/
-extern int ia_css_queue_is_empty(
+int ia_css_queue_is_empty(
ia_css_queue_t *qhandle,
bool *is_empty);
* @return ENOSYS - Function not implemented.
*
*/
-extern int ia_css_queue_is_full(
+int ia_css_queue_is_full(
ia_css_queue_t *qhandle,
bool *is_full);
* @return EINVAL - Invalid argument.
*
*/
-extern int ia_css_queue_get_used_space(
+int ia_css_queue_get_used_space(
ia_css_queue_t *qhandle,
uint32_t *size);
* @return EINVAL - Invalid argument.
*
*/
-extern int ia_css_queue_get_free_space(
+int ia_css_queue_get_free_space(
ia_css_queue_t *qhandle,
uint32_t *size);
*
* @param[in] qhandle. Handle to queue instance
* @param[in] offset Offset of element to peek,
- * starting from head of queue
+ * starting from head of queue
* @param[in] element Value of element returned
* @return 0 - Successfully access state.
* @return EINVAL - Invalid argument.
*
*/
-extern int ia_css_queue_peek(
+int ia_css_queue_peek(
ia_css_queue_t *qhandle,
- uint32_t offset,
+ u32 offset,
uint32_t *element);
/* @brief Get the usable size for the queue
* @return ENOSYS - Function not implemented.
*
*/
-extern int ia_css_queue_get_size(
+int ia_css_queue_get_size(
ia_css_queue_t *qhandle,
uint32_t *size);
#endif /* __IA_CSS_QUEUE_H */
-
/* Remote Queue object descriptor */
struct ia_css_queue_remote {
- uint32_t cb_desc_addr; /*Circbuf desc address for remote queues*/
- uint32_t cb_elems_addr; /*Circbuf elements addr for remote queue*/
- uint8_t location; /* Cell location for queue */
- uint8_t proc_id; /* Processor id for queue access */
+ u32 cb_desc_addr; /*Circbuf desc address for remote queues*/
+ u32 cb_elems_addr; /*Circbuf elements addr for remote queue*/
+ u8 location; /* Cell location for queue */
+ u8 proc_id; /* Processor id for queue access */
};
-typedef struct ia_css_queue_remote ia_css_queue_remote_t;
+typedef struct ia_css_queue_remote ia_css_queue_remote_t;
#endif /* __IA_CSS_QUEUE_COMM_H */
uint32_t item)
{
int error = 0;
- if (NULL == qhandle)
+
+ if (!qhandle)
return EINVAL;
/* 1. Load the required queue object */
} else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) {
ia_css_circbuf_desc_t cb_desc;
ia_css_circbuf_elem_t cb_elem;
- uint32_t ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG;
+ u32 ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG;
/* a. Load the queue cb_desc from remote */
QUEUE_CB_DESC_INIT(&cb_desc);
uint32_t *item)
{
int error = 0;
- if (qhandle == NULL || NULL == item)
+
+ if (!qhandle || NULL == item)
return EINVAL;
/* 1. Load the required queue object */
/* a. Load the queue from remote */
ia_css_circbuf_desc_t cb_desc;
ia_css_circbuf_elem_t cb_elem;
- uint32_t ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG;
+ u32 ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG;
QUEUE_CB_DESC_INIT(&cb_desc);
bool *is_full)
{
int error = 0;
- if ((qhandle == NULL) || (is_full == NULL))
+
+ if ((!qhandle) || (!is_full))
return EINVAL;
/* 1. Load the required queue object */
} else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) {
/* a. Load the queue from remote */
ia_css_circbuf_desc_t cb_desc;
- uint32_t ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG;
+ u32 ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG;
+
QUEUE_CB_DESC_INIT(&cb_desc);
error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags);
if (error != 0)
uint32_t *size)
{
int error = 0;
- if ((qhandle == NULL) || (size == NULL))
+
+ if ((!qhandle) || (!size))
return EINVAL;
/* 1. Load the required queue object */
} else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) {
/* a. Load the queue from remote */
ia_css_circbuf_desc_t cb_desc;
- uint32_t ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG;
+ u32 ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG;
+
QUEUE_CB_DESC_INIT(&cb_desc);
error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags);
if (error != 0)
uint32_t *size)
{
int error = 0;
- if ((qhandle == NULL) || (size == NULL))
+
+ if ((!qhandle) || (!size))
return EINVAL;
/* 1. Load the required queue object */
} else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) {
/* a. Load the queue from remote */
ia_css_circbuf_desc_t cb_desc;
- uint32_t ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG;
+ u32 ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG;
+
QUEUE_CB_DESC_INIT(&cb_desc);
error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags);
if (error != 0)
int ia_css_queue_peek(
ia_css_queue_t *qhandle,
- uint32_t offset,
+ u32 offset,
uint32_t *element)
{
- uint32_t num_elems = 0;
+ u32 num_elems = 0;
int error = 0;
- if ((qhandle == NULL) || (element == NULL))
+ if ((!qhandle) || (!element))
return EINVAL;
/* 1. Load the required queue object */
if (offset > num_elems)
return EINVAL;
- *element = ia_css_circbuf_peek_from_start(&qhandle->desc.cb_local, (int) offset);
+ *element = ia_css_circbuf_peek_from_start(&qhandle->desc.cb_local, (int)offset);
return 0;
} else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) {
/* a. Load the queue from remote */
ia_css_circbuf_desc_t cb_desc;
ia_css_circbuf_elem_t cb_elem;
- uint32_t ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG;
+ u32 ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG;
QUEUE_CB_DESC_INIT(&cb_desc);
bool *is_empty)
{
int error = 0;
- if ((qhandle == NULL) || (is_empty == NULL))
+
+ if ((!qhandle) || (!is_empty))
return EINVAL;
/* 1. Load the required queue object */
} else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) {
/* a. Load the queue from remote */
ia_css_circbuf_desc_t cb_desc;
- uint32_t ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG;
+ u32 ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG;
QUEUE_CB_DESC_INIT(&cb_desc);
error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags);
uint32_t *size)
{
int error = 0;
- if ((qhandle == NULL) || (size == NULL))
+
+ if ((!qhandle) || (!size))
return EINVAL;
/* 1. Load the required queue object */
} else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) {
/* a. Load the queue from remote */
ia_css_circbuf_desc_t cb_desc;
- uint32_t ignore_desc_flags = QUEUE_IGNORE_START_END_STEP_FLAGS;
+ u32 ignore_desc_flags = QUEUE_IGNORE_START_END_STEP_FLAGS;
QUEUE_CB_DESC_INIT(&cb_desc);
ia_css_circbuf_desc_t *cb_desc,
uint32_t ignore_desc_flags)
{
- if (rdesc == NULL || cb_desc == NULL)
+ if (!rdesc || !cb_desc)
return EINVAL;
if (rdesc->location == IA_CSS_QUEUE_LOC_SP) {
rdesc->desc.remote.cb_desc_addr
+ offsetof(ia_css_circbuf_desc_t, size));
- if (0 == cb_desc->size) {
+ if (cb_desc->size == 0) {
/* Adding back the workaround which was removed
while refactoring queues. When reading size
through sp_dmem_load_*, sometimes we get back
ia_css_circbuf_desc_t *cb_desc,
uint32_t ignore_desc_flags)
{
- if (rdesc == NULL || cb_desc == NULL)
+ if (!rdesc || !cb_desc)
return EINVAL;
if (rdesc->location == IA_CSS_QUEUE_LOC_SP) {
int ia_css_queue_item_load(
struct ia_css_queue *rdesc,
- uint8_t position,
+ u8 position,
ia_css_circbuf_elem_t *item)
{
- if (rdesc == NULL || item == NULL)
+ if (!rdesc || !item)
return EINVAL;
if (rdesc->location == IA_CSS_QUEUE_LOC_SP) {
int ia_css_queue_item_store(
struct ia_css_queue *rdesc,
- uint8_t position,
+ u8 position,
ia_css_circbuf_elem_t *item)
{
- if (rdesc == NULL || item == NULL)
+ if (!rdesc || !item)
return EINVAL;
if (rdesc->location == IA_CSS_QUEUE_LOC_SP) {
(cb_desc)->step = 0; \
(cb_desc)->start = 0; \
(cb_desc)->end = 0; \
- } while(0)
+ } while (0)
struct ia_css_queue {
- uint8_t type; /* Specify remote/local type of access */
- uint8_t location; /* Cell location for queue */
- uint8_t proc_id; /* Processor id for queue access */
+ u8 type; /* Specify remote/local type of access */
+ u8 location; /* Cell location for queue */
+ u8 proc_id; /* Processor id for queue access */
union {
ia_css_circbuf_t cb_local;
struct {
- uint32_t cb_desc_addr; /*Circbuf desc address for remote queues*/
- uint32_t cb_elems_addr; /*Circbuf elements addr for remote queue*/
+ u32 cb_desc_addr; /*Circbuf desc address for remote queues*/
+ u32 cb_elems_addr; /*Circbuf elements addr for remote queue*/
} remote;
} desc;
};
-extern int ia_css_queue_load(
+int ia_css_queue_load(
struct ia_css_queue *rdesc,
ia_css_circbuf_desc_t *cb_desc,
uint32_t ignore_desc_flags);
-extern int ia_css_queue_store(
+int ia_css_queue_store(
struct ia_css_queue *rdesc,
ia_css_circbuf_desc_t *cb_desc,
uint32_t ignore_desc_flags);
-extern int ia_css_queue_item_load(
+int ia_css_queue_item_load(
struct ia_css_queue *rdesc,
- uint8_t position,
+ u8 position,
ia_css_circbuf_elem_t *item);
-extern int ia_css_queue_item_store(
+int ia_css_queue_item_store(
struct ia_css_queue *rdesc,
- uint8_t position,
+ u8 position,
ia_css_circbuf_elem_t *item);
#endif /* __QUEUE_ACCESS_H */
*/
struct ia_css_rmgr_vbuf_handle {
hrt_vaddress vptr;
- uint8_t count;
- uint32_t size;
+ u8 count;
+ u32 size;
};
/**
* @brief Data structure for the resource pool (host, vbuf)
*/
struct ia_css_rmgr_vbuf_pool {
- uint8_t copy_on_write;
- uint8_t recycle;
- uint32_t size;
- uint32_t index;
+ u8 copy_on_write;
+ u8 recycle;
+ u32 size;
+ u32 index;
struct ia_css_rmgr_vbuf_handle **handles;
};
{
int i;
struct ia_css_rmgr_vbuf_handle *h;
- if ((handle == NULL) || (*handle == NULL)) {
+
+ if ((!handle) || (!*handle)) {
IA_CSS_LOG("Invalid inputs");
return;
}
/* if the loop dus not break and *handle == NULL
this is an error handle and report it.
*/
- if (*handle == NULL) {
+ if (!*handle) {
ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
"ia_css_i_host_refcount_retain_vbuf() failed to find empty slot!\n");
return;
*/
void ia_css_rmgr_refcount_release_vbuf(struct ia_css_rmgr_vbuf_handle **handle)
{
- if ((handle == NULL) || ((*handle) == NULL) || (((*handle)->count) == 0)) {
+ if ((!handle) || ((*handle) == NULL) || (((*handle)->count) == 0)) {
ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
"ia_css_rmgr_refcount_release_vbuf() invalid arguments!\n");
return;
{
enum ia_css_err err = IA_CSS_SUCCESS;
size_t bytes_needed;
+
rmgr_refcount_init_vbuf();
- assert(pool != NULL);
- if (pool == NULL)
+ assert(pool);
+ if (!pool)
return IA_CSS_ERR_INVALID_ARGUMENTS;
/* initialize the recycle pool if used */
if (pool->recycle && pool->size) {
sizeof(void *) *
pool->size;
pool->handles = sh_css_malloc(bytes_needed);
- if (pool->handles != NULL)
+ if (pool->handles)
memset(pool->handles, 0, bytes_needed);
else
err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
*/
void ia_css_rmgr_uninit_vbuf(struct ia_css_rmgr_vbuf_pool *pool)
{
- uint32_t i;
+ u32 i;
+
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_rmgr_uninit_vbuf()\n");
- if (pool == NULL) {
+ if (!pool) {
ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, "ia_css_rmgr_uninit_vbuf(): NULL argument\n");
return;
}
- if (pool->handles != NULL) {
+ if (pool->handles) {
/* free the hmm buffers */
for (i = 0; i < pool->size; i++) {
- if (pool->handles[i] != NULL) {
+ if (pool->handles[i]) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
" freeing/releasing %x (count=%d)\n",
pool->handles[i]->vptr,
void rmgr_push_handle(struct ia_css_rmgr_vbuf_pool *pool,
struct ia_css_rmgr_vbuf_handle **handle)
{
- uint32_t i;
+ u32 i;
bool succes = false;
- assert(pool != NULL);
+
+ assert(pool);
assert(pool->recycle);
- assert(pool->handles != NULL);
- assert(handle != NULL);
+ assert(pool->handles);
+ assert(handle);
for (i = 0; i < pool->size; i++) {
- if (pool->handles[i] == NULL) {
+ if (!pool->handles[i]) {
ia_css_rmgr_refcount_retain_vbuf(handle);
pool->handles[i] = *handle;
succes = true;
void rmgr_pop_handle(struct ia_css_rmgr_vbuf_pool *pool,
struct ia_css_rmgr_vbuf_handle **handle)
{
- uint32_t i;
+ u32 i;
bool succes = false;
- assert(pool != NULL);
+
+ assert(pool);
assert(pool->recycle);
- assert(pool->handles != NULL);
- assert(handle != NULL);
- assert(*handle != NULL);
+ assert(pool->handles);
+ assert(handle);
+ assert(*handle);
for (i = 0; i < pool->size; i++) {
- if ((pool->handles[i] != NULL) &&
+ if ((pool->handles[i]) &&
(pool->handles[i]->size == (*handle)->size)) {
*handle = pool->handles[i];
pool->handles[i] = NULL;
{
struct ia_css_rmgr_vbuf_handle h;
- if ((pool == NULL) || (handle == NULL) || (*handle == NULL)) {
+ if ((!pool) || (!handle) || (!*handle)) {
IA_CSS_LOG("Invalid inputs");
return;
}
void ia_css_rmgr_rel_vbuf(struct ia_css_rmgr_vbuf_pool *pool,
struct ia_css_rmgr_vbuf_handle **handle)
{
- if ((pool == NULL) || (handle == NULL) || (*handle == NULL)) {
+ if ((!pool) || (!handle) || (!*handle)) {
IA_CSS_LOG("Invalid inputs");
return;
}
#include <ia_css_err.h>
#include "ia_css_spctrl_comm.h"
-
typedef struct {
- uint32_t ddr_data_offset; /** posistion of data in DDR */
- uint32_t dmem_data_addr; /** data segment address in dmem */
- uint32_t dmem_bss_addr; /** bss segment address in dmem */
- uint32_t data_size; /** data segment size */
- uint32_t bss_size; /** bss segment size */
- uint32_t spctrl_config_dmem_addr; /* <location of dmem_cfg in SP dmem */
- uint32_t spctrl_state_dmem_addr; /* < location of state in SP dmem */
+ u32 ddr_data_offset; /** posistion of data in DDR */
+ u32 dmem_data_addr; /** data segment address in dmem */
+ u32 dmem_bss_addr; /** bss segment address in dmem */
+ u32 data_size; /** data segment size */
+ u32 bss_size; /** bss segment size */
+ u32 spctrl_config_dmem_addr; /* <location of dmem_cfg in SP dmem */
+ u32 spctrl_state_dmem_addr; /* < location of state in SP dmem */
unsigned int sp_entry; /* < entry function ptr on SP */
const void *code; /** location of firmware */
- uint32_t code_size;
+ u32 code_size;
char *program_name; /** not used on hardware, only for simulation */
} ia_css_spctrl_cfg;
*/
enum ia_css_err ia_css_spctrl_unload_fw(sp_ID_t sp_id);
-
/*! Intilaize dmem_cfg in SP dmem and start SP program
*/
enum ia_css_err ia_css_spctrl_start(sp_ID_t sp_id);
*/
struct ia_css_sp_init_dmem_cfg {
ia_css_ptr ddr_data_addr; /** data segment address in ddr */
- uint32_t dmem_data_addr; /** data segment address in dmem */
- uint32_t dmem_bss_addr; /** bss segment address in dmem */
- uint32_t data_size; /** data segment size */
- uint32_t bss_size; /** bss segment size */
+ u32 dmem_data_addr; /** data segment address in dmem */
+ u32 dmem_bss_addr; /** bss segment address in dmem */
+ u32 data_size; /** data segment size */
+ u32 bss_size; /** bss segment size */
sp_ID_t sp_id; /* <sp Id */
};
struct spctrl_context_info {
struct ia_css_sp_init_dmem_cfg dmem_config;
- uint32_t spctrl_config_dmem_addr; /* location of dmem_cfg in SP dmem */
- uint32_t spctrl_state_dmem_addr;
+ u32 spctrl_config_dmem_addr; /* location of dmem_cfg in SP dmem */
+ u32 spctrl_state_dmem_addr;
unsigned int sp_entry; /* entry function ptr on SP */
hrt_vaddress code_addr; /* sp firmware location in host mem-DDR*/
- uint32_t code_size;
+ u32 code_size;
char *program_name; /* used in case of PLATFORM_SIM */
};
hrt_vaddress code_addr = mmgr_NULL;
struct ia_css_sp_init_dmem_cfg *init_dmem_cfg;
- if ((sp_id >= N_SP_ID) || (spctrl_cfg == NULL))
+ if ((sp_id >= N_SP_ID) || (!spctrl_cfg))
return IA_CSS_ERR_INVALID_ARGUMENTS;
spctrl_cofig_info[sp_id].code_addr = mmgr_NULL;
{
ia_css_spctrl_sp_sw_state state = 0;
unsigned int HIVE_ADDR_sp_sw_state;
+
if (sp_id >= N_SP_ID)
return IA_CSS_SP_SW_TERMINATED;
HIVE_ADDR_sp_sw_state = spctrl_cofig_info[sp_id].spctrl_state_dmem_addr;
(void)HIVE_ADDR_sp_sw_state; /* Suppres warnings in CRUN */
if (sp_id == SP0_ID)
- state = sp_dmem_load_uint32(sp_id, (unsigned)sp_address_of(sp_sw_state));
+ state = sp_dmem_load_uint32(sp_id, (unsigned int)sp_address_of(sp_sw_state));
return state;
}
int ia_css_spctrl_is_idle(sp_ID_t sp_id)
{
int state = 0;
- assert (sp_id < N_SP_ID);
+
+ assert(sp_id < N_SP_ID);
state = sp_ctrl_getbit(sp_id, SP_SC_REG, SP_IDLE_BIT);
return state;
}
-
* @brief Data structure for the tagger buffer element.
*/
typedef struct {
- uint32_t frame; /* the frame value stored in the element */
- uint32_t param; /* the param value stored in the element */
- uint8_t mark; /* the mark on the element */
- uint8_t lock; /* the lock on the element */
- uint8_t exp_id; /* exp_id of frame, for debugging only */
+ u32 frame; /* the frame value stored in the element */
+ u32 param; /* the param value stored in the element */
+ u8 mark; /* the mark on the element */
+ u8 lock; /* the lock on the element */
+ u8 exp_id; /* exp_id of frame, for debugging only */
} ia_css_tagger_buf_sp_elem_t;
#endif /* __IA_CSS_TAGGER_COMMON_H__ */
enum ia_css_err
ia_css_timer_get_current_tick(
struct ia_css_clock_tick *curr_ts) {
-
- assert(curr_ts != NULL);
- if (curr_ts == NULL) {
+ assert(curr_ts);
+ if (!curr_ts) {
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
curr_ts->ticks = (clock_value_t)gp_timer_read(GP_TIMER_SEL);
return IA_CSS_SUCCESS;
}
-
#define JPEG_BYTES (16 * 1024 * 1024)
#define STATS_ENABLED(stage) (stage && stage->binary && stage->binary->info && \
- (stage->binary->info->sp.enable.s3a || stage->binary->info->sp.enable.dis))
+ (stage->binary->info->sp.enable.s3a || stage->binary->info->sp.enable.dis))
struct sh_css my_css;
-int (*sh_css_printf) (const char *fmt, va_list args) = NULL;
+int (*sh_css_printf)(const char *fmt, va_list args) = NULL;
/* modes of work: stream_create and stream_destroy will update the save/restore data
only when in working mode, not suspend/resume
*/
struct sh_css_save {
enum ia_sh_css_modes mode;
- uint32_t mmu_base; /* the last mmu_base */
+ u32 mmu_base; /* the last mmu_base */
enum ia_css_irq_type irq_type;
struct sh_css_stream_seed stream_seeds[MAX_ACTIVE_STREAMS];
struct ia_css_fw *loaded_fw; /* fw struct previously loaded */
static struct sh_css_hmm_buffer_record hmm_buffer_record[MAX_HMM_BUFFER_NUM];
-#define GPIO_FLASH_PIN_MASK (1 << HIVE_GPIO_STROBE_TRIGGER_PIN)
+#define GPIO_FLASH_PIN_MASK BIT(HIVE_GPIO_STROBE_TRIGGER_PIN)
-static bool fw_explicitly_loaded = false;
+static bool fw_explicitly_loaded;
/*
* Local prototypes
ia_css_pipe_unload_extension(struct ia_css_pipe *pipe,
struct ia_css_fw_info *firmware);
static void
-ia_css_reset_defaults(struct sh_css* css);
+ia_css_reset_defaults(struct sh_css *css);
static void
sh_css_init_host_sp_control_vars(void);
static enum ia_css_err
create_host_copy_pipeline(struct ia_css_pipe *pipe,
- unsigned max_input_width,
+ unsigned int max_input_width,
struct ia_css_frame *out_frame);
static enum ia_css_err
struct ia_css_pipe *pipe,
struct ia_css_isp_config *config);
-
#if CONFIG_ON_FRAME_ENQUEUE()
static enum ia_css_err set_config_on_frame_enqueue(struct ia_css_frame_info *info, struct frame_data_wrapper *frame);
#endif
static void
sh_css_pipe_free_shading_table(struct ia_css_pipe *pipe)
{
- assert(pipe != NULL);
- if (pipe == NULL) {
+ assert(pipe);
+ if (!pipe) {
IA_CSS_ERROR("NULL input parameter");
return;
}
enum ia_css_frame_format out_fmt = pipe->output_info[0].format;
unsigned int i, found = 0;
- assert(pipe != NULL);
- assert(pipe->stream != NULL);
+ assert(pipe);
+ assert(pipe->stream);
switch (pipe->stream->config.input_config.format) {
case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY:
case ATOMISP_INPUT_FORMAT_YUV420_8:
- for (i=0; i<ARRAY_SIZE(yuv420_copy_formats) && !found; i++)
+ for (i = 0; i < ARRAY_SIZE(yuv420_copy_formats) && !found; i++)
found = (out_fmt == yuv420_copy_formats[i]);
break;
case ATOMISP_INPUT_FORMAT_YUV420_10:
found = (out_fmt == IA_CSS_FRAME_FORMAT_YUV420_16);
break;
case ATOMISP_INPUT_FORMAT_YUV422_8:
- for (i=0; i<ARRAY_SIZE(yuv422_copy_formats) && !found; i++)
+ for (i = 0; i < ARRAY_SIZE(yuv422_copy_formats) && !found; i++)
found = (out_fmt == yuv422_copy_formats[i]);
break;
case ATOMISP_INPUT_FORMAT_YUV422_10:
{
int bpp = 0;
- if (stream != NULL)
+ if (stream)
bpp = ia_css_util_input_format_bpp(stream->config.input_config.format,
stream->config.pixels_per_clock == 2);
struct ia_css_binary *binary = NULL;
enum ia_css_err err = IA_CSS_SUCCESS;
- assert(stream != NULL);
- assert(pipe != NULL);
+ assert(stream);
+ assert(pipe);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"sh_css_config_input_network() enter:\n");
isys_stream_descr->tpg_port_attr.sync_gen_cfg.hblank_cycles = 100;
isys_stream_descr->tpg_port_attr.sync_gen_cfg.vblank_cycles = 100;
isys_stream_descr->tpg_port_attr.sync_gen_cfg.pixels_per_clock = stream_cfg->pixels_per_clock;
- isys_stream_descr->tpg_port_attr.sync_gen_cfg.nr_of_frames = (uint32_t) ~(0x0);
+ isys_stream_descr->tpg_port_attr.sync_gen_cfg.nr_of_frames = (uint32_t)~(0x0);
isys_stream_descr->tpg_port_attr.sync_gen_cfg.pixels_per_line = stream_cfg->isys_config[IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX].input_res.width;
isys_stream_descr->tpg_port_attr.sync_gen_cfg.lines_per_frame = stream_cfg->isys_config[IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX].input_res.height;
isys_stream_descr->prbs_port_attr.sync_gen_cfg.hblank_cycles = 100;
isys_stream_descr->prbs_port_attr.sync_gen_cfg.vblank_cycles = 100;
isys_stream_descr->prbs_port_attr.sync_gen_cfg.pixels_per_clock = stream_cfg->pixels_per_clock;
- isys_stream_descr->prbs_port_attr.sync_gen_cfg.nr_of_frames = (uint32_t) ~(0x0);
+ isys_stream_descr->prbs_port_attr.sync_gen_cfg.nr_of_frames = (uint32_t)~(0x0);
isys_stream_descr->prbs_port_attr.sync_gen_cfg.pixels_per_line = stream_cfg->isys_config[IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX].input_res.width;
isys_stream_descr->prbs_port_attr.sync_gen_cfg.lines_per_frame = stream_cfg->isys_config[IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX].input_res.height;
if ((stream_cfg->mode == IA_CSS_INPUT_MODE_SENSOR ||
stream_cfg->mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) &&
stream_cfg->source.port.compression.type != IA_CSS_CSI2_COMPRESSION_TYPE_NONE) {
-
if (stream_cfg->source.port.compression.uncompressed_bits_per_pixel ==
UNCOMPRESSED_BITS_PER_PIXEL_10) {
fmt_type = ATOMISP_INPUT_FORMAT_RAW_10;
- }
- else if (stream_cfg->source.port.compression.uncompressed_bits_per_pixel ==
+ } else if (stream_cfg->source.port.compression.uncompressed_bits_per_pixel ==
UNCOMPRESSED_BITS_PER_PIXEL_12) {
fmt_type = ATOMISP_INPUT_FORMAT_RAW_12;
- }
- else
+ } else
return false;
}
rc &= sh_css_translate_stream_cfg_to_input_system_input_port_resolution(stream_cfg, isys_stream_descr, isys_stream_idx);
isys_stream_descr->raw_packed = stream_cfg->pack_raw_pixels;
- isys_stream_descr->linked_isys_stream_id = (int8_t) stream_cfg->isys_config[isys_stream_idx].linked_isys_stream_id;
+ isys_stream_descr->linked_isys_stream_id = (int8_t)stream_cfg->isys_config[isys_stream_idx].linked_isys_stream_id;
/*
* Early polling is required for timestamp accuracy in certain case.
* The ISYS HW polling is started on
static bool sh_css_translate_binary_info_to_input_system_output_port_attr(
struct ia_css_binary *binary,
- ia_css_isys_descr_t *isys_stream_descr)
+ ia_css_isys_descr_t *isys_stream_descr)
{
if (!binary)
return false;
struct ia_css_pipe *pipe = NULL;
struct ia_css_binary *binary = NULL;
int i;
- uint32_t isys_stream_id;
+ u32 isys_stream_id;
bool early_polling = false;
- assert(stream != NULL);
+ assert(stream);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"sh_css_config_input_network() enter 0x%p:\n", stream);
}
}
- assert(pipe != NULL);
- if (pipe == NULL)
+ assert(pipe);
+ if (!pipe)
return IA_CSS_ERR_INTERNAL_ERROR;
- if (pipe->pipeline.stages != NULL)
- if (pipe->pipeline.stages->binary != NULL)
+ if (pipe->pipeline.stages)
+ if (pipe->pipeline.stages->binary)
binary = pipe->pipeline.stages->binary;
-
-
if (binary) {
/* this was being done in ifmtr in 2400.
* online and cont bypass the init_in_frameinfo_memory_defaults
if (!rc)
return IA_CSS_ERR_INTERNAL_ERROR;
/* get the target input terminal */
- sp_pipeline_input_terminal = &(sh_css_sp_group.pipe_io[sp_thread_id].input);
+ sp_pipeline_input_terminal = &sh_css_sp_group.pipe_io[sp_thread_id].input;
for (i = 0; i < IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH; i++) {
/* initialization */
- memset((void*)(&isys_stream_descr), 0, sizeof(ia_css_isys_descr_t));
+ memset((void *)(&isys_stream_descr), 0, sizeof(ia_css_isys_descr_t));
sp_pipeline_input_terminal->context.virtual_input_system_stream[i].valid = 0;
sp_pipeline_input_terminal->ctrl.virtual_input_system_stream_cfg[i].valid = 0;
/* translate the stream configuration to the Input System (2401) configuration */
rc = sh_css_translate_stream_cfg_to_isys_stream_descr(
- &(stream->config),
+ &stream->config,
early_polling,
&(isys_stream_descr), i);
/* create the virtual Input System (2401) */
rc = ia_css_isys_stream_create(
&(isys_stream_descr),
- &(sp_pipeline_input_terminal->context.virtual_input_system_stream[i]),
+ &sp_pipeline_input_terminal->context.virtual_input_system_stream[i],
isys_stream_id);
if (!rc)
return IA_CSS_ERR_INTERNAL_ERROR;
/* calculate the configuration of the virtual Input System (2401) */
rc = ia_css_isys_stream_calculate_cfg(
- &(sp_pipeline_input_terminal->context.virtual_input_system_stream[i]),
+ &sp_pipeline_input_terminal->context.virtual_input_system_stream[i],
&(isys_stream_descr),
- &(sp_pipeline_input_terminal->ctrl.virtual_input_system_stream_cfg[i]));
+ &sp_pipeline_input_terminal->ctrl.virtual_input_system_stream_cfg[i]);
if (!rc) {
- ia_css_isys_stream_destroy(&(sp_pipeline_input_terminal->context.virtual_input_system_stream[i]));
+ ia_css_isys_stream_destroy(&sp_pipeline_input_terminal->context.virtual_input_system_stream[i]);
return IA_CSS_ERR_INTERNAL_ERROR;
}
}
struct ia_css_stream *stream)
{
struct ia_css_pipe *last_pipe = NULL;
- if (stream != NULL)
+
+ if (stream)
last_pipe = stream->last_pipe;
return last_pipe;
last_pipe = stream_get_last_pipe(stream);
- if ((stream != NULL) &&
- (last_pipe != NULL) &&
+ if ((stream) &&
+ (last_pipe) &&
(stream->config.continuous)) {
-
pipe_id = last_pipe->mode;
switch (pipe_id) {
case IA_CSS_PIPE_ID_PREVIEW:
enum ia_css_err (*func)(enum mipi_port_id, uint32_t))
{
enum ia_css_err retval = IA_CSS_ERR_INTERNAL_ERROR;
- uint32_t sp_thread_id, stream_id;
+ u32 sp_thread_id, stream_id;
bool rc;
struct ia_css_pipe *target_pipe = NULL;
- if ((stream == NULL) || (stream->config.mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR))
+ if ((!stream) || (stream->config.mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR))
goto exit;
target_pipe = stream_get_target_pipe(stream);
- if (target_pipe == NULL)
+ if (!target_pipe)
goto exit;
rc = ia_css_pipeline_get_sp_thread_id(
stream_id = 0;
do {
if (stream->config.isys_config[stream_id].valid) {
- uint32_t isys_stream_id = ia_css_isys_generate_stream_id(sp_thread_id, stream_id);
+ u32 isys_stream_id = ia_css_isys_generate_stream_id(sp_thread_id, stream_id);
+
retval = func(stream->config.source.port.port, isys_stream_id);
}
stream_id++;
static void print_pc_histo(char *core_name, struct sh_css_pc_histogram *hist)
{
- unsigned i;
- unsigned cnt_run = 0;
- unsigned cnt_stall = 0;
+ unsigned int i;
+ unsigned int cnt_run = 0;
+ unsigned int cnt_stall = 0;
- if (hist == NULL)
+ if (!hist)
return;
sh_css_print("%s histogram length = %d\n", core_name, hist->length);
cnt_stall += hist->stall[i];
}
- sh_css_print(" Statistics for %s, cnt_run = %d, cnt_stall = %d, "
- "hist->length = %d\n",
+ sh_css_print(" Statistics for %s, cnt_run = %d, cnt_stall = %d, hist->length = %d\n",
core_name, cnt_run, cnt_stall, hist->length);
}
sh_css_print(" pc_histogram for binary %d\n", metrics->id);
print_pc_histo(" ISP", &metrics->isp_histogram);
print_pc_histo(" SP", &metrics->sp_histogram);
- sh_css_print("print_pc_histogram() done for binay->id = %d, "
- "done.\n", metrics->id);
+ sh_css_print("print_pc_histogram() done for binay->id = %d, done.\n",
+ metrics->id);
}
sh_css_print("PC_MONITORING:print_pc_histogram() -- DONE\n");
static void input_frame_info(struct ia_css_frame_info frame_info)
{
- sh_css_print("SH_CSS:input_frame_info() -- frame->info.res.width = %d, "
- "frame->info.res.height = %d, format = %d\n",
+ sh_css_print("SH_CSS:input_frame_info() -- frame->info.res.width = %d, frame->info.res.height = %d, format = %d\n",
frame_info.res.width, frame_info.res.height, frame_info.format);
}
#endif /* WITH_PC_MONITORING */
{
struct ia_css_stream *stream;
- assert(pipe != NULL);
+ assert(pipe);
/* Acceleration uses firmware, the binary thus can be NULL */
/* assert(binary != NULL); */
sh_css_metrics_start_binary(&binary->metrics);
#if WITH_PC_MONITORING
- sh_css_print("PC_MONITORING: %s() -- binary id = %d , "
- "enable_dvs_envelope = %d\n",
+ sh_css_print("PC_MONITORING: %s() -- binary id = %d , enable_dvs_envelope = %d\n",
__func__, binary->info->sp.id,
binary->info->sp.enable.dvs_envelope);
input_frame_info(binary->in_frame_info);
start_copy_on_sp(struct ia_css_pipe *pipe,
struct ia_css_frame *out_frame)
{
-
(void)out_frame;
- assert(pipe != NULL);
- assert(pipe->stream != NULL);
+ assert(pipe);
+ assert(pipe->stream);
- if ((pipe == NULL) || (pipe->stream == NULL))
+ if ((!pipe) || (!pipe->stream))
return IA_CSS_ERR_INVALID_ARGUMENTS;
#if !defined(HAS_NO_INPUT_SYSTEM) && !defined(USE_INPUT_SYSTEM_VERSION_2401)
IA_CSS_ENTER_PRIVATE("me = %p, copy_ovrd = %d, input_mode = %d",
me, copy_ovrd, input_mode);
- assert(me != NULL); /* all callers are in this file and call with non null argument */
+ assert(me); /* all callers are in this file and call with non null argument */
sh_css_sp_init_pipeline(&me->pipeline,
me->mode,
&me->stream->config.metadata_config,
&me->stream->info.metadata_info
#if !defined(HAS_NO_INPUT_SYSTEM)
- ,(input_mode==IA_CSS_INPUT_MODE_MEMORY) ?
+ , (input_mode == IA_CSS_INPUT_MODE_MEMORY) ?
(enum mipi_port_id)0 :
me->stream->config.source.port.port
#endif
#ifdef ISP2401
- ,&me->config.internal_frame_origin_bqs_on_sctbl,
+ , &me->config.internal_frame_origin_bqs_on_sctbl,
me->stream->isp_params_configs
#endif
);
if (me->config.mode != IA_CSS_PIPE_MODE_COPY) {
struct ia_css_pipeline_stage *stage;
+
stage = me->pipeline.stages;
if (stage) {
me->pipeline.current_stage = stage;
sh_css_invalidate_shading_tables(struct ia_css_stream *stream)
{
int i;
- assert(stream != NULL);
+
+ assert(stream);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"sh_css_invalidate_shading_tables() enter:\n");
- for (i=0; i<stream->num_pipes; i++) {
- assert(stream->pipes[i] != NULL);
+ for (i = 0; i < stream->num_pipes; i++) {
+ assert(stream->pipes[i]);
sh_css_pipe_free_shading_table(stream->pipes[i]);
}
enum mipi_port_id port;
#endif
bool enable_pulse = irq_type != IA_CSS_IRQ_TYPE_EDGE;
+
IA_CSS_ENTER_PRIVATE("");
/* Enable IRQ on the SP which signals that SP goes to idle
* (aka ready state) */
#endif
static bool sh_css_setup_spctrl_config(const struct ia_css_fw_info *fw,
- const char * program,
+ const char *program,
ia_css_spctrl_cfg *spctrl_cfg)
{
- if((fw == NULL)||(spctrl_cfg == NULL))
+ if ((!fw) || (!spctrl_cfg))
return false;
spctrl_cfg->sp_entry = 0;
spctrl_cfg->program_name = (char *)(program);
spctrl_cfg->ddr_data_offset = fw->blob.data_source;
spctrl_cfg->dmem_data_addr = fw->blob.data_target;
spctrl_cfg->dmem_bss_addr = fw->blob.bss_target;
- spctrl_cfg->data_size = fw->blob.data_size ;
+ spctrl_cfg->data_size = fw->blob.data_size;
spctrl_cfg->bss_size = fw->blob.bss_size;
spctrl_cfg->spctrl_config_dmem_addr = fw->info.sp.init_dmem_data;
return true;
}
+
void
ia_css_unload_firmware(void)
{
}
static void
-ia_css_reset_defaults(struct sh_css* css)
+ia_css_reset_defaults(struct sh_css *css)
{
struct sh_css default_css;
{
bool retval = false;
- if (fw != NULL) {
+ if (fw) {
retval = sh_css_check_firmware_version(fw->data);
}
return retval;
{
enum ia_css_err err;
- if (env == NULL)
+ if (!env)
return IA_CSS_ERR_INVALID_ARGUMENTS;
- if (fw == NULL)
+ if (!fw)
return IA_CSS_ERR_INVALID_ARGUMENTS;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_load_firmware() enter\n");
fw_explicitly_loaded = true;
}
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_load_firmware() leave \n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_load_firmware() leave\n");
return err;
}
enum ia_css_err
ia_css_init(const struct ia_css_env *env,
const struct ia_css_fw *fw,
- uint32_t mmu_l1_base,
+ u32 mmu_l1_base,
enum ia_css_irq_type irq_type)
{
enum ia_css_err err;
* equal, functionality will break.
*/
/* Check struct sh_css_ddr_address_map */
- COMPILATION_ERROR_IF( sizeof(struct sh_css_ddr_address_map) != SIZE_OF_SH_CSS_DDR_ADDRESS_MAP_STRUCT );
+ COMPILATION_ERROR_IF(sizeof(struct sh_css_ddr_address_map) != SIZE_OF_SH_CSS_DDR_ADDRESS_MAP_STRUCT);
/* Check struct host_sp_queues */
- COMPILATION_ERROR_IF( sizeof(struct host_sp_queues) != SIZE_OF_HOST_SP_QUEUES_STRUCT );
- COMPILATION_ERROR_IF( sizeof(struct ia_css_circbuf_desc_s) != SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT );
- COMPILATION_ERROR_IF( sizeof(struct ia_css_circbuf_elem_s) != SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT );
+ COMPILATION_ERROR_IF(sizeof(struct host_sp_queues) != SIZE_OF_HOST_SP_QUEUES_STRUCT);
+ COMPILATION_ERROR_IF(sizeof(struct ia_css_circbuf_desc_s) != SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT);
+ COMPILATION_ERROR_IF(sizeof(struct ia_css_circbuf_elem_s) != SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT);
/* Check struct host_sp_communication */
- COMPILATION_ERROR_IF( sizeof(struct host_sp_communication) != SIZE_OF_HOST_SP_COMMUNICATION_STRUCT );
- COMPILATION_ERROR_IF( sizeof(struct sh_css_event_irq_mask) != SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT );
+ COMPILATION_ERROR_IF(sizeof(struct host_sp_communication) != SIZE_OF_HOST_SP_COMMUNICATION_STRUCT);
+ COMPILATION_ERROR_IF(sizeof(struct sh_css_event_irq_mask) != SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT);
/* Check struct sh_css_hmm_buffer */
- COMPILATION_ERROR_IF( sizeof(struct sh_css_hmm_buffer) != SIZE_OF_SH_CSS_HMM_BUFFER_STRUCT );
- COMPILATION_ERROR_IF( sizeof(struct ia_css_isp_3a_statistics) != SIZE_OF_IA_CSS_ISP_3A_STATISTICS_STRUCT );
- COMPILATION_ERROR_IF( sizeof(struct ia_css_isp_dvs_statistics) != SIZE_OF_IA_CSS_ISP_DVS_STATISTICS_STRUCT );
- COMPILATION_ERROR_IF( sizeof(struct ia_css_metadata) != SIZE_OF_IA_CSS_METADATA_STRUCT );
+ COMPILATION_ERROR_IF(sizeof(struct sh_css_hmm_buffer) != SIZE_OF_SH_CSS_HMM_BUFFER_STRUCT);
+ COMPILATION_ERROR_IF(sizeof(struct ia_css_isp_3a_statistics) != SIZE_OF_IA_CSS_ISP_3A_STATISTICS_STRUCT);
+ COMPILATION_ERROR_IF(sizeof(struct ia_css_isp_dvs_statistics) != SIZE_OF_IA_CSS_ISP_DVS_STATISTICS_STRUCT);
+ COMPILATION_ERROR_IF(sizeof(struct ia_css_metadata) != SIZE_OF_IA_CSS_METADATA_STRUCT);
/* Check struct ia_css_init_dmem_cfg */
- COMPILATION_ERROR_IF( sizeof(struct ia_css_sp_init_dmem_cfg) != SIZE_OF_IA_CSS_SP_INIT_DMEM_CFG_STRUCT );
+ COMPILATION_ERROR_IF(sizeof(struct ia_css_sp_init_dmem_cfg) != SIZE_OF_IA_CSS_SP_INIT_DMEM_CFG_STRUCT);
- if (fw == NULL && !fw_explicitly_loaded)
+ if (!fw && !fw_explicitly_loaded)
return IA_CSS_ERR_INVALID_ARGUMENTS;
- if (env == NULL)
- return IA_CSS_ERR_INVALID_ARGUMENTS;
+ if (!env)
+ return IA_CSS_ERR_INVALID_ARGUMENTS;
sh_css_printf = env->print_env.debug_print;
my_css_save.loaded_fw = (struct ia_css_fw *)fw;
#endif
}
- if(!sh_css_setup_spctrl_config(&sh_css_sp_fw,SP_PROG_NAME,&spctrl_cfg))
+ if (!sh_css_setup_spctrl_config(&sh_css_sp_fw, SP_PROG_NAME, &spctrl_cfg))
return IA_CSS_ERR_INTERNAL_ERROR;
err = ia_css_spctrl_load_fw(SP0_ID, &spctrl_cfg);
#if defined(HAS_INPUT_SYSTEM_VERSION_2) && defined(HAS_INPUT_SYSTEM_VERSION_2401)
#if defined(USE_INPUT_SYSTEM_VERSION_2)
gp_device_reg_store(GP_DEVICE0_ID, _REG_GP_SWITCH_ISYS2401_ADDR, 0);
-#elif defined (USE_INPUT_SYSTEM_VERSION_2401)
+#elif defined(USE_INPUT_SYSTEM_VERSION_2401)
gp_device_reg_store(GP_DEVICE0_ID, _REG_GP_SWITCH_ISYS2401_ADDR, 1);
#endif
#endif
dma_set_max_burst_size(DMA0_ID, HIVE_DMA_BUS_DDR_CONN,
ISP_DMA_MAX_BURST_LENGTH);
- if(ia_css_isys_init() != INPUT_SYSTEM_ERR_NO_ERROR)
+ if (ia_css_isys_init() != INPUT_SYSTEM_ERR_NO_ERROR)
err = IA_CSS_ERR_INVALID_ARGUMENTS;
#endif
enum ia_css_err ia_css_suspend(void)
{
int i;
+
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_suspend() enter\n");
my_css_save.mode = sh_css_mode_suspend;
- for(i=0;i<MAX_ACTIVE_STREAMS;i++)
- if (my_css_save.stream_seeds[i].stream != NULL)
+ for (i = 0; i < MAX_ACTIVE_STREAMS; i++)
+ if (my_css_save.stream_seeds[i].stream)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "==*> unloading seed %d (%p)\n", i, my_css_save.stream_seeds[i].stream);
ia_css_stream_unload(my_css_save.stream_seeds[i].stream);
my_css_save.mode = sh_css_mode_working;
ia_css_stop_sp();
ia_css_uninit();
- for(i=0;i<MAX_ACTIVE_STREAMS;i++)
+ for (i = 0; i < MAX_ACTIVE_STREAMS; i++)
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "==*> after 1: seed %d (%p)\n", i, my_css_save.stream_seeds[i].stream);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_suspend() leave\n");
return IA_CSS_SUCCESS;
{
int i, j;
enum ia_css_err err;
+
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_resume() enter: void\n");
- err = ia_css_init(&(my_css_save.driver_env), my_css_save.loaded_fw, my_css_save.mmu_base, my_css_save.irq_type);
+ err = ia_css_init(&my_css_save.driver_env, my_css_save.loaded_fw, my_css_save.mmu_base, my_css_save.irq_type);
if (err != IA_CSS_SUCCESS)
return err;
err = ia_css_start_sp();
if (err != IA_CSS_SUCCESS)
return err;
my_css_save.mode = sh_css_mode_resume;
- for(i=0;i<MAX_ACTIVE_STREAMS;i++)
+ for (i = 0; i < MAX_ACTIVE_STREAMS; i++)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "==*> seed stream %p\n", my_css_save.stream_seeds[i].stream);
- if (my_css_save.stream_seeds[i].stream != NULL)
+ if (my_css_save.stream_seeds[i].stream)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "==*> loading seed %d\n", i);
err = ia_css_stream_load(my_css_save.stream_seeds[i].stream);
if (err != IA_CSS_SUCCESS)
{
if (i)
- for(j=0;j<i;j++)
+ for (j = 0; j < i; j++)
ia_css_stream_unload(my_css_save.stream_seeds[j].stream);
return err;
}
err = ia_css_stream_start(my_css_save.stream_seeds[i].stream);
if (err != IA_CSS_SUCCESS)
{
- for(j=0;j<=i;j++)
+ for (j = 0; j <= i; j++)
{
ia_css_stream_stop(my_css_save.stream_seeds[j].stream);
ia_css_stream_unload(my_css_save.stream_seeds[j].stream);
return err;
}
*my_css_save.stream_seeds[i].orig_stream = my_css_save.stream_seeds[i].stream;
- for(j=0;j<my_css_save.stream_seeds[i].num_pipes;j++)
- *(my_css_save.stream_seeds[i].orig_pipes[j]) = my_css_save.stream_seeds[i].pipes[j];
+ for (j = 0; j < my_css_save.stream_seeds[i].num_pipes; j++)
+ *my_css_save.stream_seeds[i].orig_pipes[j] = my_css_save.stream_seeds[i].pipes[j];
}
}
my_css_save.mode = sh_css_mode_working;
void *sh_css_malloc(size_t size)
{
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_malloc() enter: size=%zu\n",size);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_malloc() enter: size=%zu\n", size);
/* FIXME: This first test can probably go away */
if (size == 0)
return NULL;
{
void *p;
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_calloc() enter: N=%zu, size=%zu\n",N,size);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_calloc() enter: N=%zu, size=%zu\n", N, size);
/* FIXME: this test can probably go away */
if (size > 0) {
- p = sh_css_malloc(N*size);
+ p = sh_css_malloc(N * size);
if (p)
memset(p, 0, size);
return p;
sh_css_flush(struct ia_css_acc_fw *fw)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_flush() enter:\n");
- if ((fw != NULL) && (my_css.flush != NULL))
+ if ((fw) && (my_css.flush))
my_css.flush(fw);
}
enum ia_css_err err = IA_CSS_SUCCESS;
enum ia_css_pipe_id pipe_id;
- assert(stream != NULL);
+ assert(stream);
IA_CSS_ENTER_PRIVATE("stream = %p, map = %s",
stream, map ? "true" : "false");
- if (stream == NULL) {
+ if (!stream) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
ia_css_pipeline_map(acc_pipe->pipe_num, map);
}
- if(capture_pipe) {
+ if (capture_pipe) {
ia_css_pipeline_map(capture_pipe->pipe_num, map);
}
/* Firmware expects copy pipe to be the last pipe mapped. (if needed) */
- if(copy_pipe) {
+ if (copy_pipe) {
ia_css_pipeline_map(copy_pipe->pipe_num, map);
}
/* DH regular multi pipe - not continuous mode: map the next pipes too */
if (!stream->config.continuous) {
int i;
+
for (i = 1; i < stream->num_pipes; i++)
ia_css_pipeline_map(stream->pipes[i]->pipe_num, map);
}
unsigned int copy_pipe_delay = 0,
capture_pipe_delay = 0;
- assert(stream != NULL);
+ assert(stream);
IA_CSS_ENTER_PRIVATE("stream = %p", stream);
- if (stream == NULL) {
+ if (!stream) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
main_pipe = stream->last_pipe;
- assert(main_pipe != NULL);
- if (main_pipe == NULL) {
+ assert(main_pipe);
+ if (!main_pipe) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
err = IA_CSS_ERR_INVALID_ARGUMENTS;
}
- if ((IA_CSS_SUCCESS == err) && copy_pipe) {
+ if ((err == IA_CSS_SUCCESS) && copy_pipe) {
err = ia_css_pipeline_create(©_pipe->pipeline,
copy_pipe->mode,
copy_pipe->pipe_num,
copy_pipe_delay);
}
- if ((IA_CSS_SUCCESS == err) && capture_pipe) {
+ if ((err == IA_CSS_SUCCESS) && capture_pipe) {
err = ia_css_pipeline_create(&capture_pipe->pipeline,
capture_pipe->mode,
capture_pipe->pipe_num,
capture_pipe_delay);
}
- if ((IA_CSS_SUCCESS == err) && acc_pipe) {
+ if ((err == IA_CSS_SUCCESS) && acc_pipe) {
err = ia_css_pipeline_create(&acc_pipe->pipeline, acc_pipe->mode, acc_pipe->pipe_num, main_pipe->dvs_frame_delay);
}
/* DH regular multi pipe - not continuous mode: create the next pipelines too */
- if (!stream->config.continuous) {
+ if (!stream->config.continuous) {
int i;
+
for (i = 1; i < stream->num_pipes && IA_CSS_SUCCESS == err; i++) {
main_pipe = stream->pipes[i];
err = ia_css_pipeline_create(&main_pipe->pipeline,
enum ia_css_pipe_id pipe_id;
struct ia_css_pipe *main_pipe = NULL;
enum ia_css_err err = IA_CSS_SUCCESS;
- unsigned max_input_width = 0;
+ unsigned int max_input_width = 0;
IA_CSS_ENTER_PRIVATE("stream = %p", stream);
- if (stream == NULL) {
+ if (!stream) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
if (err != IA_CSS_SUCCESS)
goto ERR;
}
-
}
#if defined(USE_INPUT_SYSTEM_VERSION_2)
if (err != IA_CSS_SUCCESS)
goto ERR;
- if(copy_pipe) {
+ if (copy_pipe) {
err = create_host_copy_pipeline(copy_pipe, max_input_width,
main_pipe->continuous_frames[0]);
if (err != IA_CSS_SUCCESS)
goto ERR;
}
- if(capture_pipe) {
+ if (capture_pipe) {
err = create_host_capture_pipeline(capture_pipe);
if (err != IA_CSS_SUCCESS)
goto ERR;
/* DH regular multi pipe - not continuous mode: create the next pipelines too */
if (!stream->config.continuous) {
int i;
+
for (i = 1; i < stream->num_pipes && IA_CSS_SUCCESS == err; i++) {
switch (stream->pipes[i]->mode) {
case IA_CSS_PIPE_ID_PREVIEW:
struct ia_css_pipe *pipe,
bool copy_pipe)
{
- if (pipe == NULL) {
+ if (!pipe) {
IA_CSS_ERROR("NULL pipe parameter");
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
static void
pipe_global_init(void)
{
- uint8_t i;
+ u8 i;
my_css.pipe_counter = 0;
for (i = 0; i < IA_CSS_PIPELINE_NUM_MAX; i++) {
static enum ia_css_err
pipe_generate_pipe_num(const struct ia_css_pipe *pipe, unsigned int *pipe_number)
{
- const uint8_t INVALID_PIPE_NUM = (uint8_t)~(0);
- uint8_t pipe_num = INVALID_PIPE_NUM;
- uint8_t i;
+ const u8 INVALID_PIPE_NUM = (uint8_t)~(0);
+ u8 pipe_num = INVALID_PIPE_NUM;
+ u8 i;
- if (pipe == NULL) {
+ if (!pipe) {
IA_CSS_ERROR("NULL pipe parameter");
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
/* Assign a new pipe_num .... search for empty place */
for (i = 0; i < IA_CSS_PIPELINE_NUM_MAX; i++) {
- if (my_css.all_pipes[i] == NULL) {
+ if (!my_css.all_pipes[i]) {
/*position is reserved */
my_css.all_pipes[i] = (struct ia_css_pipe *)pipe;
pipe_num = i;
enum ia_css_err err = IA_CSS_SUCCESS;
struct ia_css_pipe *me;
- if (pipe == NULL) {
+ if (!pipe) {
IA_CSS_ERROR("NULL pipe parameter");
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
return err;
}
- err = pipe_generate_pipe_num(me, &(me->pipe_num));
+ err = pipe_generate_pipe_num(me, &me->pipe_num);
if (err != IA_CSS_SUCCESS) {
kfree(me);
return err;
find_pipe_by_num(uint32_t pipe_num)
{
unsigned int i;
- for (i = 0; i < IA_CSS_PIPELINE_NUM_MAX; i++){
+
+ for (i = 0; i < IA_CSS_PIPELINE_NUM_MAX; i++) {
if (my_css.all_pipes[i] &&
ia_css_pipe_get_pipe_num(my_css.all_pipes[i]) == pipe_num) {
return my_css.all_pipes[i];
return NULL;
}
-static void sh_css_pipe_free_acc_binaries (
+static void sh_css_pipe_free_acc_binaries(
struct ia_css_pipe *pipe)
{
struct ia_css_pipeline *pipeline;
struct ia_css_pipeline_stage *stage;
- assert(pipe != NULL);
- if (pipe == NULL) {
+ assert(pipe);
+ if (!pipe) {
IA_CSS_ERROR("NULL input pointer");
return;
}
ia_css_pipe_destroy(struct ia_css_pipe *pipe)
{
enum ia_css_err err = IA_CSS_SUCCESS;
+
IA_CSS_ENTER("pipe = %p", pipe);
- if (pipe == NULL) {
+ if (!pipe) {
IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
- if (pipe->stream != NULL) {
+ if (pipe->stream) {
IA_CSS_LOG("ia_css_stream_destroy not called!");
IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
pipe->cont_md_buffers);
if (pipe->pipe_settings.preview.copy_pipe) {
err = ia_css_pipe_destroy(pipe->pipe_settings.preview.copy_pipe);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_pipe_destroy(): "
- "destroyed internal copy pipe err=%d\n", err);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_pipe_destroy(): destroyed internal copy pipe err=%d\n",
+ err);
}
}
break;
pipe->cont_md_buffers);
if (pipe->pipe_settings.video.copy_pipe) {
err = ia_css_pipe_destroy(pipe->pipe_settings.video.copy_pipe);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_pipe_destroy(): "
- "destroyed internal copy pipe err=%d\n", err);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_pipe_destroy(): destroyed internal copy pipe err=%d\n",
+ err);
}
}
#ifndef ISP2401
sh_css_params_free_default_gdc_lut();
-
/* TODO: JB: implement decent check and handling of freeing mipi frames */
//assert(ref_count_mipi_allocation == 0); //mipi frames are not freed
/* cleanup generic data */
/* irq_infos can be NULL, but that would make the function useless */
/* assert(irq_infos != NULL); */
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_irq_translate() enter: irq_infos=%p\n",irq_infos);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_irq_translate() enter: irq_infos=%p\n", irq_infos);
while (status == hrt_isp_css_irq_status_more_irqs) {
status = virq_get_channel_id(&irq);
return IA_CSS_ERR_INTERNAL_ERROR;
#if WITH_PC_MONITORING
- sh_css_print("PC_MONITORING: %s() irq = %d, "
- "sh_binary_running set to 0\n", __func__, irq);
- sh_binary_running = 0 ;
+ sh_css_print("PC_MONITORING: %s() irq = %d, sh_binary_running set to 0\n",
+ __func__, irq);
+ sh_binary_running = 0;
#endif
switch (irq) {
if (irq_infos)
*irq_infos = infos;
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_irq_translate() "
- "leave: irq_infos=%u\n", infos);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_irq_translate() leave: irq_infos=%u\n",
+ infos);
return IA_CSS_SUCCESS;
}
bool enable)
{
virq_id_t irq = N_virq_id;
+
IA_CSS_ENTER("info=%d, enable=%d", info, enable);
switch (info) {
sh_css_get_sw_interrupt_value(unsigned int irq)
{
unsigned int irq_value;
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_get_sw_interrupt_value() enter: irq=%d\n",irq);
+
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_get_sw_interrupt_value() enter: irq=%d\n", irq);
irq_value = sh_css_sp_get_sw_interrupt_value(irq);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_get_sw_interrupt_value() leave: irq_value=%d\n",irq_value);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_get_sw_interrupt_value() leave: irq_value=%d\n", irq_value);
return irq_value;
}
struct ia_css_binary_descr copy_descr;
/* next_binary can be NULL */
- assert(pipe != NULL);
- assert(copy_binary != NULL);
+ assert(pipe);
+ assert(copy_binary);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"load_copy_binary() enter:\n");
- if (next_binary != NULL) {
+ if (next_binary) {
copy_out_info = next_binary->in_frame_info;
left_padding = next_binary->left_padding;
} else {
}
ia_css_pipe_get_copy_binarydesc(pipe, ©_descr,
- ©_in_info, ©_out_info, (next_binary != NULL) ? NULL : NULL/*TODO: ©_vf_info*/);
+ ©_in_info, ©_out_info, (next_binary) ? NULL : NULL/*TODO: ©_vf_info*/);
err = ia_css_binary_find(©_descr, copy_binary);
if (err != IA_CSS_SUCCESS)
return err;
IA_CSS_ENTER_PRIVATE("pipe = %p, init_time = %d", pipe, init_time);
- if ((pipe == NULL) || (pipe->stream == NULL)) {
+ if ((!pipe) || (!pipe->stream)) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
ref_info = pipe->pipe_settings.preview.preview_binary.in_frame_info;
} else if (pipe_id == IA_CSS_PIPE_ID_VIDEO) {
ref_info = pipe->pipe_settings.video.video_binary.in_frame_info;
- }
- else {
+ } else {
/* should not happen */
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INTERNAL_ERROR);
return IA_CSS_ERR_INTERNAL_ERROR;
enum ia_css_err
ia_css_alloc_continuous_frame_remain(struct ia_css_stream *stream)
{
- if (stream == NULL)
+ if (!stream)
return IA_CSS_ERR_INVALID_ARGUMENTS;
return alloc_continuous_frames(stream->continuous_pipe, false);
}
struct ia_css_preview_settings *mycs = &pipe->pipe_settings.preview;
IA_CSS_ENTER_PRIVATE("");
- assert(pipe != NULL);
- assert(pipe->stream != NULL);
+ assert(pipe);
+ assert(pipe->stream);
assert(pipe->mode == IA_CSS_PIPE_ID_PREVIEW);
online = pipe->stream->config.online;
*/
if (need_vf_pp &&
(mycs->preview_binary.out_frame_info[0].format != IA_CSS_FRAME_FORMAT_YUV_LINE)) {
-
/* Preview step 2 */
if (pipe->vf_yuv_ds_input_info.res.width)
prev_vf_info = pipe->vf_yuv_ds_input_info;
{
IA_CSS_ENTER_PRIVATE("pipe = %p", pipe);
- if ((pipe == NULL) || (pipe->mode != IA_CSS_PIPE_ID_PREVIEW)) {
+ if ((!pipe) || (pipe->mode != IA_CSS_PIPE_ID_PREVIEW)) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
for (; fw; fw = fw->next) {
const struct ia_css_fw_info *info = fw;
+
if (info->info.isp.sp.enable.output)
last_fw = fw;
}
struct ia_css_frame *out[IA_CSS_BINARY_MAX_OUTPUT_PORTS] = {NULL};
struct ia_css_frame *in = NULL;
struct ia_css_frame *vf = NULL;
+
if ((fw == last_fw) && (fw->info.isp.sp.enable.out_frame != 0)) {
out[0] = out_frame;
}
struct ia_css_binary *vf_pp_binary,
struct ia_css_pipeline_stage **vf_pp_stage)
{
-
struct ia_css_pipeline *me = NULL;
const struct ia_css_fw_info *last_fw = NULL;
enum ia_css_err err = IA_CSS_SUCCESS;
/* out_frame can be NULL ??? */
- if (pipe == NULL)
+ if (!pipe)
return IA_CSS_ERR_INVALID_ARGUMENTS;
- if (in_frame == NULL)
+ if (!in_frame)
return IA_CSS_ERR_INVALID_ARGUMENTS;
- if (vf_pp_binary == NULL)
+ if (!vf_pp_binary)
return IA_CSS_ERR_INVALID_ARGUMENTS;
- if (vf_pp_stage == NULL)
+ if (!vf_pp_stage)
return IA_CSS_ERR_INVALID_ARGUMENTS;
ia_css_pipe_util_create_output_frames(out_frames);
ia_css_pipe_util_set_output_frames(out_frames, 0, NULL);
ia_css_pipe_get_generic_stage_desc(&stage_desc, vf_pp_binary,
out_frames, in_frame, NULL);
- } else{
+ } else {
ia_css_pipe_util_set_output_frames(out_frames, 0, out_frame);
ia_css_pipe_get_generic_stage_desc(&stage_desc, vf_pp_binary,
out_frames, in_frame, NULL);
struct ia_css_pipeline_stage_desc stage_desc;
/* out_frame can be NULL ??? */
- assert(in_frame != NULL);
- assert(pipe != NULL);
- assert(me != NULL);
- assert(yuv_scaler_binary != NULL);
- assert(pre_vf_pp_stage != NULL);
+ assert(in_frame);
+ assert(pipe);
+ assert(me);
+ assert(yuv_scaler_binary);
+ assert(pre_vf_pp_stage);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"add_yuv_scaler_stage() enter:\n");
last_fw = last_output_firmware(pipe->output_stage);
- if(last_fw) {
+ if (last_fw) {
ia_css_pipe_util_set_output_frames(out_frames, 0, NULL);
ia_css_pipe_get_generic_stage_desc(&stage_desc,
yuv_scaler_binary, out_frames, in_frame, vf_frame);
struct ia_css_pipeline_stage_desc stage_desc;
/* out_frame can be NULL ??? */
- assert(in_frame != NULL);
- assert(pipe != NULL);
- assert(me != NULL);
- assert(capture_pp_binary != NULL);
- assert(capture_pp_stage != NULL);
+ assert(in_frame);
+ assert(pipe);
+ assert(me);
+ assert(capture_pp_binary);
+ assert(capture_pp_stage);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"add_capture_pp_stage() enter:\n");
&capture_pp_binary->vf_frame_info);
if (err != IA_CSS_SUCCESS)
return err;
- if(last_fw) {
+ if (last_fw) {
ia_css_pipe_util_set_output_frames(out_frames, 0, NULL);
ia_css_pipe_get_generic_stage_desc(&stage_desc,
capture_pp_binary, out_frames, NULL, vf_frame);
unsigned int thread_id;
enum sh_css_queue_id queue_id;
- assert(vf_frame != NULL);
+ assert(vf_frame);
sh_css_pipe_get_viewfinder_frame_info(pipe, &vf_frame->info, idx);
vf_frame->contiguous = false;
#ifdef USE_INPUT_SYSTEM_VERSION_2401
static unsigned int
-get_crop_lines_for_bayer_order (
+get_crop_lines_for_bayer_order(
const struct ia_css_stream_config *config)
{
- assert(config != NULL);
- if ((IA_CSS_BAYER_ORDER_BGGR == config->input_config.bayer_order)
- || (IA_CSS_BAYER_ORDER_GBRG == config->input_config.bayer_order))
+ assert(config);
+ if ((config->input_config.bayer_order == IA_CSS_BAYER_ORDER_BGGR)
+ || (config->input_config.bayer_order == IA_CSS_BAYER_ORDER_GBRG))
return 1;
return 0;
}
static unsigned int
-get_crop_columns_for_bayer_order (
+get_crop_columns_for_bayer_order(
const struct ia_css_stream_config *config)
{
- assert(config != NULL);
- if ((IA_CSS_BAYER_ORDER_RGGB == config->input_config.bayer_order)
- || (IA_CSS_BAYER_ORDER_GBRG == config->input_config.bayer_order))
+ assert(config);
+ if ((config->input_config.bayer_order == IA_CSS_BAYER_ORDER_RGGB)
+ || (config->input_config.bayer_order == IA_CSS_BAYER_ORDER_GBRG))
return 1;
return 0;
}
void
-ia_css_get_crop_offsets (
+ia_css_get_crop_offsets(
struct ia_css_pipe *pipe,
struct ia_css_frame_info *in_frame)
{
unsigned int extra_row = 0, extra_col = 0;
unsigned int min_reqd_height, min_reqd_width;
- assert(pipe != NULL);
- assert(pipe->stream != NULL);
- assert(in_frame != NULL);
+ assert(pipe);
+ assert(pipe->stream);
+ assert(in_frame);
IA_CSS_ENTER_PRIVATE("pipe = %p effective_wd = %u effective_ht = %u",
pipe, pipe->config.input_effective_res.width,
unsigned int thread_id;
enum sh_css_queue_id queue_id;
- assert(frame != NULL);
+ assert(frame);
in_frame = frame;
in_frame->info.format = format;
IA_CSS_FRAME_FORMAT_RAW_PACKED : IA_CSS_FRAME_FORMAT_RAW;
#endif
-
in_frame->info.res.width = pipe->stream->config.input_config.input_res.width;
in_frame->info.res.height = pipe->stream->config.input_config.input_res.height;
in_frame->info.raw_bit_depth =
unsigned int thread_id;
enum sh_css_queue_id queue_id;
- assert(out_frame != NULL);
+ assert(out_frame);
sh_css_pipe_get_output_frame_info(pipe, &out_frame->info, idx);
out_frame->contiguous = false;
bool need_copy = false;
bool need_vf_pp = false;
bool need_yuv_pp = false;
- unsigned num_output_pins;
+ unsigned int num_output_pins;
bool need_in_frameinfo_memory = false;
unsigned int i, num_yuv_scaler;
bool *is_output_stage = NULL;
IA_CSS_ENTER_PRIVATE("pipe = %p", pipe);
- if ((pipe == NULL) || (pipe->stream == NULL) || (pipe->mode != IA_CSS_PIPE_ID_VIDEO)) {
+ if ((!pipe) || (!pipe->stream) || (pipe->mode != IA_CSS_PIPE_ID_VIDEO)) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
num_yuv_scaler = pipe->pipe_settings.video.num_yuv_scaler;
is_output_stage = pipe->pipe_settings.video.is_output_stage;
- need_copy = (copy_binary != NULL && copy_binary->info != NULL);
- need_vf_pp = (vf_pp_binary != NULL && vf_pp_binary->info != NULL);
- need_yuv_pp = (yuv_scaler_binary != NULL && yuv_scaler_binary->info != NULL);
+ need_copy = (copy_binary && copy_binary->info);
+ need_vf_pp = (vf_pp_binary && vf_pp_binary->info);
+ need_yuv_pp = (yuv_scaler_binary && yuv_scaler_binary->info);
if (need_copy) {
ia_css_pipe_util_set_output_frames(out_frames, 0, NULL);
/* when the video binary supports a second output pin,
it can directly produce the vf_frame. */
- if(need_vf_pp) {
+ if (need_vf_pp) {
ia_css_pipe_get_generic_stage_desc(&stage_desc, video_binary,
out_frames, in_frame, NULL);
} else {
goto ERR;
/* If we use copy iso video, the input must be yuv iso raw */
- if(video_stage) {
+ if (video_stage) {
video_stage->args.copy_vf =
video_binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_COPY;
video_stage->args.copy_output = video_stage->args.copy_vf;
if ((pipe->config.acc_extension->info.isp.sp.enable.output) &&
(pipe->config.acc_extension->info.isp.sp.enable.in_frame) &&
(pipe->config.acc_extension->info.isp.sp.enable.out_frame)) {
-
/* In/Out Frame mapping to support output frame extension.*/
out = video_stage->args.out_frame[0];
- err = ia_css_frame_allocate_from_info(&in, &(pipe->output_info[0]));
+ err = ia_css_frame_allocate_from_info(&in, &pipe->output_info[0]);
if (err != IA_CSS_SUCCESS)
goto ERR;
video_stage->args.out_frame[0] = in;
}
- err = add_firmwares( me, video_binary, pipe->output_stage,
+ err = add_firmwares(me, video_binary, pipe->output_stage,
last_output_firmware(pipe->output_stage),
IA_CSS_BINARY_MODE_VIDEO,
in, out, NULL, &video_stage, NULL);
unsigned int i;
IA_CSS_ENTER_PRIVATE("pipe = %p", pipe);
- if ((pipe == NULL) || (pipe->stream == NULL)) {
+ if ((!pipe) || (!pipe->stream)) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
pipe->pipeline.pipe_qos_config = 0;
fw = pipe->vf_stage;
- for (i = 0; fw; fw = fw->next){
+ for (i = 0; fw; fw = fw->next) {
err = sh_css_pipeline_add_acc_stage(&pipe->pipeline, fw);
if (err != IA_CSS_SUCCESS)
goto ERR;
}
- for (i=0; i<pipe->config.num_acc_stages; i++) {
+ for (i = 0; i < pipe->config.num_acc_stages; i++) {
struct ia_css_fw_info *fw = pipe->config.acc_stages[i];
+
err = sh_css_pipeline_add_acc_stage(&pipe->pipeline, fw);
if (err != IA_CSS_SUCCESS)
goto ERR;
#endif
IA_CSS_ENTER_PRIVATE("pipe = %p", pipe);
- if ((pipe == NULL) || (pipe->stream == NULL) || (pipe->mode != IA_CSS_PIPE_ID_PREVIEW)) {
+ if ((!pipe) || (!pipe->stream) || (pipe->mode != IA_CSS_PIPE_ID_PREVIEW)) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
-
ia_css_pipe_util_create_output_frames(out_frames);
/* pipeline already created as part of create_host_pipeline_structure */
me = &pipe->pipeline;
/* When continuous is enabled, configure in_frame with the
* last pipe, which is the copy pipe.
*/
- if (continuous || !online){
+ if (continuous || !online) {
in_frame = pipe->stream->last_pipe->continuous_frames[0];
}
#else
static enum ia_css_err
preview_start(struct ia_css_pipe *pipe)
{
- struct ia_css_pipeline *me ;
+ struct ia_css_pipeline *me;
struct ia_css_binary *copy_binary, *preview_binary, *vf_pp_binary = NULL;
enum ia_css_err err = IA_CSS_SUCCESS;
struct ia_css_pipe *copy_pipe, *capture_pipe;
enum ia_css_input_mode preview_pipe_input_mode;
IA_CSS_ENTER_PRIVATE("pipe = %p", pipe);
- if ((pipe == NULL) || (pipe->stream == NULL) || (pipe->mode != IA_CSS_PIPE_ID_PREVIEW)) {
+ if ((!pipe) || (!pipe->stream) || (pipe->mode != IA_CSS_PIPE_ID_PREVIEW)) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
#ifndef ISP2401
);
#else
- &pipe->config.internal_frame_origin_bqs_on_sctbl,
+ & pipe->config.internal_frame_origin_bqs_on_sctbl,
pipe->stream->isp_params_configs);
#endif
#ifndef ISP2401
);
#else
- &capture_pipe->config.internal_frame_origin_bqs_on_sctbl,
+ & capture_pipe->config.internal_frame_origin_bqs_on_sctbl,
capture_pipe->stream->isp_params_configs);
#endif
}
if (acc_pipe) {
sh_css_sp_init_pipeline(&acc_pipe->pipeline,
IA_CSS_PIPE_ID_ACC,
- (uint8_t) ia_css_pipe_get_pipe_num(acc_pipe),
+ (uint8_t)ia_css_pipe_get_pipe_num(acc_pipe),
false,
pipe->stream->config.pixels_per_clock == 2,
false, /* continuous */
#endif
#if !defined(HAS_NO_INPUT_SYSTEM)
#ifndef ISP2401
- , (enum mipi_port_id) 0
+ , (enum mipi_port_id)0
#else
- (enum mipi_port_id) 0,
+ (enum mipi_port_id)0,
#endif
#endif
#ifndef ISP2401
);
#else
- &pipe->config.internal_frame_origin_bqs_on_sctbl,
+ & pipe->config.internal_frame_origin_bqs_on_sctbl,
pipe->stream->isp_params_configs);
#endif
}
IA_CSS_ENTER("pipe=%p, buffer=%p", pipe, buffer);
- if ((pipe == NULL) || (buffer == NULL)) {
+ if ((!pipe) || (!buffer)) {
IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
#if 0
if (buf_type == IA_CSS_BUFFER_TYPE_OUTPUT_FRAME) {
bool found_pipe = false;
+
for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) {
if ((buffer->data.frame->info.res.width == pipe->output_info[i].res.width) &&
(buffer->data.frame->info.res.height == pipe->output_info[i].res.height)) {
}
if (buf_type == IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME) {
bool found_pipe = false;
+
for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) {
if ((buffer->data.frame->info.res.width == pipe->vf_output_info[i].res.width) &&
(buffer->data.frame->info.res.height == pipe->vf_output_info[i].res.height)) {
IA_CSS_LOG("pipe_id=%d, buf_type=%d", pipe_id, buf_type);
-
assert(pipe_id < IA_CSS_PIPE_ID_NUM);
assert(buf_type < IA_CSS_NUM_DYNAMIC_BUFFER_TYPE);
if ((buf_type == IA_CSS_BUFFER_TYPE_INVALID) ||
return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE;
}
-
pipeline = &pipe->pipeline;
- assert(pipeline != NULL ||
+ assert(pipeline ||
pipe_id == IA_CSS_PIPE_ID_COPY ||
pipe_id == IA_CSS_PIPE_ID_ACC);
ddr_buffer.timing_data = buffer->timing_data;
if (buf_type == IA_CSS_BUFFER_TYPE_3A_STATISTICS) {
- if (buffer->data.stats_3a == NULL) {
+ if (!buffer->data.stats_3a) {
IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
ddr_buffer.kernel_ptr = HOST_ADDRESS(buffer->data.stats_3a);
ddr_buffer.payload.s3a = *buffer->data.stats_3a;
} else if (buf_type == IA_CSS_BUFFER_TYPE_DIS_STATISTICS) {
- if (buffer->data.stats_dvs == NULL) {
+ if (!buffer->data.stats_dvs) {
IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
ddr_buffer.kernel_ptr = HOST_ADDRESS(buffer->data.stats_dvs);
ddr_buffer.payload.dis = *buffer->data.stats_dvs;
} else if (buf_type == IA_CSS_BUFFER_TYPE_METADATA) {
- if (buffer->data.metadata == NULL) {
+ if (!buffer->data.metadata) {
IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
|| (buf_type == IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME)
|| (buf_type == IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME)
|| (buf_type == IA_CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME)) {
- if (buffer->data.frame == NULL) {
+ if (!buffer->data.frame) {
IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
"ia_css_pipe_enqueue_buffer() buf_type=%d, data(DDR address)=0x%x\n",
buf_type, buffer->data.frame->data);
-
#if CONFIG_ON_FRAME_ENQUEUE()
return_err = set_config_on_frame_enqueue(
&buffer->data.frame->info,
&ddr_buffer.payload.frame);
- if (IA_CSS_SUCCESS != return_err) {
+ if (return_err != IA_CSS_SUCCESS) {
IA_CSS_LEAVE_ERR(return_err);
return return_err;
}
/* TODO: change next to correct pool for optimization */
ia_css_rmgr_acq_vbuf(hmm_buffer_pool, &h_vbuf);
- assert(h_vbuf != NULL);
+ assert(h_vbuf);
assert(h_vbuf->vptr != 0x0);
- if ((h_vbuf == NULL) || (h_vbuf->vptr == 0x0)) {
+ if ((!h_vbuf) || (h_vbuf->vptr == 0x0)) {
IA_CSS_LEAVE_ERR(IA_CSS_ERR_INTERNAL_ERROR);
return IA_CSS_ERR_INTERNAL_ERROR;
}
if ((buf_type == IA_CSS_BUFFER_TYPE_3A_STATISTICS)
|| (buf_type == IA_CSS_BUFFER_TYPE_DIS_STATISTICS)
|| (buf_type == IA_CSS_BUFFER_TYPE_LACE_STATISTICS)) {
- if (pipeline == NULL) {
+ if (!pipeline) {
ia_css_rmgr_rel_vbuf(hmm_buffer_pool, &h_vbuf);
IA_CSS_LOG("pipeline is empty!");
IA_CSS_LEAVE_ERR(IA_CSS_ERR_INTERNAL_ERROR);
|| (buf_type == IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME)
|| (buf_type == IA_CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME)
|| (buf_type == IA_CSS_BUFFER_TYPE_METADATA)) {
-
return_err = ia_css_bufq_enqueue_buffer(thread_id,
queue_id,
(uint32_t)h_vbuf->vptr);
#if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS)
- if ((return_err == IA_CSS_SUCCESS) && (IA_CSS_BUFFER_TYPE_OUTPUT_FRAME == buf_type)) {
+ if ((return_err == IA_CSS_SUCCESS) && (buf_type == IA_CSS_BUFFER_TYPE_OUTPUT_FRAME)) {
IA_CSS_LOG("pfp: enqueued OF %d to q %d thread %d",
ddr_buffer.payload.frame.frame_data,
queue_id, thread_id);
}
#endif
-
}
if (return_err == IA_CSS_SUCCESS) {
IA_CSS_ENTER("pipe=%p, buffer=%p", pipe, buffer);
- if ((pipe == NULL) || (buffer == NULL)) {
+ if ((!pipe) || (!buffer)) {
IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
/* Validate the ddr_buffer_addr and buf_type */
hmm_buffer_record = sh_css_hmm_buffer_record_validate(
ddr_buffer_addr, buf_type);
- if (hmm_buffer_record != NULL) {
+ if (hmm_buffer_record) {
/* valid hmm_buffer_record found. Save the kernel_ptr
* for validation after performing mmgr_load. The
* vbuf handle and buffer_record can be released.
case IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME:
if ((pipe) && (pipe->stop_requested == true))
{
-
#if defined(USE_INPUT_SYSTEM_VERSION_2)
/* free mipi frames only for old input system
* for 2401 it is done in ia_css_stream_destroy call
}
case IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME:
case IA_CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME:
- frame = (struct ia_css_frame*)HOST_ADDRESS(ddr_buffer.kernel_ptr);
+ frame = (struct ia_css_frame *)HOST_ADDRESS(ddr_buffer.kernel_ptr);
buffer->data.frame = frame;
buffer->exp_id = ddr_buffer.payload.frame.exp_id;
frame->exp_id = ddr_buffer.payload.frame.exp_id;
#endif
}
#if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS)
- if (IA_CSS_BUFFER_TYPE_OUTPUT_FRAME == buf_type) {
+ if (buf_type == IA_CSS_BUFFER_TYPE_OUTPUT_FRAME) {
IA_CSS_LOG("pfp: dequeued OF %d with config id %d thread %d",
frame->data, frame->isp_config_id, thread_id);
}
break;
case IA_CSS_BUFFER_TYPE_3A_STATISTICS:
buffer->data.stats_3a =
- (struct ia_css_isp_3a_statistics*)HOST_ADDRESS(ddr_buffer.kernel_ptr);
+ (struct ia_css_isp_3a_statistics *)HOST_ADDRESS(ddr_buffer.kernel_ptr);
buffer->exp_id = ddr_buffer.payload.s3a.exp_id;
buffer->data.stats_3a->exp_id = ddr_buffer.payload.s3a.exp_id;
buffer->data.stats_3a->isp_config_id = ddr_buffer.payload.s3a.isp_config_id;
break;
case IA_CSS_BUFFER_TYPE_DIS_STATISTICS:
buffer->data.stats_dvs =
- (struct ia_css_isp_dvs_statistics*)
+ (struct ia_css_isp_dvs_statistics *)
HOST_ADDRESS(ddr_buffer.kernel_ptr);
buffer->exp_id = ddr_buffer.payload.dis.exp_id;
buffer->data.stats_dvs->exp_id = ddr_buffer.payload.dis.exp_id;
break;
case IA_CSS_BUFFER_TYPE_METADATA:
buffer->data.metadata =
- (struct ia_css_metadata*)HOST_ADDRESS(ddr_buffer.kernel_ptr);
+ (struct ia_css_metadata *)HOST_ADDRESS(ddr_buffer.kernel_ptr);
buffer->exp_id = ddr_buffer.payload.metadata.exp_id;
buffer->data.metadata->exp_id = ddr_buffer.payload.metadata.exp_id;
break;
* Tell the SP which queues are not full,
* by sending the software event.
*/
- if (return_err == IA_CSS_SUCCESS){
+ if (return_err == IA_CSS_SUCCESS) {
if (!sh_css_sp_is_running()) {
IA_CSS_LOG("SP is not running!");
IA_CSS_LEAVE_ERR(IA_CSS_ERR_RESOURCE_NOT_AVAILABLE);
ia_css_dequeue_psys_event(struct ia_css_event *event)
{
enum ia_css_pipe_id pipe_id = 0;
- uint8_t payload[4] = {0,0,0,0};
+ u8 payload[4] = {0, 0, 0, 0};
enum ia_css_err ret_err;
/*TODO:
* We skip the IA_CSS_ENTER logging call
* to avoid flooding the logs when the host application
* uses polling. */
- if (event == NULL)
+ if (!event)
return IA_CSS_ERR_INVALID_ARGUMENTS;
if (!sh_css_sp_is_running()) {
if (event->type == IA_CSS_EVENT_TYPE_TIMER) {
/* timer event ??? get the 2nd event and decode the data into the event struct */
- uint32_t tmp_data;
+ u32 tmp_data;
/* 1st event: LSB 16-bit timer data and code */
event->timer_data = ((payload[1] & 0xFF) | ((payload[3] & 0xFF) << 8));
event->timer_code = payload[2];
if (event->type == IA_CSS_EVENT_TYPE_FRAME_TAGGED) {
/* find the capture pipe that goes with this */
int i, n;
+
n = event->pipe->stream->num_pipes;
for (i = 0; i < n; i++) {
struct ia_css_pipe *p =
}
if (event->type == IA_CSS_EVENT_TYPE_ACC_STAGE_COMPLETE) {
/* payload[3] contains the acc fw handle. */
- uint32_t stage_num = (uint32_t)payload[3];
+ u32 stage_num = (uint32_t)payload[3];
+
ret_err = ia_css_pipeline_get_fw_from_stage(
- &(event->pipe->pipeline),
+ &event->pipe->pipeline,
stage_num,
- &(event->fw_handle));
+ &event->fw_handle);
if (ret_err != IA_CSS_SUCCESS) {
IA_CSS_ERROR("Invalid stage num received for ACC event. stage_num:%u",
stage_num);
enum ia_css_err
ia_css_dequeue_isys_event(struct ia_css_event *event)
{
- uint8_t payload[4] = {0, 0, 0, 0};
+ u8 payload[4] = {0, 0, 0, 0};
enum ia_css_err err = IA_CSS_SUCCESS;
/* We skip the IA_CSS_ENTER logging call
* to avoid flooding the logs when the host application
* uses polling. */
- if (event == NULL)
+ if (!event)
return IA_CSS_ERR_INVALID_ARGUMENTS;
if (!sh_css_sp_is_running()) {
static void
acc_start(struct ia_css_pipe *pipe)
{
- assert(pipe != NULL);
- assert(pipe->stream != NULL);
+ assert(pipe);
+ assert(pipe->stream);
start_pipe(pipe, SH_CSS_PIPE_CONFIG_OVRD_NO_OVRD,
pipe->stream->config.mode);
IA_CSS_ENTER_PRIVATE("stream = %p", stream);
- if (stream == NULL) {
+ if (!stream) {
IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
pipe = stream->last_pipe;
- if (pipe == NULL) {
+ if (!pipe) {
IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
pipe_id = pipe->mode;
- if(stream->started == true) {
+ if (stream->started == true) {
IA_CSS_WARNING("Cannot start stream that is already started");
IA_CSS_LEAVE_ERR(err);
return err;
/* DH regular multi pipe - not continuous mode: start the next pipes too */
if (!stream->config.continuous) {
int i;
+
for (i = 1; i < stream->num_pipes && IA_CSS_SUCCESS == err ; i++) {
switch (stream->pipes[i]->mode) {
case IA_CSS_PIPE_ID_PREVIEW:
/* DH regular multi pipe - not continuous mode: enqueue event to the next pipes too */
if (!stream->config.continuous) {
int i;
+
for (i = 1; i < stream->num_pipes; i++) {
ia_css_pipeline_get_sp_thread_id(
ia_css_pipe_get_pipe_num(stream->pipes[i]),
else if (pipe_id == IA_CSS_PIPE_ID_VIDEO)
copy_pipe = pipe->pipe_settings.video.copy_pipe;
- if (copy_pipe == NULL) {
+ if (!copy_pipe) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INTERNAL_ERROR);
return IA_CSS_ERR_INTERNAL_ERROR;
}
}
if (pipe->stream->cont_capt) {
struct ia_css_pipe *capture_pipe = NULL;
+
if (pipe_id == IA_CSS_PIPE_ID_PREVIEW)
capture_pipe = pipe->pipe_settings.preview.capture_pipe;
else if (pipe_id == IA_CSS_PIPE_ID_VIDEO)
capture_pipe = pipe->pipe_settings.video.capture_pipe;
- if (capture_pipe == NULL) {
+ if (!capture_pipe) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INTERNAL_ERROR);
return IA_CSS_ERR_INTERNAL_ERROR;
}
/* in case of PREVIEW mode, check whether QOS acc_pipe is available, then start the qos pipe */
if (pipe_id == IA_CSS_PIPE_ID_PREVIEW) {
struct ia_css_pipe *acc_pipe = NULL;
+
acc_pipe = pipe->pipe_settings.preview.acc_pipe;
- if (acc_pipe){
+ if (acc_pipe) {
ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(acc_pipe), &thread_id);
/* by the time we reach here q is initialized and handle is available.*/
ia_css_bufq_enqueue_psys_event(
IA_CSS_PSYS_SW_EVENT_START_STREAM,
- (uint8_t) thread_id, 0, 0);
+ (uint8_t)thread_id, 0, 0);
}
}
sh_css_enable_cont_capt(bool enable, bool stop_copy_preview)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
- "sh_css_enable_cont_capt() enter: enable=%d\n", enable);
+ "sh_css_enable_cont_capt() enter: enable=%d\n", enable);
//my_css.cont_capt = enable;
my_css.stop_copy_preview = stop_copy_preview;
}
#ifndef ISP2401
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_continuous_is_enabled() enter: pipe_num=%d\n", pipe_num);
#else
- assert(stream != NULL);
- if (stream == NULL) {
+ assert(stream);
+ if (!stream) {
IA_CSS_LOG("stream does NOT exist!");
err = IA_CSS_ERR_INTERNAL_ERROR;
goto ERR;
}
#else
main_pipe = stream->last_pipe;
- assert(main_pipe != NULL);
- if (main_pipe == NULL) {
+ assert(main_pipe);
+ if (!main_pipe) {
IA_CSS_LOG("main_pipe does NOT exist!");
err = IA_CSS_ERR_INTERNAL_ERROR;
goto ERR;
enum ia_css_err
ia_css_stream_get_max_buffer_depth(struct ia_css_stream *stream, int *buffer_depth)
{
- if (buffer_depth == NULL)
+ if (!buffer_depth)
return IA_CSS_ERR_INVALID_ARGUMENTS;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_get_max_buffer_depth() enter: void\n");
(void)stream;
enum ia_css_err
ia_css_stream_set_buffer_depth(struct ia_css_stream *stream, int buffer_depth)
{
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_set_buffer_depth() enter: num_frames=%d\n",buffer_depth);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_set_buffer_depth() enter: num_frames=%d\n", buffer_depth);
(void)stream;
if (buffer_depth > NUM_CONTINUOUS_FRAMES || buffer_depth < 1)
return IA_CSS_ERR_INVALID_ARGUMENTS;
enum ia_css_err
ia_css_stream_get_buffer_depth(struct ia_css_stream *stream, int *buffer_depth)
{
- if (buffer_depth == NULL)
+ if (!buffer_depth)
return IA_CSS_ERR_INVALID_ARGUMENTS;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_get_buffer_depth() enter: void\n");
#else
copy_pipe = main_pipe->pipe_settings.video.copy_pipe;
/* return the error code if "Copy Pipe" does NOT exist */
- assert(copy_pipe != NULL);
- if (copy_pipe == NULL) {
+ assert(copy_pipe);
+ if (!copy_pipe) {
IA_CSS_LOG("Copy Pipe does NOT exist!");
err = IA_CSS_ERR_INTERNAL_ERROR;
goto ERR;
int i;
- assert(stream != NULL);
- if (stream == NULL) {
+ assert(stream);
+ if (!stream) {
IA_CSS_LOG("stream does NOT exist!");
rval = false;
goto RET;
}
main_pipe = stream->last_pipe;
- assert(main_pipe != NULL);
+ assert(main_pipe);
- if (main_pipe == NULL) {
+ if (!main_pipe) {
IA_CSS_LOG("main_pipe does NOT exist!");
rval = false;
goto RET;
copy_pipe = main_pipe->pipe_settings.video.copy_pipe;
/* return if "Copy Pipe" does NOT exist */
- assert(copy_pipe != NULL);
- if (copy_pipe == NULL) {
+ assert(copy_pipe);
+ if (!copy_pipe) {
IA_CSS_LOG("Copy Pipe does NOT exist!");
rval = false;
enum ia_css_err
ia_css_stream_get_max_buffer_depth(struct ia_css_stream *stream, int *buffer_depth)
{
- if (buffer_depth == NULL)
+ if (!buffer_depth)
return IA_CSS_ERR_INVALID_ARGUMENTS;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_get_max_buffer_depth() enter: void\n");
(void)stream;
enum ia_css_err
ia_css_stream_set_buffer_depth(struct ia_css_stream *stream, int buffer_depth)
{
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_set_buffer_depth() enter: num_frames=%d\n",buffer_depth);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_set_buffer_depth() enter: num_frames=%d\n", buffer_depth);
(void)stream;
if (buffer_depth > NUM_CONTINUOUS_FRAMES || buffer_depth < 1)
return IA_CSS_ERR_INVALID_ARGUMENTS;
enum ia_css_err
ia_css_stream_get_buffer_depth(struct ia_css_stream *stream, int *buffer_depth)
{
- if (buffer_depth == NULL)
+ if (!buffer_depth)
return IA_CSS_ERR_INVALID_ARGUMENTS;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_get_buffer_depth() enter: void\n");
#endif
IA_CSS_ENTER_PRIVATE("pipe = %p, width = %d, height = %d, paddaed width = %d, format = %d, idx = %d",
pipe, width, height, padded_width, format, idx);
- if (pipe == NULL) {
+ if (!pipe) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
enum ia_css_err err = IA_CSS_SUCCESS;
struct ia_css_binary *binary = NULL;
- assert(pipe != NULL);
+ assert(pipe);
#ifndef ISP2401
- assert(info != NULL);
+ assert(info);
#else
- assert(shading_info != NULL);
- assert(pipe_config != NULL);
+ assert(shading_info);
+ assert(pipe_config);
#endif
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"sh_css_pipe_get_shading_info() enter:\n");
enum ia_css_err err = IA_CSS_SUCCESS;
struct ia_css_binary *binary = NULL;
- assert(pipe != NULL);
- assert(info != NULL);
+ assert(pipe);
+ assert(info);
IA_CSS_ENTER_PRIVATE("");
sizeof(info->dvs_grid.dvs_stat_grid_info));
}
- if (binary != NULL) {
+ if (binary) {
/* copy pipe does not have ISP binary*/
info->isp_in_width = binary->internal_frame_info.res.width;
info->isp_in_height = binary->internal_frame_info.res.height;
#error "Unknown VAMEM version"
#endif
-ERR:
+ERR :
IA_CSS_LEAVE_ERR_PRIVATE(err);
return err;
}
}
supported_formats = pipe->pipe_settings.video.video_binary.info->output_formats;
- number_of_formats = sizeof(pipe->pipe_settings.video.video_binary.info->output_formats)/sizeof(enum ia_css_frame_format);
+ number_of_formats = sizeof(pipe->pipe_settings.video.video_binary.info->output_formats) / sizeof(enum ia_css_frame_format);
for (i = 0; i < number_of_formats && !found; i++) {
if (supported_formats[i] == format) {
enum ia_css_err err = IA_CSS_SUCCESS;
bool continuous = pipe->stream->config.continuous;
unsigned int i;
- unsigned num_output_pins;
+ unsigned int num_output_pins;
struct ia_css_frame_info video_bin_out_info;
bool need_scaler = false;
bool vf_res_different_than_output = false;
struct ia_css_video_settings *mycs = &pipe->pipe_settings.video;
IA_CSS_ENTER_PRIVATE("");
- assert(pipe != NULL);
+ assert(pipe);
assert(pipe->mode == IA_CSS_PIPE_ID_VIDEO);
/* we only test the video_binary because offline video doesn't need a
* vf_pp binary and online does not (always use) the copy_binary.
pipe_out_info = &pipe->output_info[0];
pipe_vf_out_info = &pipe->vf_output_info[0];
- assert(pipe_out_info != NULL);
+ assert(pipe_out_info);
/*
* There is no explicit input format requirement for raw or yuv
video_bin_out_info = *pipe_out_info;
/* Video */
- if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]){
+ if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]) {
video_vf_info = pipe_vf_out_info;
vf_res_different_than_output = (video_vf_info->res.width != video_bin_out_info.res.width) ||
(video_vf_info->res.height != video_bin_out_info.res.height);
- }
- else {
+ } else {
video_vf_info = NULL;
}
}
for (i = 0; i < cas_scaler_descr.num_stage; i++) {
struct ia_css_binary_descr yuv_scaler_descr;
+
mycs->is_output_stage[i] = cas_scaler_descr.is_output_stage[i];
ia_css_pipe_get_yuvscaler_binarydesc(pipe,
&yuv_scaler_descr, &cas_scaler_descr.in_info[i],
ia_css_pipe_destroy_cas_scaler_desc(&cas_scaler_descr);
}
-
{
struct ia_css_binary_descr video_descr;
enum ia_css_frame_format vf_info_format;
unload_video_binaries(struct ia_css_pipe *pipe)
{
unsigned int i;
+
IA_CSS_ENTER_PRIVATE("pipe = %p", pipe);
- if ((pipe == NULL) || (pipe->mode != IA_CSS_PIPE_ID_VIDEO)) {
+ if ((!pipe) || (pipe->mode != IA_CSS_PIPE_ID_VIDEO)) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
enum sh_css_pipe_config_override copy_ovrd;
enum ia_css_input_mode video_pipe_input_mode;
-
IA_CSS_ENTER_PRIVATE("pipe = %p", pipe);
- if ((pipe == NULL) || (pipe->mode != IA_CSS_PIPE_ID_VIDEO)) {
+ if ((!pipe) || (pipe->mode != IA_CSS_PIPE_ID_VIDEO)) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
#ifndef ISP2401
);
#else
- ©_pipe->config.internal_frame_origin_bqs_on_sctbl,
+ & copy_pipe->config.internal_frame_origin_bqs_on_sctbl,
copy_pipe->stream->isp_params_configs);
#endif
#ifndef ISP2401
);
#else
- &capture_pipe->config.internal_frame_origin_bqs_on_sctbl,
+ & capture_pipe->config.internal_frame_origin_bqs_on_sctbl,
capture_pipe->stream->isp_params_configs);
#endif
}
struct ia_css_frame_info *info,
unsigned int idx)
{
- assert(pipe != NULL);
- assert(info != NULL);
+ assert(pipe);
+ assert(info);
/* We could print the pointer as input arg, and the values as output */
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "sh_css_pipe_get_viewfinder_frame_info() enter: void\n");
- if ( pipe->mode == IA_CSS_PIPE_ID_CAPTURE &&
+ if (pipe->mode == IA_CSS_PIPE_ID_CAPTURE &&
(pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_RAW ||
pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER))
return IA_CSS_ERR_MODE_HAS_NO_VIEWFINDER;
info.res.width=%d, info.res.height=%d, \
info.padded_width=%d, info.format=%d, \
info.raw_bit_depth=%d, info.raw_bayer_order=%d\n",
- info->res.width,info->res.height,
- info->padded_width,info->format,
- info->raw_bit_depth,info->raw_bayer_order);
+ info->res.width, info->res.height,
+ info->padded_width, info->format,
+ info->raw_bit_depth, info->raw_bayer_order);
return IA_CSS_SUCCESS;
}
IA_CSS_ENTER_PRIVATE("pipe = %p, width = %d, height = %d, min_width = %d, format = %d, idx = %d\n",
pipe, width, height, min_width, format, idx);
- if (pipe == NULL) {
+ if (!pipe) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
-
err = ia_css_util_check_res(width, height);
if (err != IA_CSS_SUCCESS) {
IA_CSS_LEAVE_ERR_PRIVATE(err);
{
enum ia_css_err err = IA_CSS_SUCCESS;
- assert(pipe != NULL);
+ assert(pipe);
IA_CSS_ENTER_PRIVATE("");
assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || pipe->mode == IA_CSS_PIPE_ID_COPY);
const struct ia_css_pipe *pipe)
{
const struct ia_css_frame_info *out_info = &pipe->output_info[0];
+
IA_CSS_ENTER_LEAVE_PRIVATE("");
- assert(pipe != NULL);
+ assert(pipe);
assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE);
#ifdef ISP2401
const struct ia_css_pipe *pipe)
{
IA_CSS_ENTER_LEAVE_PRIVATE("");
- assert(pipe != NULL);
+ assert(pipe);
assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE);
- return (pipe->extra_config.enable_dvs_6axis) ? true:false;
+ return (pipe->extra_config.enable_dvs_6axis) ? true : false;
}
static enum ia_css_err set_num_primary_stages(unsigned int *num, enum ia_css_pipe_version version)
{
enum ia_css_err err = IA_CSS_SUCCESS;
- if (num == NULL)
+ if (!num)
return IA_CSS_ERR_INVALID_ARGUMENTS;
switch (version) {
bool need_extra_yuv_scaler = false;
IA_CSS_ENTER_PRIVATE("");
- assert(pipe != NULL);
- assert(pipe->stream != NULL);
+ assert(pipe);
+ assert(pipe->stream);
assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || pipe->mode == IA_CSS_PIPE_ID_COPY);
online = pipe->stream->config.online;
IA_CSS_LEAVE_ERR_PRIVATE(err);
return err;
}
- }
- else{
+ } else {
err = ia_css_frame_check_info(pipe_out_info);
if (err != IA_CSS_SUCCESS) {
IA_CSS_LEAVE_ERR_PRIVATE(err);
}
for (i = 0; i < cas_scaler_descr.num_stage; i++) {
struct ia_css_binary_descr yuv_scaler_descr;
+
mycs->is_output_stage[i] = cas_scaler_descr.is_output_stage[i];
ia_css_pipe_get_yuvscaler_binarydesc(pipe,
&yuv_scaler_descr, &cas_scaler_descr.in_info[i],
/* ldc and capt_pp are not supported in the same pipeline */
if (need_ldc) {
struct ia_css_binary_descr capt_ldc_descr;
+
ia_css_pipe_get_ldc_binarydesc(pipe,
&capt_ldc_descr, &prim_out_info,
&capt_pp_out_info);
}
#ifndef ISP2401
- if(need_ldc) {
+ if (need_ldc) {
struct ia_css_binary_descr capt_ldc_descr;
+
ia_css_pipe_get_ldc_binarydesc(pipe,
&capt_ldc_descr, &prim_out_info,
&capt_ldc_out_info);
for (i = 0; i < mycs->num_primary_stage; i++) {
struct ia_css_frame_info *local_vf_info = NULL;
+
if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0] && (i == mycs->num_primary_stage - 1))
local_vf_info = &vf_info;
ia_css_pipe_get_primary_binarydesc(pipe, &prim_descr[i], &prim_in_info, &prim_out_info, local_vf_info, i);
IA_CSS_ENTER_PRIVATE("");
- if (pipe == NULL) {
+ if (!pipe) {
IA_CSS_ERROR("Invalid args - pipe %p", pipe);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
case IA_CSS_PIPE_ID_VIDEO:
{
struct ia_css_video_settings *mycs_video = &pipe->pipe_settings.video;
+
ref_info = mycs_video->video_binary.internal_frame_info;
/*The ref frame expects
- * 1. Y plane
- * 2. UV plane with line interleaving, like below
- * UUUUUU(width/2 times) VVVVVVVV..(width/2 times)
+ * 1. Y plane
+ * 2. UV plane with line interleaving, like below
+ * UUUUUU(width/2 times) VVVVVVVV..(width/2 times)
*
* This format is not YUV420(which has Y, U and V planes).
* Its closer to NV12, except that the UV plane has UV
case IA_CSS_PIPE_ID_PREVIEW:
{
struct ia_css_preview_settings *mycs_preview = &pipe->pipe_settings.preview;
+
ref_info = mycs_preview->preview_binary.internal_frame_info;
/*The ref frame expects
* 1. Y plane
break;
default:
return IA_CSS_ERR_INVALID_ARGUMENTS;
-
}
ref_info.raw_bit_depth = SH_CSS_REF_BIT_DEPTH;
IA_CSS_ENTER_PRIVATE("");
- assert(pipe != NULL);
+ assert(pipe);
assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || pipe->mode == IA_CSS_PIPE_ID_COPY);
if (pipe->pipe_settings.capture.pre_isp_binary.info)
return IA_CSS_SUCCESS;
struct ia_css_binary_descr pre_de_descr;
IA_CSS_ENTER_PRIVATE("");
- assert(pipe != NULL);
+ assert(pipe);
assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || pipe->mode == IA_CSS_PIPE_ID_COPY);
pipe_out_info = &pipe->output_info[0];
enum ia_css_err err = IA_CSS_SUCCESS;
IA_CSS_ENTER_PRIVATE("");
- assert(pipe != NULL);
+ assert(pipe);
assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || pipe->mode == IA_CSS_PIPE_ID_COPY);
if (pipe->pipe_settings.capture.pre_isp_binary.info)
{
bool rval;
- assert(pipe != NULL);
+ assert(pipe);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "copy_on_sp() enter:\n");
rval = true;
bool must_be_raw;
IA_CSS_ENTER_PRIVATE("");
- assert(pipe != NULL);
+ assert(pipe);
assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || pipe->mode == IA_CSS_PIPE_ID_COPY);
if (pipe->pipe_settings.capture.primary_binary[0].info) {
case IA_CSS_CAPTURE_MODE_RAW:
err = load_copy_binaries(pipe);
#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2401)
- if (err == IA_CSS_SUCCESS)
+ if (err == IA_CSS_SUCCESS)
pipe->pipe_settings.capture.copy_binary.online = pipe->stream->config.online;
#endif
break;
unload_capture_binaries(struct ia_css_pipe *pipe)
{
unsigned int i;
+
IA_CSS_ENTER_PRIVATE("pipe = %p", pipe);
- if ((pipe == NULL) || ((pipe->mode != IA_CSS_PIPE_ID_CAPTURE) && (pipe->mode != IA_CSS_PIPE_ID_COPY))) {
+ if ((!pipe) || ((pipe->mode != IA_CSS_PIPE_ID_CAPTURE) && (pipe->mode != IA_CSS_PIPE_ID_COPY))) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
need_downscaling(const struct ia_css_resolution in_res,
const struct ia_css_resolution out_res)
{
-
if (in_res.width > out_res.width || in_res.height > out_res.height)
return true;
bool need_format_conversion = false;
IA_CSS_ENTER_PRIVATE("");
- assert(pipe != NULL);
+ assert(pipe);
assert(pipe->mode == IA_CSS_PIPE_ID_YUVPP);
/* TODO: make generic function */
enum ia_css_err err = IA_CSS_SUCCESS;
struct ia_css_frame_info tmp_in_info;
- unsigned max_scale_factor_per_stage = MAX_PREFERRED_YUV_DS_PER_STEP;
+ unsigned int max_scale_factor_per_stage = MAX_PREFERRED_YUV_DS_PER_STEP;
- assert(cas_scaler_in_info != NULL);
- assert(cas_scaler_out_info != NULL);
+ assert(cas_scaler_in_info);
+ assert(cas_scaler_out_info);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_pipe_create_cas_scaler_desc() enter:\n");
/* We assume that this function is used only for single output port case. */
descr->num_output_stage = 1;
- hor_ds_factor = CEIL_DIV(cas_scaler_in_info->res.width , cas_scaler_out_info->res.width);
+ hor_ds_factor = CEIL_DIV(cas_scaler_in_info->res.width, cas_scaler_out_info->res.width);
ver_ds_factor = CEIL_DIV(cas_scaler_in_info->res.height, cas_scaler_out_info->res.height);
/* use the same horizontal and vertical downscaling factor for simplicity */
assert(hor_ds_factor == ver_ds_factor);
tmp_in_info = *cas_scaler_in_info;
for (i = 0; i < descr->num_stage; i++) {
-
descr->in_info[i] = tmp_in_info;
if ((tmp_in_info.res.width / max_scale_factor_per_stage) <= cas_scaler_out_info->res.width) {
descr->is_output_stage[i] = true;
descr->out_info[i].res.height = cas_scaler_out_info->res.height;
descr->out_info[i].padded_width = cas_scaler_out_info->padded_width;
descr->out_info[i].format = cas_scaler_out_info->format;
- if (cas_scaler_vf_info != NULL) {
+ if (cas_scaler_vf_info) {
descr->vf_info[i].res.width = cas_scaler_vf_info->res.width;
descr->vf_info[i].res.height = cas_scaler_vf_info->res.height;
descr->vf_info[i].padded_width = cas_scaler_vf_info->padded_width;
unsigned int num_stages = 0;
enum ia_css_err err = IA_CSS_SUCCESS;
- unsigned max_scale_factor_per_stage = MAX_PREFERRED_YUV_DS_PER_STEP;
+ unsigned int max_scale_factor_per_stage = MAX_PREFERRED_YUV_DS_PER_STEP;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_pipe_create_cas_scaler_desc() enter:\n");
descr->num_output_stage += 1;
}
- if (out_info[i] != NULL) {
+ if (out_info[i]) {
hor_scale_factor[i] = CEIL_DIV(in_info.res.width, out_info[i]->res.width);
ver_scale_factor[i] = CEIL_DIV(in_info.res.height, out_info[i]->res.height);
/* use the same horizontal and vertical scaling factor for simplicity */
descr->num_stage = num_stages;
- descr->in_info = kmalloc(descr->num_stage * sizeof(struct ia_css_frame_info), GFP_KERNEL);
+ descr->in_info = kmalloc_array(descr->num_stage, sizeof(struct ia_css_frame_info), GFP_KERNEL);
if (!descr->in_info) {
err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
goto ERR;
goto ERR;
}
descr->is_output_stage = kmalloc(descr->num_stage * sizeof(bool), GFP_KERNEL);
- if (descr->is_output_stage == NULL) {
+ if (!descr->is_output_stage) {
err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
goto ERR;
}
for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) {
if (out_info[i]) {
if (i > 0) {
- assert((out_info[i-1]->res.width >= out_info[i]->res.width) &&
- (out_info[i-1]->res.height >= out_info[i]->res.height));
+ assert((out_info[i - 1]->res.width >= out_info[i]->res.width) &&
+ (out_info[i - 1]->res.height >= out_info[i]->res.height));
}
}
}
tmp_in_info.format = IA_CSS_FRAME_FORMAT_YUV420;
for (i = 0, j = 0; i < descr->num_stage; i++) {
assert(j < 2);
- assert(out_info[j] != NULL);
+ assert(out_info[j]);
descr->in_info[i] = tmp_in_info;
if ((tmp_in_info.res.width / max_scale_factor_per_stage) <= out_info[j]->res.width) {
descr->out_info[i].res.height = out_info[j]->res.height;
descr->out_info[i].padded_width = out_info[j]->padded_width;
descr->out_info[i].format = out_info[j]->format;
- if (vf_out_info[j] != NULL) {
+ if (vf_out_info[j]) {
descr->vf_info[i].res.width = vf_out_info[j]->res.width;
descr->vf_info[i].res.height = vf_out_info[j]->res.height;
descr->vf_info[i].padded_width = vf_out_info[j]->padded_width;
bool need_isp_copy_binary = false;
IA_CSS_ENTER_PRIVATE("");
- assert(pipe != NULL);
- assert(pipe->stream != NULL);
+ assert(pipe);
+ assert(pipe->stream);
assert(pipe->mode == IA_CSS_PIPE_ID_YUVPP);
if (pipe->pipe_settings.yuvpp.copy_binary.info)
goto ERR;
- /* Set both must_be_raw and must_be_yuv to false then yuvpp can take rgb inputs */
+ /* Set both must_be_raw and must_be_yuv to false then yuvpp can take rgb inputs */
err = ia_css_util_check_input(&pipe->stream->config, false, false);
if (err != IA_CSS_SUCCESS)
goto ERR;
unload_yuvpp_binaries(struct ia_css_pipe *pipe)
{
unsigned int i;
+
IA_CSS_ENTER_PRIVATE("pipe = %p", pipe);
- if ((pipe == NULL) || (pipe->mode != IA_CSS_PIPE_ID_YUVPP)) {
+ if ((!pipe) || (pipe->mode != IA_CSS_PIPE_ID_YUVPP)) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
enum ia_css_input_mode yuvpp_pipe_input_mode;
IA_CSS_ENTER_PRIVATE("pipe = %p", pipe);
- if ((pipe == NULL) || (pipe->mode != IA_CSS_PIPE_ID_YUVPP)) {
+ if ((!pipe) || (pipe->mode != IA_CSS_PIPE_ID_YUVPP)) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
/* multi stream video needs mipi buffers */
-#if !defined(HAS_NO_INPUT_SYSTEM) && ( defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) )
+#if !defined(HAS_NO_INPUT_SYSTEM) && (defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401))
err = send_mipi_frames(pipe);
if (err != IA_CSS_SUCCESS) {
IA_CSS_LEAVE_ERR_PRIVATE(err);
sh_css_pipe_unload_binaries(struct ia_css_pipe *pipe)
{
enum ia_css_err err = IA_CSS_SUCCESS;
+
IA_CSS_ENTER_PRIVATE("pipe = %p", pipe);
- if (pipe == NULL) {
+ if (!pipe) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
{
enum ia_css_err err = IA_CSS_SUCCESS;
- assert(pipe != NULL);
+ assert(pipe);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "sh_css_pipe_load_binaries() enter:\n");
/* PIPE_MODE_COPY has no binaries, but has output frames to outside*/
#endif
IA_CSS_ENTER_PRIVATE("pipe = %p", pipe);
- if ((pipe == NULL) || (pipe->stream == NULL) || (pipe->mode != IA_CSS_PIPE_ID_YUVPP)) {
+ if ((!pipe) || (!pipe->stream) || (pipe->mode != IA_CSS_PIPE_ID_YUVPP)) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
* Bayer-Quad RAW.
*/
int in_frame_format;
+
if (pipe->stream->config.input_config.format == ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY) {
in_frame_format = IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8;
} else if (pipe->stream->config.input_config.format == ATOMISP_INPUT_FORMAT_YUV422_8) {
need_scaler = need_yuv_scaler_stage(pipe);
if (pipe->pipe_settings.yuvpp.copy_binary.info) {
-
struct ia_css_frame *in_frame_local = NULL;
#ifdef USE_INPUT_SYSTEM_VERSION_2401
j++;
}
}
- } else if (copy_stage != NULL) {
- if (vf_frame[0] != NULL && vf_frame[0]->info.res.width != 0) {
+ } else if (copy_stage) {
+ if (vf_frame[0] && vf_frame[0]->info.res.width != 0) {
in_frame = copy_stage->args.out_vf_frame;
err = add_vf_pp_stage(pipe, in_frame, vf_frame[0], &vf_pp_binary[0],
&vf_pp_stage);
static enum ia_css_err
create_host_copy_pipeline(struct ia_css_pipe *pipe,
- unsigned max_input_width,
+ unsigned int max_input_width,
struct ia_css_frame *out_frame)
{
struct ia_css_pipeline *me;
IA_CSS_PIPELINE_ISYS_COPY, max_input_width);
err = ia_css_pipeline_create_and_add_stage(me,
&stage_desc, &out_stage);
- if(err != IA_CSS_SUCCESS)
+ if (err != IA_CSS_SUCCESS)
return err;
ia_css_pipeline_finalize_stages(me, pipe->stream->config.continuous);
bool need_ldc = false;
IA_CSS_ENTER_PRIVATE("");
- assert(pipe != NULL);
- assert(pipe->stream != NULL);
+ assert(pipe);
+ assert(pipe->stream);
assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || pipe->mode == IA_CSS_PIPE_ID_COPY);
me = &pipe->pipeline;
need_pp = (need_capture_pp(pipe) || pipe->output_stage) &&
mode != IA_CSS_CAPTURE_MODE_RAW &&
mode != IA_CSS_CAPTURE_MODE_BAYER;
- need_yuv_pp = (yuv_scaler_binary != NULL && yuv_scaler_binary->info != NULL);
- need_ldc = (capture_ldc_binary != NULL && capture_ldc_binary->info != NULL);
+ need_yuv_pp = (yuv_scaler_binary && yuv_scaler_binary->info);
+ need_ldc = (capture_ldc_binary && capture_ldc_binary->info);
if (pipe->pipe_settings.capture.copy_binary.info) {
if (raw) {
IA_CSS_BINARY_MODE_COPY;
current_stage->args.copy_output = current_stage->args.copy_vf;
} else if (mode == IA_CSS_CAPTURE_MODE_ADVANCED ||
- mode == IA_CSS_CAPTURE_MODE_LOW_LIGHT) {
+ mode == IA_CSS_CAPTURE_MODE_LOW_LIGHT) {
ia_css_pipe_util_set_output_frames(out_frames, 0, NULL);
ia_css_pipe_get_generic_stage_desc(&stage_desc, pre_isp_binary,
out_frames, in_frame, NULL);
return err;
}
- if(need_pp) {
+ if (need_pp) {
ia_css_pipe_util_set_output_frames(out_frames, 0, NULL);
ia_css_pipe_get_generic_stage_desc(&stage_desc, post_isp_binary,
out_frames, NULL, NULL);
#ifndef ISP2401
if (need_pp && current_stage) {
struct ia_css_frame *local_in_frame = NULL;
+
local_in_frame = current_stage->args.out_frame[0];
- if(need_ldc) {
+ if (need_ldc) {
ia_css_pipe_util_set_output_frames(out_frames, 0, NULL);
ia_css_pipe_get_generic_stage_desc(&stage_desc, capture_ldc_binary,
out_frames, local_in_frame, NULL);
enum sh_css_pipe_config_override copy_ovrd;
IA_CSS_ENTER_PRIVATE("pipe = %p", pipe);
- if (pipe == NULL) {
+ if (!pipe) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
me = &pipe->pipeline;
if ((pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_RAW ||
- pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER ) &&
+ pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER) &&
(pipe->config.mode != IA_CSS_PIPE_MODE_COPY)) {
if (copy_on_sp(pipe)) {
err = start_copy_on_sp(pipe, &me->out_frame[0]);
ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id);
copy_ovrd = 1 << thread_id;
-
}
start_pipe(pipe, copy_ovrd, pipe->stream->config.mode);
IA_CSS_LEAVE_ERR_PRIVATE(err);
return err;
-
}
static enum ia_css_err
struct ia_css_frame_info *info,
unsigned int idx)
{
- assert(pipe != NULL);
- assert(info != NULL);
+ assert(pipe);
+ assert(info);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"sh_css_pipe_get_output_frame_info() enter:\n");
0);
} else if (info->format == IA_CSS_FRAME_FORMAT_RAW ||
info->format == IA_CSS_FRAME_FORMAT_RAW_PACKED) {
- info->raw_bit_depth =
- ia_css_pipe_util_pipe_input_format_bpp(pipe);
-
+ info->raw_bit_depth =
+ ia_css_pipe_util_pipe_input_format_bpp(pipe);
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
unsigned int width,
unsigned int height)
{
- assert(stream != NULL);
+ assert(stream);
ia_css_inputfifo_send_input_frame(
data, width, height,
void
ia_css_stream_start_input_frame(const struct ia_css_stream *stream)
{
- assert(stream != NULL);
+ assert(stream);
ia_css_inputfifo_start_frame(
stream->config.channel_id,
const unsigned short *data2,
unsigned int width2)
{
- assert(stream != NULL);
+ assert(stream);
ia_css_inputfifo_send_line(stream->config.channel_id,
data, width, data2, width2);
const unsigned short *data,
unsigned int width)
{
- assert(stream != NULL);
- if (data == NULL || width == 0)
+ assert(stream);
+ if (!data || width == 0)
return;
ia_css_inputfifo_send_embedded_line(stream->config.channel_id,
format, data, width);
void
ia_css_stream_end_input_frame(const struct ia_css_stream *stream)
{
- assert(stream != NULL);
+ assert(stream);
ia_css_inputfifo_end_frame(stream->config.channel_id);
}
static void
append_firmware(struct ia_css_fw_info **l, struct ia_css_fw_info *firmware)
{
- IA_CSS_ENTER_PRIVATE("l = %p, firmware = %p", l , firmware);
- if (l == NULL) {
+ IA_CSS_ENTER_PRIVATE("l = %p, firmware = %p", l, firmware);
+ if (!l) {
IA_CSS_ERROR("NULL fw_info");
IA_CSS_LEAVE_PRIVATE("");
return;
{
hrt_vaddress binary;
- if (firmware == NULL) {
+ if (!firmware) {
IA_CSS_ERROR("NULL input parameter");
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
binary = firmware->info.isp.xmem_addr;
if (!binary) {
- unsigned size = firmware->blob.size;
+ unsigned int size = firmware->blob.size;
const unsigned char *blob;
const unsigned char *binary_name;
+
binary_name =
(const unsigned char *)(IA_CSS_EXT_ISP_PROG_NAME(
firmware));
{
enum ia_css_err err;
struct ia_css_fw_info *hd = firmware;
- while (hd){
+
+ while (hd) {
err = upload_isp_code(hd);
if (err != IA_CSS_SUCCESS)
return err;
hd = hd->next;
}
- if (firmware == NULL)
+ if (!firmware)
return IA_CSS_ERR_INVALID_ARGUMENTS;
firmware->loaded = true;
return IA_CSS_SUCCESS;
struct ia_css_fw_info *hd = firmware;
struct ia_css_fw_info *hdn = NULL;
- if (firmware == NULL) /* should not happen */
+ if (!firmware) /* should not happen */
return;
/* unload and remove multiple firmwares */
- while (hd){
+ while (hd) {
hdn = (hd->next) ? &(*hd->next) : NULL;
if (hd->info.isp.xmem_addr) {
hmm_free(hd->info.isp.xmem_addr);
firmware->loaded = false;
}
+
/* Load firmware for extension */
static enum ia_css_err
ia_css_pipe_load_extension(struct ia_css_pipe *pipe,
IA_CSS_ENTER_PRIVATE("fw = %p pipe = %p", firmware, pipe);
- if ((firmware == NULL) || (pipe == NULL)) {
+ if ((!firmware) || (!pipe)) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
if (firmware->info.isp.type == IA_CSS_ACC_OUTPUT) {
- if (&pipe->output_stage != NULL)
+ if (&pipe->output_stage)
append_firmware(&pipe->output_stage, firmware);
else {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INTERNAL_ERROR);
return IA_CSS_ERR_INTERNAL_ERROR;
}
- }
- else if (firmware->info.isp.type == IA_CSS_ACC_VIEWFINDER) {
- if (&pipe->vf_stage != NULL)
+ } else if (firmware->info.isp.type == IA_CSS_ACC_VIEWFINDER) {
+ if (&pipe->vf_stage)
append_firmware(&pipe->vf_stage, firmware);
else {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INTERNAL_ERROR);
{
IA_CSS_ENTER_PRIVATE("fw = %p pipe = %p", firmware, pipe);
- if ((firmware == NULL) || (pipe == NULL)) {
+ if ((!firmware) || (!pipe)) {
IA_CSS_ERROR("NULL input parameters");
IA_CSS_LEAVE_PRIVATE("");
return;
{
struct ia_css_pipeline_stage *stage;
- assert(me != NULL);
+ assert(me);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_pipeline_uses_params() enter: me=%p\n", me);
for (stage = me->stages; stage; stage = stage->next)
if (stage->binary_info && stage->binary_info->enable.params) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
- "ia_css_pipeline_uses_params() leave: "
- "return_bool=true\n");
+ "ia_css_pipeline_uses_params() leave: return_bool=true\n");
return true;
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
struct ia_css_fw_info *fw = (struct ia_css_fw_info *)acc_fw;
/* In QoS case, load_extension already called, so skipping */
enum ia_css_err err = IA_CSS_SUCCESS;
+
if (fw->loaded == false)
err = acc_load_extension(fw);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
- "sh_css_pipeline_add_acc_stage() enter: pipeline=%p,"
- " acc_fw=%p\n", pipeline, acc_fw);
+ "sh_css_pipeline_add_acc_stage() enter: pipeline=%p, acc_fw=%p\n",
+ pipeline, acc_fw);
if (err == IA_CSS_SUCCESS) {
struct ia_css_pipeline_stage_desc stage_desc;
+
ia_css_pipe_get_acc_stage_desc(&stage_desc, NULL, fw);
err = ia_css_pipeline_create_and_add_stage(pipeline,
&stage_desc,
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
- "sh_css_pipeline_add_acc_stage() leave: return_err=%d\n",err);
+ "sh_css_pipeline_add_acc_stage() leave: return_err=%d\n", err);
return err;
}
unsigned int exp_id)
{
struct sh_css_tag_descr tag_descr;
- uint32_t encoded_tag_descr;
+ u32 encoded_tag_descr;
enum ia_css_err err;
- assert(stream != NULL);
+ assert(stream);
IA_CSS_ENTER("exp_id=%d", exp_id);
/* Only continuous streams have a tagger */
* Note: The pipe and stage IDs for tag_cmd queue are hard-coded to 0
* on both host and the SP side.
* It is mainly because it is enough to have only one tag_cmd queue */
- err= ia_css_bufq_enqueue_tag_cmd(encoded_tag_descr);
+ err = ia_css_bufq_enqueue_tag_cmd(encoded_tag_descr);
IA_CSS_LEAVE_ERR(err);
return err;
unsigned int encoded_tag_descr;
enum ia_css_err return_err;
- if (stream == NULL)
+ if (!stream)
return IA_CSS_ERR_INVALID_ARGUMENTS;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
- "ia_css_stream_capture() enter: num_captures=%d,"
- " skip=%d, offset=%d\n", num_captures, skip,offset);
+ "ia_css_stream_capture() enter: num_captures=%d, skip=%d, offset=%d\n",
+ num_captures, skip, offset);
/* Check if the tag descriptor is valid */
if (num_captures < SH_CSS_MINIMUM_TAG_ID) {
/* Create the tag descriptor from the parameters */
sh_css_create_tag_descr(num_captures, skip, offset, 0, &tag_descr);
-
/* Encode the tag descriptor into a 32-bit value */
encoded_tag_descr = sh_css_encode_tag_descr(&tag_descr);
if (!sh_css_sp_is_running()) {
/* SP is not running. The queues are not valid */
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
- "ia_css_stream_capture() leaving:"
- "queues unavailable\n");
+ "ia_css_stream_capture() leaving:queues unavailable\n");
return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE;
}
{
(void)stream;
- assert(stream != NULL);
+ assert(stream);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_request_flash() enter: void\n");
#ifndef ISP2401
#ifndef ISP2401
sp_dmem_store_uint32(SP0_ID,
(unsigned int)sp_address_of(sp_stop_copy_preview),
- my_css.stop_copy_preview?(uint32_t)(1):(uint32_t)(0));
+ my_css.stop_copy_preview ? (uint32_t)(1) : (uint32_t)(0));
#endif
store_sp_array_uint(host_sp_com, o, host2sp_cmd_ready);
void
ia_css_pipe_extra_config_defaults(struct ia_css_pipe_extra_config *extra_config)
{
- if (extra_config == NULL) {
+ if (!extra_config) {
IA_CSS_ERROR("NULL input parameter");
return;
}
void ia_css_stream_config_defaults(struct ia_css_stream_config *stream_config)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_config_defaults()\n");
- assert(stream_config != NULL);
+ assert(stream_config);
memset(stream_config, 0, sizeof(*stream_config));
stream_config->online = true;
stream_config->left_padding = -1;
{
enum ia_css_err err = IA_CSS_SUCCESS;
- if (pipe == NULL) {
+ if (!pipe) {
IA_CSS_ERROR("NULL input parameter");
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
struct ia_css_pipe **pipe)
{
#ifndef ISP2401
- if (config == NULL)
+ if (!config)
#else
enum ia_css_err err = IA_CSS_SUCCESS;
+
IA_CSS_ENTER_PRIVATE("config = %p, pipe = %p", config, pipe);
- if (config == NULL) {
+ if (!config) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
#endif
return IA_CSS_ERR_INVALID_ARGUMENTS;
#ifndef ISP2401
- if (pipe == NULL)
+ if (!pipe)
#else
}
- if (pipe == NULL) {
+ if (!pipe) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
#endif
return IA_CSS_ERR_INVALID_ARGUMENTS;
err = ia_css_pipe_create_extra(config, NULL, pipe);
- if(err == IA_CSS_SUCCESS) {
+ if (err == IA_CSS_SUCCESS) {
IA_CSS_LOG("pipe created successfully = %p", *pipe);
}
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
- if ((pipe == NULL) || (config == NULL)) {
+ if ((!pipe) || (!config)) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
else
internal_pipe->dvs_frame_delay = 1;
-
/* we still keep enable_raw_binning for backward compatibility, for any new
fractional bayer downscaling, we should use bayer_ds_out_res. if both are
specified, bayer_ds_out_res will take precedence.if none is specified, we
if ((internal_pipe->config.vf_pp_in_res.width ||
internal_pipe->config.capt_pp_in_res.width)) {
enum ia_css_frame_format format;
+
if (internal_pipe->config.vf_pp_in_res.width) {
format = IA_CSS_FRAME_FORMAT_YUV_LINE;
ia_css_frame_info_init(
return IA_CSS_SUCCESS;
}
-
enum ia_css_err
ia_css_pipe_get_info(const struct ia_css_pipe *pipe,
struct ia_css_pipe_info *pipe_info)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_pipe_get_info()\n");
- assert(pipe_info != NULL);
- if (pipe_info == NULL) {
+ assert(pipe_info);
+ if (!pipe_info) {
ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
"ia_css_pipe_get_info: pipe_info cannot be NULL\n");
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
- if (pipe == NULL || pipe->stream == NULL) {
+ if (!pipe || !pipe->stream) {
ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
- "ia_css_pipe_get_info: ia_css_stream_create needs to"
- " be called before ia_css_[stream/pipe]_get_info\n");
+ "ia_css_pipe_get_info: ia_css_stream_create needs to be called before ia_css_[stream/pipe]_get_info\n");
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
/* we succeeded return the info */
{
unsigned int i;
- if (pipe_info != NULL) {
+ if (pipe_info) {
for (i = 0; i < IA_CSS_DVS_STAT_NUM_OF_LEVELS; i++) {
if (pipe_info->grid_info.dvs_grid.dvs_stat_grid_info.grd_cfg[i].grd_start.enable)
return true;
IA_CSS_ENTER_PRIVATE("pipe = %p, pin_index = %d, new_formats = %d", pipe, pin_index, new_format);
- if (NULL == pipe) {
+ if (!pipe) {
IA_CSS_ERROR("pipe is not set");
err = IA_CSS_ERR_INVALID_ARGUMENTS;
IA_CSS_LEAVE_ERR_PRIVATE(err);
IA_CSS_LEAVE_ERR_PRIVATE(err);
return err;
}
- if (IA_CSS_FRAME_FORMAT_NV12_TILEY != new_format) {
+ if (new_format != IA_CSS_FRAME_FORMAT_NV12_TILEY) {
IA_CSS_ERROR("new format is not valid");
err = IA_CSS_ERR_INVALID_ARGUMENTS;
IA_CSS_LEAVE_ERR_PRIVATE(err);
return err;
} else {
err = ia_css_pipe_check_format(pipe, new_format);
- if (IA_CSS_SUCCESS == err) {
+ if (err == IA_CSS_SUCCESS) {
if (pin_index == 0) {
pipe->output_info[0].format = new_format;
} else {
ia_css_stream_configure_rx(struct ia_css_stream *stream)
{
struct ia_css_input_port *config;
- assert(stream != NULL);
+
+ assert(stream);
config = &stream->config.source.port;
/* AM: this code is not reliable, especially for 2400 */
enum ia_css_pipe_mode mode,
bool copy_pipe)
{
- unsigned i;
- assert(pipes != NULL);
+ unsigned int i;
+
+ assert(pipes);
for (i = 0; i < num_pipes; i++) {
- assert(pipes[i] != NULL);
+ assert(pipes[i]);
if (pipes[i]->config.mode != mode)
continue;
if (copy_pipe && pipes[i]->mode != IA_CSS_PIPE_ID_COPY)
int i;
enum ia_css_err err = IA_CSS_SUCCESS;
- assert(stream != NULL);
+ assert(stream);
IA_CSS_ENTER_PRIVATE("stream = %p", stream);
- if (stream == NULL) {
+ if (!stream) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
for (i = 0; i < stream->num_pipes; i++) {
struct ia_css_pipe *pipe = stream->pipes[i];
- assert(pipe != NULL);
- if (pipe == NULL) {
+
+ assert(pipe);
+ if (!pipe) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
for (i = 0; i < stream->num_pipes; i++) {
struct ia_css_pipe *pipe = stream->pipes[i];
- assert(pipe != NULL);
+
+ assert(pipe);
ia_css_pipe_map_queue(pipe, true);
}
stream->started = false;
-
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS);
return IA_CSS_SUCCESS;
return IA_CSS_ERR_INVALID_ARGUMENTS;
md->resolution = mdc->resolution;
- /* We round up the stride to a multiple of the width
- * of the port going to DDR, this is a HW requirements (DMA). */
+ /* We round up the stride to a multiple of the width
+ * of the port going to DDR, this is a HW requirements (DMA). */
md->stride = CEIL_MUL(mdc->resolution.width, HIVE_ISP_DDR_WORD_BYTES);
md->size = mdc->resolution.height * md->stride;
return IA_CSS_SUCCESS;
/* some checks */
if (num_pipes == 0 ||
- stream == NULL ||
- pipes == NULL) {
+ !stream ||
+ !pipes) {
err = IA_CSS_ERR_INVALID_ARGUMENTS;
IA_CSS_LEAVE_ERR(err);
return err;
if (!stream_config->online)
#endif
{
- unsigned int port = (unsigned int) stream_config->source.port.port;
+ unsigned int port = (unsigned int)stream_config->source.port.port;
+
if (port >= N_MIPI_PORT_ID) {
err = IA_CSS_ERR_INVALID_ARGUMENTS;
IA_CSS_LEAVE_ERR(err);
return err;
}
- if (my_css.size_mem_words != 0){
+ if (my_css.size_mem_words != 0) {
my_css.mipi_frame_size[port] = my_css.size_mem_words;
} else if (stream_config->mipi_buffer_config.size_mem_words != 0) {
my_css.mipi_frame_size[port] = stream_config->mipi_buffer_config.size_mem_words;
IA_CSS_LEAVE_ERR(err);
return err;
}
-
}
#endif
/* allocate pipes */
curr_stream->num_pipes = num_pipes;
- curr_stream->pipes = kzalloc(num_pipes * sizeof(struct ia_css_pipe *), GFP_KERNEL);
+ curr_stream->pipes = kcalloc(num_pipes, sizeof(struct ia_css_pipe *), GFP_KERNEL);
if (!curr_stream->pipes) {
curr_stream->num_pipes = 0;
kfree(curr_stream);
/* store pipes */
spcopyonly = (num_pipes == 1) && (pipes[0]->config.mode == IA_CSS_PIPE_MODE_COPY);
for (i = 0; i < num_pipes; i++)
- curr_stream->pipes [i] = pipes[i];
+ curr_stream->pipes[i] = pipes[i];
curr_stream->last_pipe = curr_stream->pipes[0];
/* take over stream config */
curr_stream->config = *stream_config;
/* The aspect ratio cropping is currently only
* supported on the new input system. */
if (aspect_ratio_crop_check(aspect_ratio_crop_enabled, curr_pipe)) {
-
struct ia_css_resolution crop_res;
err = aspect_ratio_crop(curr_pipe, &crop_res);
goto ERR;
}
/* sensor binning */
- if (!spcopyonly){
+ if (!spcopyonly) {
sensor_binning_changed =
sh_css_params_set_binning_factor(curr_stream, curr_stream->config.sensor_binning_factor);
} else {
if (curr_stream->cont_capt == true) {
capture_pipe = find_pipe(pipes, num_pipes,
IA_CSS_PIPE_MODE_CAPTURE, false);
- if (capture_pipe == NULL) {
+ if (!capture_pipe) {
err = IA_CSS_ERR_INTERNAL_ERROR;
goto ERR;
}
/* now pipes have been configured, info should be available */
for (i = 0; i < num_pipes; i++) {
struct ia_css_pipe_info *pipe_info = NULL;
+
curr_pipe = pipes[i];
err = sh_css_pipe_load_binaries(curr_pipe);
#ifdef ISP2401
pipe_info->output_system_in_res_info = curr_pipe->config.output_system_in_res;
#endif
- if (!spcopyonly){
+ if (!spcopyonly) {
err = sh_css_pipe_get_shading_info(curr_pipe,
#ifndef ISP2401
&pipe_info->shading_info);
#else
- &pipe_info->shading_info, &curr_pipe->config);
+ & pipe_info->shading_info, &curr_pipe->config);
#endif
if (err != IA_CSS_SUCCESS)
goto ERR;
#endif
IA_CSS_ENTER_PRIVATE("stream = %p", stream);
- if (stream == NULL) {
+ if (!stream) {
err = IA_CSS_ERR_INVALID_ARGUMENTS;
IA_CSS_LEAVE_ERR_PRIVATE(err);
return err;
ia_css_stream_isp_parameters_uninit(stream);
- if ((stream->last_pipe != NULL) &&
+ if ((stream->last_pipe) &&
ia_css_pipeline_is_mapped(stream->last_pipe->pipe_num)) {
#if defined(USE_INPUT_SYSTEM_VERSION_2401)
for (i = 0; i < stream->num_pipes; i++) {
unsigned int sp_thread_id;
struct sh_css_sp_pipeline_terminal *sp_pipeline_input_terminal;
- assert(entry != NULL);
- if (entry != NULL) {
+ assert(entry);
+ if (entry) {
/* get the SP thread id */
if (ia_css_pipeline_get_sp_thread_id(
ia_css_pipe_get_pipe_num(entry), &sp_thread_id) != true)
return IA_CSS_ERR_INTERNAL_ERROR;
/* get the target input terminal */
sp_pipeline_input_terminal =
- &(sh_css_sp_group.pipe_io[sp_thread_id].input);
+ &sh_css_sp_group.pipe_io[sp_thread_id].input;
for (i = 0; i < IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH; i++) {
ia_css_isys_stream_h isys_stream =
- &(sp_pipeline_input_terminal->context.virtual_input_system_stream[i]);
+ &sp_pipeline_input_terminal->context.virtual_input_system_stream[i];
if (stream->config.isys_config[i].valid && isys_stream->valid)
ia_css_isys_stream_destroy(isys_stream);
}
* some test stream create-destroy cycles do not generate output frames
* and the mipi buffer is not freed in the deque function
*/
- if (entry != NULL)
+ if (entry)
free_mipi_frames(entry);
}
}
for (i = 0; i < stream->num_pipes; i++) {
struct ia_css_pipe *curr_pipe = stream->pipes[i];
- assert(curr_pipe != NULL);
+
+ assert(curr_pipe);
ia_css_pipe_map_queue(curr_pipe, false);
}
/* remove references from pipes to stream */
for (i = 0; i < stream->num_pipes; i++) {
struct ia_css_pipe *entry = stream->pipes[i];
- assert(entry != NULL);
- if (entry != NULL) {
+
+ assert(entry);
+ if (entry) {
/* clear reference to stream */
entry->stream = NULL;
/* check internal copy pipe */
#ifndef ISP2401
/* working mode: take out of the seed list */
if (my_css_save.mode == sh_css_mode_working)
- for(i=0;i<MAX_ACTIVE_STREAMS;i++)
+ for (i = 0; i < MAX_ACTIVE_STREAMS; i++)
if (my_css_save.stream_seeds[i].stream == stream)
{
IA_CSS_LOG("took out stream %d", i);
struct ia_css_stream_info *stream_info)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_get_info: enter/exit\n");
- assert(stream != NULL);
- assert(stream_info != NULL);
+ assert(stream);
+ assert(stream_info);
*stream_info = stream->info;
return IA_CSS_SUCCESS;
#ifndef ISP2401
int i;
enum ia_css_err err;
- assert(stream != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_load() enter, \n");
+
+ assert(stream);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_load() enter,\n");
for (i = 0; i < MAX_ACTIVE_STREAMS; i++) {
if (my_css_save.stream_seeds[i].stream == stream) {
int j;
- for ( j = 0; j < my_css_save.stream_seeds[i].num_pipes; j++) {
- if ((err = ia_css_pipe_create(&(my_css_save.stream_seeds[i].pipe_config[j]), &my_css_save.stream_seeds[i].pipes[j])) != IA_CSS_SUCCESS) {
+
+ for (j = 0; j < my_css_save.stream_seeds[i].num_pipes; j++) {
+ if ((err = ia_css_pipe_create(&my_css_save.stream_seeds[i].pipe_config[j], &my_css_save.stream_seeds[i].pipes[j])) != IA_CSS_SUCCESS) {
if (j) {
int k;
- for(k=0;k<j;k++)
+
+ for (k = 0; k < j; k++)
ia_css_pipe_destroy(my_css_save.stream_seeds[i].pipes[k]);
}
return err;
}
}
- err = ia_css_stream_create(&(my_css_save.stream_seeds[i].stream_config),
+ err = ia_css_stream_create(&my_css_save.stream_seeds[i].stream_config,
my_css_save.stream_seeds[i].num_pipes,
my_css_save.stream_seeds[i].pipes,
- &(my_css_save.stream_seeds[i].stream));
+ &my_css_save.stream_seeds[i].stream);
if (err != IA_CSS_SUCCESS) {
ia_css_stream_destroy(stream);
for (j = 0; j < my_css_save.stream_seeds[i].num_pipes; j++)
break;
}
}
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_load() exit, \n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_load() exit,\n");
return IA_CSS_SUCCESS;
#else
/* TODO remove function - DEPRECATED */
ia_css_stream_start(struct ia_css_stream *stream)
{
enum ia_css_err err = IA_CSS_SUCCESS;
+
IA_CSS_ENTER("stream = %p", stream);
- if ((stream == NULL) || (stream->last_pipe == NULL)) {
+ if ((!stream) || (!stream->last_pipe)) {
IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
#if !defined(HAS_NO_INPUT_SYSTEM)
#if defined(USE_INPUT_SYSTEM_VERSION_2401)
- if((stream->config.mode == IA_CSS_INPUT_MODE_SENSOR) ||
+ if ((stream->config.mode == IA_CSS_INPUT_MODE_SENSOR) ||
(stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR))
stream_register_with_csi_rx(stream);
#endif
if (stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR)
{
unsigned int idx;
- unsigned int port = (unsigned int) (stream->config.source.port.port) ;
+ unsigned int port = (unsigned int)(stream->config.source.port.port);
for (idx = 0; idx < IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT; idx++) {
sh_css_sp_group.config.mipi_sizes_for_check[port][idx] = sh_css_get_mipi_sizes_for_check(port, idx);
enum ia_css_err err = IA_CSS_SUCCESS;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_stop() enter/exit\n");
- assert(stream != NULL);
- assert(stream->last_pipe != NULL);
+ assert(stream);
+ assert(stream->last_pipe);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_stop: stopping %d\n",
stream->last_pipe->mode);
if (stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR)
{
unsigned int idx;
- unsigned int port = (unsigned int) (stream->config.source.port.port) ;
+ unsigned int port = (unsigned int)(stream->config.source.port.port);
for (idx = 0; idx < IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT; idx++) {
sh_css_sp_group.config.mipi_sizes_for_check[port][idx] = 0;
ia_css_stream_has_stopped(struct ia_css_stream *stream)
{
bool stopped;
- assert(stream != NULL);
+
+ assert(stream);
#ifndef ISP2401
stopped = ia_css_pipeline_has_stopped(&stream->last_pipe->pipeline);
ia_css_stream_unload(struct ia_css_stream *stream)
{
int i;
- assert(stream != NULL);
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_unload() enter, \n");
+
+ assert(stream);
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_unload() enter,\n");
/* some checks */
- assert (stream != NULL);
- for(i=0;i<MAX_ACTIVE_STREAMS;i++)
+ assert(stream);
+ for (i = 0; i < MAX_ACTIVE_STREAMS; i++)
if (my_css_save.stream_seeds[i].stream == stream)
{
int j;
+
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_unload(): unloading %d (%p)\n", i, my_css_save.stream_seeds[i].stream);
ia_css_stream_destroy(stream);
- for(j=0;j<my_css_save.stream_seeds[i].num_pipes;j++)
+ for (j = 0; j < my_css_save.stream_seeds[i].num_pipes; j++)
ia_css_pipe_destroy(my_css_save.stream_seeds[i].pipes[j]);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_unload(): after unloading %d (%p)\n", i, my_css_save.stream_seeds[i].stream);
break;
}
- ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_unload() exit, \n");
+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_unload() exit,\n");
return IA_CSS_SUCCESS;
}
ia_css_temp_pipe_to_pipe_id(const struct ia_css_pipe *pipe, enum ia_css_pipe_id *pipe_id)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_temp_pipe_to_pipe_id() enter/exit\n");
- if (pipe != NULL)
+ if (pipe)
*pipe_id = pipe->mode;
else
*pipe_id = IA_CSS_PIPE_ID_COPY;
{
struct ia_css_pipe *pipe;
- assert(stream != NULL);
+ assert(stream);
pipe = stream->pipes[0];
if (stream->num_pipes == 2) {
- assert(stream->pipes[1] != NULL);
+ assert(stream->pipes[1]);
if (stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_VIDEO ||
stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_PREVIEW)
pipe = stream->pipes[1];
struct ia_css_pipe *video_pipe = NULL;
/* First we find the video pipe */
- for (i=0; i<stream->num_pipes; i++) {
+ for (i = 0; i < stream->num_pipes; i++) {
struct ia_css_pipe *pipe = stream->pipes[i];
+
if (pipe->config.mode == IA_CSS_PIPE_MODE_VIDEO) {
video_pipe = pipe;
break;
struct ia_css_pipe *pipe;
struct ia_css_binary *s3a_binary = NULL;
- assert(stream != NULL);
+ assert(stream);
pipe = stream->pipes[0];
if (stream->num_pipes == 2) {
- assert(stream->pipes[1] != NULL);
+ assert(stream->pipes[1]);
if (stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_VIDEO ||
stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_PREVIEW)
pipe = stream->pipes[1];
return s3a_binary;
}
-
enum ia_css_err
ia_css_stream_set_output_padded_width(struct ia_css_stream *stream, unsigned int output_padded_width)
{
struct ia_css_pipe *pipe;
- assert(stream != NULL);
+ assert(stream);
pipe = stream->last_pipe;
- assert(pipe != NULL);
+ assert(pipe);
/* set the config also just in case (redundant info? why do we save config in pipe?) */
pipe->config.output_info[IA_CSS_PIPE_OUTPUT_STAGE_0].padded_width = output_padded_width;
{
struct ia_css_binary *binary = NULL;
- assert(pipe != NULL);
+ assert(pipe);
switch (pipe->config.mode) {
case IA_CSS_PIPE_MODE_PREVIEW:
break;
}
}
- }
- else if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER)
+ } else if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER)
binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.pre_isp_binary;
else if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_ADVANCED ||
pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_LOW_LIGHT) {
{
struct ia_css_binary *binary = NULL;
- assert(pipe != NULL);
+ assert(pipe);
switch (pipe->config.mode) {
case IA_CSS_PIPE_MODE_PREVIEW:
- binary = (struct ia_css_binary*)&pipe->pipe_settings.preview.preview_binary;
+ binary = (struct ia_css_binary *)&pipe->pipe_settings.preview.preview_binary;
break;
case IA_CSS_PIPE_MODE_VIDEO:
- binary = (struct ia_css_binary*)&pipe->pipe_settings.video.video_binary;
+ binary = (struct ia_css_binary *)&pipe->pipe_settings.video.video_binary;
break;
case IA_CSS_PIPE_MODE_CAPTURE:
if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_PRIMARY) {
unsigned int i;
+
for (i = 0; i < pipe->pipe_settings.capture.num_primary_stage; i++) {
if (pipe->pipe_settings.capture.primary_binary[i].info->sp.enable.s3a) {
binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.primary_binary[i];
break;
}
}
- }
- else if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER)
+ } else if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER)
binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.pre_isp_binary;
else if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_ADVANCED ||
pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_LOW_LIGHT) {
if (binary && !binary->info->sp.enable.s3a)
binary = NULL;
- return binary;
+ return binary;
}
static struct ia_css_binary *
{
struct ia_css_binary *binary = NULL;
- assert(pipe != NULL);
+ assert(pipe);
switch (pipe->config.mode) {
case IA_CSS_PIPE_MODE_VIDEO:
- binary = (struct ia_css_binary*)&pipe->pipe_settings.video.video_binary;
+ binary = (struct ia_css_binary *)&pipe->pipe_settings.video.video_binary;
break;
default:
break;
struct ia_css_pipeline *
ia_css_pipe_get_pipeline(const struct ia_css_pipe *pipe)
{
- assert(pipe != NULL);
+ assert(pipe);
- return (struct ia_css_pipeline*)&pipe->pipeline;
+ return (struct ia_css_pipeline *)&pipe->pipeline;
}
unsigned int
ia_css_pipe_get_pipe_num(const struct ia_css_pipe *pipe)
{
- assert(pipe != NULL);
+ assert(pipe);
/* KW was not sure this function was not returning a value
that was out of range; so added an assert, and, for the
return pipe->pipe_num;
}
-
unsigned int
ia_css_pipe_get_isp_pipe_version(const struct ia_css_pipe *pipe)
{
- assert(pipe != NULL);
+ assert(pipe);
return (unsigned int)pipe->config.isp_pipe_version;
}
/* waiting for the SP is completely started */
timeout = SP_START_TIMEOUT_US;
- while((ia_css_spctrl_get_state(SP0_ID) != IA_CSS_SP_SW_INITIALIZED) && timeout) {
+ while ((ia_css_spctrl_get_state(SP0_ID) != IA_CSS_SP_SW_INITIALIZED) && timeout) {
timeout--;
hrt_sleep();
}
IA_CSS_DEBUG_TRACE,
"sh_css_update_continuous_frames() enter:\n");
- if (stream == NULL) {
+ if (!stream) {
ia_css_debug_dtrace(
IA_CSS_DEBUG_TRACE,
"sh_css_update_continuous_frames() leave: invalid stream, return_void\n");
bool need_input_queue;
IA_CSS_ENTER("");
- assert(pipe != NULL);
+ assert(pipe);
pipe_id = pipe->mode;
pipe_num = pipe->pipe_num;
#endif
} else if (pipe->mode == IA_CSS_PIPE_ID_YUVPP) {
unsigned int idx;
+
for (idx = 0; idx < IA_CSS_PIPE_MAX_OUTPUT_STAGE; idx++) {
ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_OUTPUT_FRAME + idx, map);
if (pipe->enable_viewfinder[idx])
if (info->padded_width > info->res.width)
{
frame->config_on_frame_enqueue.padded_width = info->padded_width;
- }
- else if ((info->padded_width < info->res.width) && (info->padded_width > 0))
+ } else if ((info->padded_width < info->res.width) && (info->padded_width > 0))
{
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
/* Only continuous streams have a tagger to which we can send the
* unlock message. */
- if (stream == NULL || !stream->config.continuous) {
+ if (!stream || !stream->config.continuous) {
IA_CSS_ERROR("invalid stream pointer");
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
}
/* @brief Set the state (Enable or Disable) of the Extension stage in the
- * given pipe.
+ * given pipe.
*/
enum ia_css_err
ia_css_pipe_set_qos_ext_state(struct ia_css_pipe *pipe, uint32_t fw_handle, bool enable)
IA_CSS_ENTER("");
/* Parameter Check */
- if (pipe == NULL || pipe->stream == NULL) {
+ if (!pipe || !pipe->stream) {
IA_CSS_ERROR("Invalid Pipe.");
err = IA_CSS_ERR_INVALID_ARGUMENTS;
} else if (!(pipe->config.acc_extension)) {
} else {
/* Query the threadid and stage_num for the Extension firmware*/
ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id);
- err = ia_css_pipeline_get_stage_from_fw(&(pipe->pipeline), fw_handle, &stage);
+ err = ia_css_pipeline_get_stage_from_fw(&pipe->pipeline, fw_handle, &stage);
if (err == IA_CSS_SUCCESS) {
/* Set the Extension State;. TODO: Add check for stage firmware.type (QOS)*/
err = ia_css_bufq_enqueue_psys_event(
- (uint8_t) IA_CSS_PSYS_SW_EVENT_STAGE_ENABLE_DISABLE,
- (uint8_t) thread_id,
- (uint8_t) stage->stage_num,
+ (uint8_t)IA_CSS_PSYS_SW_EVENT_STAGE_ENABLE_DISABLE,
+ (uint8_t)thread_id,
+ (uint8_t)stage->stage_num,
enable ? 1 : 0);
if (err == IA_CSS_SUCCESS) {
- if(enable)
- SH_CSS_QOS_STAGE_ENABLE(&(sh_css_sp_group.pipe[thread_id]),stage->stage_num);
+ if (enable)
+ SH_CSS_QOS_STAGE_ENABLE(&sh_css_sp_group.pipe[thread_id], stage->stage_num);
else
- SH_CSS_QOS_STAGE_DISABLE(&(sh_css_sp_group.pipe[thread_id]),stage->stage_num);
+ SH_CSS_QOS_STAGE_DISABLE(&sh_css_sp_group.pipe[thread_id], stage->stage_num);
}
}
}
IA_CSS_ENTER("");
/* Parameter Check */
- if (pipe == NULL || pipe->stream == NULL) {
+ if (!pipe || !pipe->stream) {
IA_CSS_ERROR("Invalid Pipe.");
err = IA_CSS_ERR_INVALID_ARGUMENTS;
} else if (!(pipe->config.acc_extension)) {
if (err == IA_CSS_SUCCESS) {
/* Get the Extension State */
- *enable = (SH_CSS_QOS_STAGE_IS_ENABLED(&(sh_css_sp_group.pipe[thread_id]),stage->stage_num)) ? true : false;
+ *enable = (SH_CSS_QOS_STAGE_IS_ENABLED(&sh_css_sp_group.pipe[thread_id], stage->stage_num)) ? true : false;
}
}
IA_CSS_LEAVE("err:%d handle:%u enable:%d", err, fw_handle, *enable);
fw = &sh_css_sp_fw;
/* Parameter Check */
- if (pipe == NULL || pipe->stream == NULL) {
+ if (!pipe || !pipe->stream) {
IA_CSS_ERROR("Invalid Pipe.");
err = IA_CSS_ERR_INVALID_ARGUMENTS;
} else if (!(pipe->config.acc_extension)) {
} else {
/* Query the thread_id and stage_num corresponding to the Extension firmware */
ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id);
- err = ia_css_pipeline_get_stage_from_fw(&(pipe->pipeline), fw_handle, &stage);
+ err = ia_css_pipeline_get_stage_from_fw(&pipe->pipeline, fw_handle, &stage);
if (err == IA_CSS_SUCCESS) {
/* Get the Extension State */
- enabled = (SH_CSS_QOS_STAGE_IS_ENABLED(&(sh_css_sp_group.pipe[thread_id]), stage->stage_num)) ? true : false;
+ enabled = (SH_CSS_QOS_STAGE_IS_ENABLED(&sh_css_sp_group.pipe[thread_id], stage->stage_num)) ? true : false;
/* Update mapped arg only when extension stage is not enabled */
if (enabled) {
IA_CSS_ERROR("Leaving: cannot update when stage is enabled.");
enum ia_css_err err = IA_CSS_SUCCESS;
int i;
struct ia_css_pipe *curr_pipe;
- uint32_t pipe_mask = 0;
+ u32 pipe_mask = 0;
- if ((curr_stream == NULL) ||
+ if ((!curr_stream) ||
(curr_stream->num_pipes == 0) ||
- (pipes == NULL) ||
- (do_crop_status == NULL)) {
+ (!pipes) ||
+ (!do_crop_status)) {
err = IA_CSS_ERR_INVALID_ARGUMENTS;
IA_CSS_LEAVE_ERR(err);
return err;
{
bool status = false;
- if ((curr_pipe != NULL) && enabled) {
+ if ((curr_pipe) && enabled) {
if ((curr_pipe->config.mode == IA_CSS_PIPE_MODE_PREVIEW) ||
(curr_pipe->config.mode == IA_CSS_PIPE_MODE_VIDEO) ||
(curr_pipe->config.mode == IA_CSS_PIPE_MODE_CAPTURE))
bool use_vf_pp_in_res = false;
bool use_capt_pp_in_res = false;
- if ((curr_pipe == NULL) ||
- (effective_res == NULL)) {
+ if ((!curr_pipe) ||
+ (!effective_res)) {
err = IA_CSS_ERR_INVALID_ARGUMENTS;
IA_CSS_LEAVE_ERR(err);
return err;
buffer_record = &hmm_buffer_record[0];
for (i = 0; i < MAX_HMM_BUFFER_NUM; i++) {
if (buffer_record->in_use) {
- if (buffer_record->h_vbuf != NULL)
+ if (buffer_record->h_vbuf)
ia_css_rmgr_rel_vbuf(hmm_buffer_pool, &buffer_record->h_vbuf);
sh_css_hmm_buffer_record_reset(buffer_record);
#else
buffer_record = &hmm_buffer_record[0];
for (i = 0; i < MAX_HMM_BUFFER_NUM; i++) {
if (buffer_record->in_use) {
- if (buffer_record->h_vbuf != NULL)
+ if (buffer_record->h_vbuf)
ia_css_rmgr_rel_vbuf(hmm_buffer_pool, &buffer_record->h_vbuf);
sh_css_hmm_buffer_record_reset(buffer_record);
}
static void
sh_css_hmm_buffer_record_reset(struct sh_css_hmm_buffer_record *buffer_record)
{
- assert(buffer_record != NULL);
+ assert(buffer_record);
buffer_record->in_use = false;
buffer_record->type = IA_CSS_BUFFER_TYPE_INVALID;
buffer_record->h_vbuf = NULL;
struct sh_css_hmm_buffer_record *buffer_record = NULL;
struct sh_css_hmm_buffer_record *out_buffer_record = NULL;
- assert(h_vbuf != NULL);
+ assert(h_vbuf);
assert((type > IA_CSS_BUFFER_TYPE_INVALID) && (type < IA_CSS_NUM_DYNAMIC_BUFFER_TYPE));
assert(kernel_ptr != 0);
for (i = 0; i < MAX_HMM_BUFFER_NUM; i++) {
if ((buffer_record->in_use) &&
(buffer_record->type == type) &&
- (buffer_record->h_vbuf != NULL) &&
+ (buffer_record->h_vbuf) &&
(buffer_record->h_vbuf->vptr == ddr_buffer_addr)) {
found_record = true;
break;
#define SH_CSS_BDS_FACTOR_8_00 (11)
#define NUM_BDS_FACTORS (12)
-#define PACK_BDS_FACTOR(factor) (1<<(factor))
+#define PACK_BDS_FACTOR(factor) (1 << (factor))
/* Following macros should match with the type enum ia_css_pipe_version in
* ia_css_pipe_public.h. The reason to add these macros is that enum type
/* Bits of fractional part of interpolation in vamem, [0,4095]->[0,255] */
#define SH_CSS_RGB_GAMMA_FRAC_BITS \
(SH_CSS_RGB_GAMMA_INPUT_BITS - SH_CSS_ISP_RGB_GAMMA_TABLE_SIZE_LOG2)
-#define SH_CSS_RGB_GAMMA_ONE (1 << SH_CSS_RGB_GAMMA_FRAC_BITS)
+#define SH_CSS_RGB_GAMMA_ONE BIT(SH_CSS_RGB_GAMMA_FRAC_BITS)
/* Bits of input of CCM, = 13, Y[0,8191],CgCo[-4096,4095] */
#define SH_CSS_YUV2RGB_CCM_INPUT_BITS SH_CSS_BAYER_BITS
#define SH_CSS_MAX_BQ_GRID_WIDTH 80
#define SH_CSS_MAX_BQ_GRID_HEIGHT 60
-/* The minimum dvs envelope is 12x12(for IPU2) to make sure the
+/* The minimum dvs envelope is 12x12(for IPU2) to make sure the
* invalid rows/columns that result from filter initialization are skipped. */
#define SH_CSS_MIN_DVS_ENVELOPE 12U
#define SH_CSS_MORPH_TABLE_GRID ISP_VEC_NELEMS
#define SH_CSS_MORPH_TABLE_ELEM_BYTES 2
#define SH_CSS_MORPH_TABLE_ELEMS_PER_DDR_WORD \
- (HIVE_ISP_DDR_WORD_BYTES/SH_CSS_MORPH_TABLE_ELEM_BYTES)
+ (HIVE_ISP_DDR_WORD_BYTES / SH_CSS_MORPH_TABLE_ELEM_BYTES)
#ifndef ISP2401
#define SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR (SH_CSS_MAX_BQ_GRID_WIDTH + 1)
#define NUM_TNR_FRAMES 2 /* FIXME */
-
#define MAX_NUM_DELAY_FRAMES MAX_NUM_VIDEO_DELAY_FRAMES
#else
/* Rules: these implement logic shared between the host code and ISP firmware.
The ISP firmware needs these rules to be applied at pre-processor time,
that's why these are macros, not functions. */
-#define _ISP_BQS(num) ((num)/2)
+#define _ISP_BQS(num) ((num) / 2)
#define _ISP_VECS(width) CEIL_DIV(width, ISP_VEC_NELEMS)
#define ISP_BQ_GRID_WIDTH(elements_per_line, deci_factor_log2) \
- CEIL_SHIFT(elements_per_line/2, deci_factor_log2)
+ CEIL_SHIFT(elements_per_line / 2, deci_factor_log2)
#define ISP_BQ_GRID_HEIGHT(lines_per_frame, deci_factor_log2) \
- CEIL_SHIFT(lines_per_frame/2, deci_factor_log2)
+ CEIL_SHIFT(lines_per_frame / 2, deci_factor_log2)
#define ISP_C_VECTORS_PER_LINE(elements_per_line) \
- _ISP_VECS(elements_per_line/2)
+ _ISP_VECS(elements_per_line / 2)
/* The morphing table is similar to the shading table in the sense that we
have 1 more value than we have cells in the grid. */
CEIL_SHIFT(_ISP_BQS(in_height), deci_factor_log2)
#define ISP_S3ATBL_VECTORS \
_ISP_VECS(SH_CSS_MAX_S3ATBL_WIDTH * \
- (sizeof(struct ia_css_3a_output)/sizeof(int32_t)))
+ (sizeof(struct ia_css_3a_output) / sizeof(int32_t)))
#define ISP_S3ATBL_HI_LO_STRIDE \
(ISP_S3ATBL_VECTORS * ISP_VEC_NELEMS)
#define ISP_S3ATBL_HI_LO_STRIDE_BYTES \
/* Viewfinder support */
#define __ISP_MAX_VF_OUTPUT_WIDTH(width, left_crop) \
- (width - 2*ISP_VEC_NELEMS + ((left_crop) ? 2 * ISP_VEC_NELEMS : 0))
+ (width - 2 * ISP_VEC_NELEMS + ((left_crop) ? 2 * ISP_VEC_NELEMS : 0))
#define __ISP_VF_OUTPUT_WIDTH_VECS(out_width, vf_log_downscale) \
(_ISP_VECS((out_width) >> (vf_log_downscale)))
/* Rules for computing the internal width. This is extremely complicated
* and definitely needs to be commented and explained. */
-#define _ISP_LEFT_CROP_EXTRA(left_crop) ((left_crop) > 0 ? 2*ISP_VEC_NELEMS : 0)
+#define _ISP_LEFT_CROP_EXTRA(left_crop) ((left_crop) > 0 ? 2 * ISP_VEC_NELEMS : 0)
#define __ISP_MIN_INTERNAL_WIDTH(num_chunks, pipelining, mode) \
- ((num_chunks) * (pipelining) * (1<<_ISP_LOG_VECTOR_STEP(mode)) * \
+ ((num_chunks) * (pipelining) * (1 << _ISP_LOG_VECTOR_STEP(mode)) * \
ISP_VEC_NELEMS)
#define __ISP_PADDED_OUTPUT_WIDTH(out_width, dvs_env_width, left_crop) \
((out_width) + MAX(dvs_env_width, _ISP_LEFT_CROP_EXTRA(left_crop)))
#define __ISP_CHUNK_STRIDE_ISP(mode) \
- ((1<<_ISP_LOG_VECTOR_STEP(mode)) * ISP_VEC_NELEMS)
+ ((1 << _ISP_LOG_VECTOR_STEP(mode)) * ISP_VEC_NELEMS)
#define __ISP_CHUNK_STRIDE_DDR(c_subsampling, num_chunks) \
((c_subsampling) * (num_chunks) * HIVE_ISP_DDR_WORD_BYTES)
((enable_ds) ? \
SH_CSS_MAX_SENSOR_WIDTH :\
(enable_fixed_bayer_ds) ? \
- CEIL_MUL(SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH_DEC, 4*ISP_VEC_NELEMS) : \
+ CEIL_MUL(SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH_DEC, 4 * ISP_VEC_NELEMS) : \
(enable_raw_bin) ? \
- CEIL_MUL(SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH, 4*ISP_VEC_NELEMS) : \
+ CEIL_MUL(SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH, 4 * ISP_VEC_NELEMS) : \
(enable_continuous) ? \
SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH \
: max_internal_width)
#ifndef ISP2401
static const char *release_version = STR(irci_stable_candrpv_0415_20150521_0458);
#else
-static const char *release_version = STR(irci_ecr-master_20150911_0724);
+static const char *release_version = STR(irci_ecr - master_20150911_0724);
#endif
#define MAX_FW_REL_VER_NAME 300
struct ia_css_fw_info sh_css_sp_fw;
struct ia_css_blob_descr *sh_css_blob_info; /* Only ISP blob info (no SP) */
-unsigned sh_css_num_binaries; /* This includes 1 SP binary */
+unsigned int sh_css_num_binaries; /* This includes 1 SP binary */
static struct fw_param *fw_minibuffer;
-
char *sh_css_get_fw_version(void)
{
return FW_rel_ver_name;
}
-
/*
* Split the loaded firmware into blobs
*/
/* Setup sp/sp1 binary */
static enum ia_css_err
-setup_binary(struct ia_css_fw_info *fw, const char *fw_data, struct ia_css_fw_info *sh_css_fw, unsigned binary_id)
+setup_binary(struct ia_css_fw_info *fw, const char *fw_data, struct ia_css_fw_info *sh_css_fw, unsigned int binary_id)
{
const char *blob_data;
- if ((fw == NULL) || (fw_data == NULL))
+ if ((!fw) || (!fw_data))
return IA_CSS_ERR_INVALID_ARGUMENTS;
blob_data = fw_data + fw->blob.offset;
*sh_css_fw = *fw;
sh_css_fw->blob.code = vmalloc(fw->blob.size);
- if (sh_css_fw->blob.code == NULL)
+ if (!sh_css_fw->blob.code)
return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
memcpy((void *)sh_css_fw->blob.code, blob_data, fw->blob.size);
return IA_CSS_SUCCESS;
}
+
enum ia_css_err
-sh_css_load_blob_info(const char *fw, const struct ia_css_fw_info *bi, struct ia_css_blob_descr *bd, unsigned index)
+sh_css_load_blob_info(const char *fw, const struct ia_css_fw_info *bi, struct ia_css_blob_descr *bd, unsigned int index)
{
const char *name;
const unsigned char *blob;
- if ((fw == NULL) || (bd == NULL))
+ if ((!fw) || (!bd))
return IA_CSS_ERR_INVALID_ARGUMENTS;
/* Special case: only one binary in fw */
- if (bi == NULL) bi = (const struct ia_css_fw_info *)fw;
+ if (!bi) bi = (const struct ia_css_fw_info *)fw;
name = fw + bi->blob.prog_name_offset;
blob = (const unsigned char *)fw + bi->blob.offset;
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
- if ((bi->blob.offset % (1UL<<(ISP_PMEM_WIDTH_LOG2-3))) != 0)
+ if ((bi->blob.offset % (1UL << (ISP_PMEM_WIDTH_LOG2 - 3))) != 0)
return IA_CSS_ERR_INVALID_ARGUMENTS;
bd->blob = blob;
sh_css_load_firmware(const char *fw_data,
unsigned int fw_size)
{
- unsigned i;
+ unsigned int i;
struct ia_css_fw_info *binaries;
struct sh_css_fw_bi_file_h *file_header;
bool valid_firmware = false;
if (bi->type != ia_css_isp_firmware)
return IA_CSS_ERR_INTERNAL_ERROR;
- if (sh_css_blob_info == NULL) /* cannot happen but KW does not see this */
+ if (!sh_css_blob_info) /* cannot happen but KW does not see this */
return IA_CSS_ERR_INTERNAL_ERROR;
sh_css_blob_info[i - NUM_OF_SPS] = bd;
}
void sh_css_unload_firmware(void)
{
-
/* release firmware minibuffer */
if (fw_minibuffer) {
unsigned int i = 0;
+
for (i = 0; i < sh_css_num_binaries; i++) {
if (fw_minibuffer[i].name)
kfree((void *)fw_minibuffer[i].name);
}
hrt_vaddress
-sh_css_load_blob(const unsigned char *blob, unsigned size)
+sh_css_load_blob(const unsigned char *blob, unsigned int size)
{
hrt_vaddress target_addr = mmgr_malloc(size);
/* this will allocate memory aligned to a DDR word boundary which
is required for the CSS DMA to read the instructions. */
- assert(blob != NULL);
- if (target_addr)
+ assert(blob);
+ if (target_addr)
mmgr_store(target_addr, blob, size);
return target_addr;
}
extern struct ia_css_fw_info sh_css_bl_fw;
#endif /* HAS_BL */
extern struct ia_css_blob_descr *sh_css_blob_info;
-extern unsigned sh_css_num_binaries;
+extern unsigned int sh_css_num_binaries;
char
*sh_css_get_fw_version(void);
void sh_css_unload_firmware(void);
-hrt_vaddress sh_css_load_blob(const unsigned char *blob, unsigned size);
+hrt_vaddress sh_css_load_blob(const unsigned char *blob, unsigned int size);
enum ia_css_err
sh_css_load_blob_info(const char *fw, const struct ia_css_fw_info *bi, struct ia_css_blob_descr *bd, unsigned int i);
#include <math_support.h>
#define sISP_REG_BIT ISP_VEC_ELEMBITS
-#define uISP_REG_BIT ((unsigned)(sISP_REG_BIT-1))
-#define sSHIFT (16-sISP_REG_BIT)
-#define uSHIFT ((unsigned)(16-uISP_REG_BIT))
-#define sFRACTION_BITS_FITTING(a) (a-sSHIFT)
-#define uFRACTION_BITS_FITTING(a) ((unsigned)(a-uSHIFT))
-#define sISP_VAL_MIN (-(1<<uISP_REG_BIT))
-#define sISP_VAL_MAX ((1<<uISP_REG_BIT)-1)
-#define uISP_VAL_MIN ((unsigned)0)
-#define uISP_VAL_MAX ((unsigned)((1<<uISP_REG_BIT)-1))
+#define uISP_REG_BIT ((unsigned int)(sISP_REG_BIT - 1))
+#define sSHIFT (16 - sISP_REG_BIT)
+#define uSHIFT ((unsigned int)(16 - uISP_REG_BIT))
+#define sFRACTION_BITS_FITTING(a) (a - sSHIFT)
+#define uFRACTION_BITS_FITTING(a) ((unsigned int)(a - uSHIFT))
+#define sISP_VAL_MIN (-(1 << uISP_REG_BIT))
+#define sISP_VAL_MAX ((1 << uISP_REG_BIT) - 1)
+#define uISP_VAL_MIN (0U)
+#define uISP_VAL_MAX ((unsigned int)((1 << uISP_REG_BIT) - 1))
/* a:fraction bits for 16bit precision, b:fraction bits for ISP precision */
#define sDIGIT_FITTING(v, a, b) \
- min_t(int, max_t(int, (((v)>>sSHIFT) >> max(sFRACTION_BITS_FITTING(a)-(b), 0)), \
+ min_t(int, max_t(int, (((v) >> sSHIFT) >> max(sFRACTION_BITS_FITTING(a) - (b), 0)), \
sISP_VAL_MIN), sISP_VAL_MAX)
#define uDIGIT_FITTING(v, a, b) \
- min((unsigned)max((unsigned)(((v)>>uSHIFT) \
- >> max((int)(uFRACTION_BITS_FITTING(a)-(b)), 0)), \
+ min((unsigned int)max((unsigned)(((v) >> uSHIFT) \
+ >> max((int)(uFRACTION_BITS_FITTING(a) - (b)), 0)), \
uISP_VAL_MIN), uISP_VAL_MAX)
#endif /* __SH_CSS_FRAC_H */
if (!idle)
IA_CSS_WARNING("ISP not idle");
- for (ch=0; ch<N_FIFO_CHANNEL; ch++) {
+ for (ch = 0; ch < N_FIFO_CHANNEL; ch++) {
fifo_channel_state_t state;
+
fifo_channel_get_state(FIFO_MONITOR0_ID, ch, &state);
if (state.fifo_valid) {
IA_CSS_WARNING("FIFO channel %d is not empty", ch);
while (!sp_ctrl_getbit(SP0_ID, SP_SC_REG, SP_IDLE_BIT) &&
((irq_reg_load(IRQ0_ID,
_HRT_IRQ_CONTROLLER_STATUS_REG_IDX) &
- (1U<<(irq_id + IRQ_SW_CHANNEL_OFFSET))) == 0)) {
+ (1U << (irq_id + IRQ_SW_CHANNEL_OFFSET))) == 0)) {
hrt_sleep();
}
#define SH_CSS_ENABLE_METADATA_THREAD
#endif
-
/*
* SH_CSS_MAX_SP_THREADS:
* sp threads visible to host with connected communication queues
hrt_vaddress tetra_batr_y;
hrt_vaddress dvs_6axis_params_y;
};
+
#define SIZE_OF_SH_CSS_DDR_ADDRESS_MAP_STRUCT \
(SIZE_OF_HRT_VADDRESS + \
(SH_CSS_MAX_STAGES * IA_CSS_NUM_MEMORIES * SIZE_OF_HRT_VADDRESS) + \
struct ia_css_isp_parameter_set_info {
struct sh_css_ddr_address_map mem_map;/** pointers to Parameters in ISP format IMPT:
This should be first member of this struct */
- uint32_t isp_parameters_id;/** Unique ID to track which config was actually applied to a particular frame */
+ u32 isp_parameters_id;/** Unique ID to track which config was actually applied to a particular frame */
ia_css_ptr output_frame_ptr;/** Output frame to which this config has to be applied (optional) */
};
struct ia_css_frame *out_vf_frame; /* viewfinder output frame */
bool copy_vf;
bool copy_output;
- unsigned vf_downscale_log2;
+ unsigned int vf_downscale_log2;
};
#if SP_DEBUG == SP_DEBUG_DUMP
#define SH_CSS_SP_DBG_TRACE_DEPTH (40)
struct sh_css_sp_debug_trace {
- uint16_t frame;
- uint16_t line;
- uint16_t pixel_distance;
- uint16_t mipi_used_dword;
- uint16_t sp_index;
+ u16 frame;
+ u16 line;
+ u16 pixel_distance;
+ u16 mipi_used_dword;
+ u16 sp_index;
};
struct sh_css_sp_debug_state {
- uint16_t if_start_line;
- uint16_t if_start_column;
- uint16_t if_cropped_height;
- uint16_t if_cropped_width;
+ u16 if_start_line;
+ u16 if_start_column;
+ u16 if_cropped_height;
+ u16 if_cropped_width;
unsigned int index;
struct sh_css_sp_debug_trace
trace[SH_CSS_SP_DBG_TRACE_DEPTH];
#define SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS (13)
struct sh_css_sp_debug_trace {
- uint16_t time_stamp;
- uint16_t location; /* bit 15..13 = file_id, 12..0 = line nr. */
- uint32_t data;
+ u16 time_stamp;
+ u16 location; /* bit 15..13 = file_id, 12..0 = line nr. */
+ u32 data;
};
struct sh_css_sp_debug_state {
struct sh_css_sp_debug_trace
trace[SH_CSS_SP_DBG_NR_OF_TRACES][SH_CSS_SP_DBG_TRACE_DEPTH];
- uint16_t index_last[SH_CSS_SP_DBG_NR_OF_TRACES];
- uint8_t index[SH_CSS_SP_DBG_NR_OF_TRACES];
+ u16 index_last[SH_CSS_SP_DBG_NR_OF_TRACES];
+ u8 index[SH_CSS_SP_DBG_NR_OF_TRACES];
};
#elif SP_DEBUG == SP_DEBUG_MINIMAL
#endif
-
struct sh_css_sp_debug_command {
/*
* The DMA software-mask,
* writing request through DMA Channel 1 and the reading request
* through DMA channel 2 are both disabled. The others are enabled.
*/
- uint32_t dma_sw_reg;
+ u32 dma_sw_reg;
};
#if !defined(HAS_NO_INPUT_FORMATTER)
/* SP input formatter configuration.*/
struct sh_css_sp_input_formatter_set {
- uint32_t stream_format;
+ u32 stream_format;
input_formatter_cfg_t config_a;
input_formatter_cfg_t config_b;
};
/* SP configuration information */
struct sh_css_sp_config {
- uint8_t no_isp_sync; /* Signal host immediately after start */
- uint8_t enable_raw_pool_locking; /** Enable Raw Buffer Locking for HALv3 Support */
- uint8_t lock_all;
+ u8 no_isp_sync; /* Signal host immediately after start */
+ u8 enable_raw_pool_locking; /** Enable Raw Buffer Locking for HALv3 Support */
+ u8 lock_all;
/** If raw buffer locking is enabled, this flag indicates whether raw
frames are locked when their EOF event is successfully sent to the
host (true) or when they are passed to the preview/video pipe
(false). */
#if !defined(HAS_NO_INPUT_FORMATTER)
struct {
- uint8_t a_changed;
- uint8_t b_changed;
- uint8_t isp_2ppc;
+ u8 a_changed;
+ u8 b_changed;
+ u8 isp_2ppc;
struct sh_css_sp_input_formatter_set set[SH_CSS_MAX_IF_CONFIGS]; /* CSI-2 port is used as index. */
} input_formatter;
#endif
tpg_cfg_t tpg;
prbs_cfg_t prbs;
input_system_cfg_t input_circuit;
- uint8_t input_circuit_cfg_changed;
- uint32_t mipi_sizes_for_check[N_CSI_PORTS][IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT];
+ u8 input_circuit_cfg_changed;
+ u32 mipi_sizes_for_check[N_CSI_PORTS][IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT];
#endif
#if !defined(HAS_NO_INPUT_SYSTEM)
- uint8_t enable_isys_event_queue;
+ u8 enable_isys_event_queue;
#endif
- uint8_t disable_cont_vf;
+ u8 disable_cont_vf;
};
enum sh_css_stage_type {
SH_CSS_SP_STAGE_TYPE = 0,
SH_CSS_ISP_STAGE_TYPE = 1
};
+
#define SH_CSS_NUM_STAGE_TYPES 2
-#define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS (1 << 0)
+#define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS BIT(0)
#define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS_MASK \
- ((SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS << SH_CSS_MAX_SP_THREADS)-1)
+ ((SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS << SH_CSS_MAX_SP_THREADS) - 1)
#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2401)
struct sh_css_sp_pipeline_terminal {
* Only when all streams are configured, the CSI RX is started for that port.
*/
struct sh_css_sp_pipeline_io_status {
- uint32_t active[N_INPUT_SYSTEM_CSI_PORT]; /** registered streams */
- uint32_t running[N_INPUT_SYSTEM_CSI_PORT]; /** configured streams */
+ u32 active[N_INPUT_SYSTEM_CSI_PORT]; /** registered streams */
+ u32 running[N_INPUT_SYSTEM_CSI_PORT]; /** configured streams */
};
#endif
/* Information for a pipeline */
struct sh_css_sp_pipeline {
- uint32_t pipe_id; /* the pipe ID */
- uint32_t pipe_num; /* the dynamic pipe number */
- uint32_t thread_id; /* the sp thread ID */
- uint32_t pipe_config; /* the pipe config */
- uint32_t pipe_qos_config; /* Bitmap of multiple QOS extension fw state.
+ u32 pipe_id; /* the pipe ID */
+ u32 pipe_num; /* the dynamic pipe number */
+ u32 thread_id; /* the sp thread ID */
+ u32 pipe_config; /* the pipe config */
+ u32 pipe_qos_config; /* Bitmap of multiple QOS extension fw state.
(0xFFFFFFFF) indicates non QOS pipe.*/
- uint32_t inout_port_config;
- uint32_t required_bds_factor;
- uint32_t dvs_frame_delay;
+ u32 inout_port_config;
+ u32 required_bds_factor;
+ u32 dvs_frame_delay;
#if !defined(HAS_NO_INPUT_SYSTEM)
- uint32_t input_system_mode; /* enum ia_css_input_mode */
- uint32_t port_id; /* port_id for input system */
+ u32 input_system_mode; /* enum ia_css_input_mode */
+ u32 port_id; /* port_id for input system */
#endif
- uint32_t num_stages; /* the pipe config */
- uint32_t running; /* needed for pipe termination */
+ u32 num_stages; /* the pipe config */
+ u32 running; /* needed for pipe termination */
hrt_vaddress sp_stage_addr[SH_CSS_MAX_STAGES];
hrt_vaddress scaler_pp_lut; /* Early bound LUT */
- uint32_t dummy; /* stage ptr is only used on sp but lives in
+ u32 dummy; /* stage ptr is only used on sp but lives in
this struct; needs cleanup */
- int32_t num_execs; /* number of times to run if this is
+ s32 num_execs; /* number of times to run if this is
an acceleration pipe. */
#if defined(SH_CSS_ENABLE_METADATA)
struct {
- uint32_t format; /* Metadata format in hrt format */
- uint32_t width; /* Width of a line */
- uint32_t height; /* Number of lines */
- uint32_t stride; /* Stride (in bytes) per line */
- uint32_t size; /* Total size (in bytes) */
+ u32 format; /* Metadata format in hrt format */
+ u32 width; /* Width of a line */
+ u32 height; /* Number of lines */
+ u32 stride; /* Stride (in bytes) per line */
+ u32 size; /* Total size (in bytes) */
hrt_vaddress cont_buf; /* Address of continuous buffer */
} metadata;
#endif
#if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS)
- uint32_t output_frame_queue_id;
+ u32 output_frame_queue_id;
#endif
union {
struct {
- uint32_t bytes_available;
+ u32 bytes_available;
} bin;
struct {
- uint32_t height;
- uint32_t width;
- uint32_t padded_width;
- uint32_t max_input_width;
- uint32_t raw_bit_depth;
+ u32 height;
+ u32 width;
+ u32 padded_width;
+ u32 max_input_width;
+ u32 raw_bit_depth;
} raw;
} copy;
#ifdef ISP2401
/* Parameters passed to Shading Correction kernel. */
struct {
- uint32_t internal_frame_origin_x_bqs_on_sctbl; /* Origin X (bqs) of internal frame on shading table */
- uint32_t internal_frame_origin_y_bqs_on_sctbl; /* Origin Y (bqs) of internal frame on shading table */
+ u32 internal_frame_origin_x_bqs_on_sctbl; /* Origin X (bqs) of internal frame on shading table */
+ u32 internal_frame_origin_y_bqs_on_sctbl; /* Origin Y (bqs) of internal frame on shading table */
} shading;
#endif
};
* Multiple boolean flags can be stored in an
* integer
*/
- uint8_t num; /* Stage number */
- uint8_t isp_online;
- uint8_t isp_copy_vf;
- uint8_t isp_copy_output;
- uint8_t sp_enable_xnr;
- uint8_t isp_deci_log_factor;
- uint8_t isp_vf_downscale_bits;
- uint8_t deinterleaved;
+ u8 num; /* Stage number */
+ u8 isp_online;
+ u8 isp_copy_vf;
+ u8 isp_copy_output;
+ u8 sp_enable_xnr;
+ u8 isp_deci_log_factor;
+ u8 isp_vf_downscale_bits;
+ u8 deinterleaved;
/*
* NOTE: Programming the input circuit can only be done at the
* start of a session. It is illegal to program it during execution
* The input circuit defines the connectivity
*/
- uint8_t program_input_circuit;
+ u8 program_input_circuit;
/* enum ia_css_pipeline_stage_sp_func func; */
- uint8_t func;
+ u8 func;
/* The type of the pipe-stage */
/* enum sh_css_stage_type stage_type; */
- uint8_t stage_type;
- uint8_t num_stripes;
- uint8_t isp_pipe_version;
+ u8 stage_type;
+ u8 num_stripes;
+ u8 isp_pipe_version;
struct {
- uint8_t vf_output;
- uint8_t s3a;
- uint8_t sdis;
- uint8_t dvs_stats;
- uint8_t lace_stats;
+ u8 vf_output;
+ u8 s3a;
+ u8 sdis;
+ u8 dvs_stats;
+ u8 lace_stats;
} enable;
/* Add padding to come to a word boundary */
/* unsigned char padding[0]; */
hrt_vaddress xmem_bin_addr;
hrt_vaddress xmem_map_addr;
- uint16_t top_cropping;
- uint16_t row_stripes_height;
- uint16_t row_stripes_overlap_lines;
- uint8_t if_config_index; /* Which should be applied by this stage. */
+ u16 top_cropping;
+ u16 row_stripes_height;
+ u16 row_stripes_overlap_lines;
+ u8 if_config_index; /* Which should be applied by this stage. */
};
/*
struct ia_css_metadata metadata;
struct frame_data_wrapper {
hrt_vaddress frame_data;
- uint32_t flashed;
- uint32_t exp_id;
- uint32_t isp_parameters_id; /** Unique ID to track which config was
+ u32 flashed;
+ u32 exp_id;
+ u32 isp_parameters_id; /** Unique ID to track which config was
actually applied to a particular frame */
#if CONFIG_ON_FRAME_ENQUEUE()
struct sh_css_config_on_frame_enqueue config_on_frame_enqueue;
* Size of the struct is checked by sp.hive.c.
*/
#if !defined(__ISP)
- CSS_ALIGN(uint64_t cookie_ptr, 8); /* TODO: check if this alignment is needed */
- uint64_t kernel_ptr;
+ CSS_ALIGN(u64 cookie_ptr, 8); /* TODO: check if this alignment is needed */
+ u64 kernel_ptr;
#else
- CSS_ALIGN(struct { uint32_t a[2]; } cookie_ptr, 8); /* TODO: check if this alignment is needed */
- struct { uint32_t a[2]; } kernel_ptr;
+ CSS_ALIGN(struct { u32 a[2]; } cookie_ptr, 8); /* TODO: check if this alignment is needed */
+ struct { u32 a[2]; } kernel_ptr;
#endif
struct ia_css_time_meas timing_data;
clock_value_t isys_eof_clock_tick;
};
+
#if CONFIG_ON_FRAME_ENQUEUE()
#define SIZE_OF_FRAME_STRUCT \
(SIZE_OF_HRT_VADDRESS + \
};
struct sh_css_event_irq_mask {
- uint16_t or_mask;
- uint16_t and_mask;
+ u16 or_mask;
+ u16 and_mask;
};
+
#define SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT \
(2 * sizeof(uint16_t))
* Don't use enum host2sp_commands, because the sizeof an enum is
* compiler dependent and thus non-portable
*/
- uint32_t host2sp_command;
+ u32 host2sp_command;
/*
* The frame buffers that are reused by the
#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401)
hrt_vaddress host2sp_mipi_frames[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM];
hrt_vaddress host2sp_mipi_metadata[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM];
- uint32_t host2sp_num_mipi_frames[N_CSI_PORTS];
+ u32 host2sp_num_mipi_frames[N_CSI_PORTS];
#endif
- uint32_t host2sp_cont_avail_num_raw_frames;
- uint32_t host2sp_cont_extra_num_raw_frames;
- uint32_t host2sp_cont_target_num_raw_frames;
+ u32 host2sp_cont_avail_num_raw_frames;
+ u32 host2sp_cont_extra_num_raw_frames;
+ u32 host2sp_cont_target_num_raw_frames;
struct sh_css_event_irq_mask host2sp_event_irq_mask[NR_OF_PIPELINES];
};
* The queues for the events.
*/
ia_css_circbuf_desc_t host2sp_psys_event_queue_desc;
+
ia_css_circbuf_elem_t host2sp_psys_event_queue_elems
[IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE];
ia_css_circbuf_desc_t sp2host_psys_event_queue_desc;
+
ia_css_circbuf_elem_t sp2host_psys_event_queue_elems
[IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE];
* The queues for the ISYS events.
*/
ia_css_circbuf_desc_t host2sp_isys_event_queue_desc;
+
ia_css_circbuf_elem_t host2sp_isys_event_queue_elems
[IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE];
ia_css_circbuf_desc_t sp2host_isys_event_queue_desc;
+
ia_css_circbuf_elem_t sp2host_isys_event_queue_elems
[IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE];
/*
* CHECK: are these last two present on the 2401 ?
*/
ia_css_circbuf_desc_t host2sp_tag_cmd_queue_desc;
+
ia_css_circbuf_elem_t host2sp_tag_cmd_queue_elems
[IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE];
#endif
/* For Acceleration API: Flush FW (shared buffer pointer) arguments */
void sh_css_flush(struct ia_css_acc_fw *fw);
-
void
sh_css_binary_args_reset(struct sh_css_binary_args *args);
sh_css_store_sp_group_to_ddr(void);
hrt_vaddress
-sh_css_store_sp_stage_to_ddr(unsigned pipe, unsigned stage);
+sh_css_store_sp_stage_to_ddr(unsigned int pipe, unsigned int stage);
hrt_vaddress
-sh_css_store_isp_stage_to_ddr(unsigned pipe, unsigned stage);
-
+sh_css_store_isp_stage_to_ddr(unsigned int pipe, unsigned int stage);
void
sh_css_update_uds_and_crop_info(
const struct ia_css_vector *motion_vector,
struct sh_css_uds_info *uds, /* out */
struct sh_css_crop_pos *sp_out_crop_pos, /* out */
+
bool enable_zoom
);
IA_CSS_PIPE_ID_ACC
#endif
};
+
#ifdef ISP2401
-#define IA_CSS_PIPE_ID_NUM (IA_CSS_PIPE_ID_ACC+1)
+#define IA_CSS_PIPE_ID_NUM (IA_CSS_PIPE_ID_ACC + 1)
#endif
struct ia_css_pipe_extra_config {
static void
clear_histogram(struct sh_css_pc_histogram *histogram)
{
- unsigned i;
+ unsigned int i;
- assert(histogram != NULL);
+ assert(histogram);
for (i = 0; i < histogram->length; i++) {
histogram->run[i] = 0;
}
static void
-make_histogram(struct sh_css_pc_histogram *histogram, unsigned length)
+make_histogram(struct sh_css_pc_histogram *histogram, unsigned int length)
{
- assert(histogram != NULL);
+ assert(histogram);
if (histogram->length)
return;
insert_binary_metrics(struct sh_css_binary_metrics **l,
struct sh_css_binary_metrics *metrics)
{
- assert(l != NULL);
- assert(*l != NULL);
- assert(metrics != NULL);
+ assert(l);
+ assert(*l);
+ assert(metrics);
for (; *l; l = &(*l)->next)
if (*l == metrics)
void
sh_css_metrics_start_binary(struct sh_css_binary_metrics *metrics)
{
- assert(metrics != NULL);
+ assert(metrics);
if (!pc_histogram_enabled)
return;
unsigned int resume_sc = 0;
#endif
-
#if MULTIPLE_PCS
int i;
unsigned int pc_tab[NOF_PCS];
#include <type_support.h>
struct sh_css_pc_histogram {
- unsigned length;
- unsigned *run;
- unsigned *stall;
- unsigned *msink;
+ unsigned int length;
+ unsigned int *run;
+ unsigned int *stall;
+ unsigned int *msink;
};
struct sh_css_binary_metrics {
- unsigned mode;
- unsigned id;
+ unsigned int mode;
+ unsigned int id;
struct sh_css_pc_histogram isp_histogram;
struct sh_css_pc_histogram sp_histogram;
struct sh_css_binary_metrics *next;
};
struct ia_css_frame_metrics {
- unsigned num_frames;
+ unsigned int num_frames;
};
struct sh_css_metrics {
#include "sw_event_global.h" /* IA_CSS_PSYS_SW_EVENT_MIPI_BUFFERS_READY */
#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401)
-static uint32_t ref_count_mipi_allocation[N_CSI_PORTS]; /* Initialized in mipi_init */
+static u32 ref_count_mipi_allocation[N_CSI_PORTS]; /* Initialized in mipi_init */
#endif
enum ia_css_err
switch (pipe->stream->config.mode) {
case IA_CSS_INPUT_MODE_BUFFERED_SENSOR:
- port = (unsigned int) pipe->stream->config.source.port.port;
+ port = (unsigned int)pipe->stream->config.source.port.port;
max_ports = N_CSI_PORTS;
break;
case IA_CSS_INPUT_MODE_TPG:
- port = (unsigned int) pipe->stream->config.source.tpg.id;
+ port = (unsigned int)pipe->stream->config.source.tpg.id;
max_ports = N_CSS_TPG_IDS;
break;
case IA_CSS_INPUT_MODE_PRBS:
- port = (unsigned int) pipe->stream->config.source.prbs.id;
+ port = (unsigned int)pipe->stream->config.source.prbs.id;
max_ports = N_CSS_PRBS_IDS;
break;
default:
ia_css_mipi_frame_enable_check_on_size(const enum mipi_port_id port,
const unsigned int size_mem_words)
{
- uint32_t idx;
+ u32 idx;
enum ia_css_err err = IA_CSS_ERR_RESOURCE_NOT_AVAILABLE;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"allocate_mipi_frames(%p) enter:\n", pipe);
- assert(pipe != NULL);
- assert(pipe->stream != NULL);
- if ((pipe == NULL) || (pipe->stream == NULL)) {
+ assert(pipe);
+ assert(pipe->stream);
+ if ((!pipe) || (!pipe->stream)) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"allocate_mipi_frames(%p) exit: pipe or stream is null.\n",
pipe);
}
#ifndef ISP2401
- port = (unsigned int) pipe->stream->config.source.port.port;
+ port = (unsigned int)pipe->stream->config.source.port.port;
assert(port < N_CSI_PORTS);
if (port >= N_CSI_PORTS) {
#else
#ifdef USE_INPUT_SYSTEM_VERSION_2401
err = calculate_mipi_buff_size(
- &(pipe->stream->config),
- &(my_css.mipi_frame_size[port]));
+ &pipe->stream->config,
+ &my_css.mipi_frame_size[port]);
#endif
#if defined(USE_INPUT_SYSTEM_VERSION_2)
/* Incremental allocation (per stream), not for all streams at once. */
{ /* limit the scope of i,j */
- unsigned i, j;
+ unsigned int i, j;
+
for (i = 0; i < my_css.num_mipi_frames[port]; i++) {
/* free previous frame */
if (my_css.mipi_frames[port][i]) {
}
if (info->metadata_info.size > 0) {
/* free previous metadata buffer */
- if (my_css.mipi_metadata[port][i] != NULL) {
+ if (my_css.mipi_metadata[port][i]) {
ia_css_metadata_free(my_css.mipi_metadata[port][i]);
my_css.mipi_metadata[port][i] = NULL;
}
if (i < my_css.num_mipi_frames[port]) {
/* allocate new metadata buffer */
my_css.mipi_metadata[port][i] = ia_css_metadata_allocate(&info->metadata_info);
- if (my_css.mipi_metadata[port][i] == NULL) {
+ if (!my_css.mipi_metadata[port][i]) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"allocate_mipi_metadata(%p, %d) failed.\n",
pipe, port);
"free_mipi_frames(%p) enter:\n", pipe);
/* assert(pipe != NULL); TEMP: TODO: Should be assert only. */
- if (pipe != NULL) {
- assert(pipe->stream != NULL);
- if ((pipe == NULL) || (pipe->stream == NULL)) {
+ if (pipe) {
+ assert(pipe->stream);
+ if ((!pipe) || (!pipe->stream)) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"free_mipi_frames(%p) exit: error: pipe or stream is null.\n",
pipe);
}
#ifndef ISP2401
- port = (unsigned int) pipe->stream->config.source.port.port;
+ port = (unsigned int)pipe->stream->config.source.port.port;
assert(port < N_CSI_PORTS);
if (port >= N_CSI_PORTS) {
#else
if (ref_count_mipi_allocation[port] == 0) {
/* no streams are using this buffer, so free it */
unsigned int i;
+
for (i = 0; i < my_css.num_mipi_frames[port]; i++) {
- if (my_css.mipi_frames[port][i] != NULL) {
+ if (my_css.mipi_frames[port][i]) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"free_mipi_frames(port=%d, num=%d).\n", port, i);
ia_css_frame_free(my_css.mipi_frames[port][i]);
my_css.mipi_frames[port][i] = NULL;
}
- if (my_css.mipi_metadata[port][i] != NULL) {
+ if (my_css.mipi_metadata[port][i]) {
ia_css_metadata_free(my_css.mipi_metadata[port][i]);
my_css.mipi_metadata[port][i] = NULL;
}
/* AM TEMP: free-ing all mipi buffers just like a legacy code. */
for (port = CSI_PORT0_ID; port < N_CSI_PORTS; port++) {
unsigned int i;
+
for (i = 0; i < my_css.num_mipi_frames[port]; i++) {
- if (my_css.mipi_frames[port][i] != NULL) {
+ if (my_css.mipi_frames[port][i]) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"free_mipi_frames(port=%d, num=%d).\n", port, i);
ia_css_frame_free(my_css.mipi_frames[port][i]);
my_css.mipi_frames[port][i] = NULL;
}
- if (my_css.mipi_metadata[port][i] != NULL) {
+ if (my_css.mipi_metadata[port][i]) {
ia_css_metadata_free(my_css.mipi_metadata[port][i]);
my_css.mipi_metadata[port][i] = NULL;
}
IA_CSS_ENTER_PRIVATE("pipe=%p", pipe);
- assert(pipe != NULL);
- assert(pipe->stream != NULL);
- if (pipe == NULL || pipe->stream == NULL) {
+ assert(pipe);
+ assert(pipe->stream);
+ if (!pipe || !pipe->stream) {
IA_CSS_ERROR("pipe or stream is null");
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
}
#ifndef ISP2401
- port = (unsigned int) pipe->stream->config.source.port.port;
+ port = (unsigned int)pipe->stream->config.source.port.port;
assert(port < N_CSI_PORTS);
if (port >= N_CSI_PORTS) {
IA_CSS_ERROR("invalid port specified (%d)", port);
sh_css_mmu_set_page_table_base_index(hrt_data base_index)
{
int i;
+
IA_CSS_ENTER_PRIVATE("base_index=0x%08x\n", base_index);
for (i = 0; i < N_MMU_ID; i++) {
mmu_ID_t mmu_id = i;
+
mmu_set_page_table_base_index(mmu_id, base_index);
mmu_invalidate_cache(mmu_id);
}
struct ia_css_dvs_6axis_config *dvs_config = NULL;
dvs_config = (struct ia_css_dvs_6axis_config *)sh_css_malloc(sizeof(struct ia_css_dvs_6axis_config));
- if (dvs_config == NULL) {
+ if (!dvs_config) {
IA_CSS_ERROR("out of memory");
err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
- }
- else
+ } else
{ /*Initialize new struct with latest config settings*/
- if (NULL != dvs_config_src) {
+ if (dvs_config_src) {
dvs_config->width_y = width_y = dvs_config_src->width_y;
dvs_config->height_y = height_y = dvs_config_src->height_y;
dvs_config->width_uv = width_uv = dvs_config_src->width_uv;
dvs_config->height_uv = height_uv = dvs_config_src->height_uv;
IA_CSS_LOG("alloc_dvs_6axis_table Y: W %d H %d", width_y, height_y);
- }
- else if (NULL != frame_res) {
+ } else if (frame_res) {
dvs_config->width_y = width_y = DVS_TABLE_IN_BLOCKDIM_X_LUMA(frame_res->width);
dvs_config->height_y = height_y = DVS_TABLE_IN_BLOCKDIM_Y_LUMA(frame_res->height);
dvs_config->width_uv = width_uv = DVS_TABLE_IN_BLOCKDIM_X_CHROMA(frame_res->width / 2); /* UV = Y/2, depens on colour format YUV 4.2.0*/
/* Generate Y buffers */
dvs_config->xcoords_y = (uint32_t *)sh_css_malloc(width_y * height_y * sizeof(uint32_t));
- if (dvs_config->xcoords_y == NULL) {
+ if (!dvs_config->xcoords_y) {
IA_CSS_ERROR("out of memory");
err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
goto exit;
}
dvs_config->ycoords_y = (uint32_t *)sh_css_malloc(width_y * height_y * sizeof(uint32_t));
- if (dvs_config->ycoords_y == NULL) {
+ if (!dvs_config->ycoords_y) {
IA_CSS_ERROR("out of memory");
err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
goto exit;
IA_CSS_LOG("UV W %d H %d", width_uv, height_uv);
dvs_config->xcoords_uv = (uint32_t *)sh_css_malloc(width_uv * height_uv * sizeof(uint32_t));
- if (dvs_config->xcoords_uv == NULL) {
+ if (!dvs_config->xcoords_uv) {
IA_CSS_ERROR("out of memory");
err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
goto exit;
}
dvs_config->ycoords_uv = (uint32_t *)sh_css_malloc(width_uv * height_uv * sizeof(uint32_t));
- if (dvs_config->ycoords_uv == NULL) {
+ if (!dvs_config->ycoords_uv) {
IA_CSS_ERROR("out of memory");
err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
}
dvs_offset->width, dvs_offset->height, width_y, height_y);
for (y = 0; y < height_y; y++) {
for (x = 0; x < width_y; x++) {
- dvs_config->xcoords_y[y*width_y + x] = (dvs_offset->width + x*DVS_BLOCKDIM_X) << DVS_COORD_FRAC_BITS;
+ dvs_config->xcoords_y[y * width_y + x] = (dvs_offset->width + x * DVS_BLOCKDIM_X) << DVS_COORD_FRAC_BITS;
}
}
for (y = 0; y < height_y; y++) {
for (x = 0; x < width_y; x++) {
- dvs_config->ycoords_y[y*width_y + x] = (dvs_offset->height + y*DVS_BLOCKDIM_Y_LUMA) << DVS_COORD_FRAC_BITS;
+ dvs_config->ycoords_y[y * width_y + x] = (dvs_offset->height + y * DVS_BLOCKDIM_Y_LUMA) << DVS_COORD_FRAC_BITS;
}
}
for (y = 0; y < height_uv; y++) {
for (x = 0; x < width_uv; x++) { /* Envelope dimensions set in Ypixels hence offset UV = offset Y/2 */
- dvs_config->xcoords_uv[y*width_uv + x] = ((dvs_offset->width / 2) + x*DVS_BLOCKDIM_X) << DVS_COORD_FRAC_BITS;
+ dvs_config->xcoords_uv[y * width_uv + x] = ((dvs_offset->width / 2) + x * DVS_BLOCKDIM_X) << DVS_COORD_FRAC_BITS;
}
}
for (y = 0; y < height_uv; y++) {
for (x = 0; x < width_uv; x++) { /* Envelope dimensions set in Ypixels hence offset UV = offset Y/2 */
- dvs_config->ycoords_uv[y*width_uv + x] = ((dvs_offset->height / 2) + y*DVS_BLOCKDIM_Y_CHROMA) << DVS_COORD_FRAC_BITS;
+ dvs_config->ycoords_uv[y * width_uv + x] = ((dvs_offset->height / 2) + y * DVS_BLOCKDIM_Y_CHROMA) << DVS_COORD_FRAC_BITS;
}
}
-
}
static void
{
struct ia_css_dvs_6axis_config *dvs_6axis_table;
- assert(frame_res != NULL);
- assert(dvs_offset != NULL);
+ assert(frame_res);
+ assert(dvs_offset);
dvs_6axis_table = alloc_dvs_6axis_table(frame_res, NULL);
if (dvs_6axis_table) {
{
struct ia_css_dvs_6axis_config *dvs_6axis_table;
- assert(NULL != dvs_config_src);
+ assert(dvs_config_src);
dvs_6axis_table = alloc_dvs_6axis_table(NULL, dvs_config_src);
if (dvs_6axis_table) {
void
free_dvs_6axis_table(struct ia_css_dvs_6axis_config **dvs_6axis_config)
{
- assert(dvs_6axis_config != NULL);
- assert(*dvs_6axis_config != NULL);
+ assert(dvs_6axis_config);
+ assert(*dvs_6axis_config);
- if ((dvs_6axis_config != NULL) && (*dvs_6axis_config != NULL))
+ if ((dvs_6axis_config) && (*dvs_6axis_config))
{
IA_CSS_ENTER_PRIVATE("dvs_6axis_config %p", (*dvs_6axis_config));
- if ((*dvs_6axis_config)->xcoords_y != NULL)
+ if ((*dvs_6axis_config)->xcoords_y)
{
sh_css_free((*dvs_6axis_config)->xcoords_y);
(*dvs_6axis_config)->xcoords_y = NULL;
}
- if ((*dvs_6axis_config)->ycoords_y != NULL)
+ if ((*dvs_6axis_config)->ycoords_y)
{
sh_css_free((*dvs_6axis_config)->ycoords_y);
(*dvs_6axis_config)->ycoords_y = NULL;
}
/* Free up UV buffers */
- if ((*dvs_6axis_config)->xcoords_uv != NULL)
+ if ((*dvs_6axis_config)->xcoords_uv)
{
sh_css_free((*dvs_6axis_config)->xcoords_uv);
(*dvs_6axis_config)->xcoords_uv = NULL;
}
- if ((*dvs_6axis_config)->ycoords_uv != NULL)
+ if ((*dvs_6axis_config)->ycoords_uv)
{
sh_css_free((*dvs_6axis_config)->ycoords_uv);
(*dvs_6axis_config)->ycoords_uv = NULL;
unsigned int width_uv;
unsigned int height_uv;
- assert(dvs_config_src != NULL);
- assert(dvs_config_dst != NULL);
- assert(dvs_config_src->xcoords_y != NULL);
- assert(dvs_config_src->xcoords_uv != NULL);
- assert(dvs_config_src->ycoords_y != NULL);
- assert(dvs_config_src->ycoords_uv != NULL);
+ assert(dvs_config_src);
+ assert(dvs_config_dst);
+ assert(dvs_config_src->xcoords_y);
+ assert(dvs_config_src->xcoords_uv);
+ assert(dvs_config_src->ycoords_y);
+ assert(dvs_config_src->ycoords_uv);
assert(dvs_config_src->width_y == dvs_config_dst->width_y);
assert(dvs_config_src->width_uv == dvs_config_dst->width_uv);
assert(dvs_config_src->height_y == dvs_config_dst->height_y);
memcpy(dvs_config_dst->xcoords_uv, dvs_config_src->xcoords_uv, (width_uv * height_uv * sizeof(uint32_t)));
memcpy(dvs_config_dst->ycoords_uv, dvs_config_src->ycoords_uv, (width_uv * height_uv * sizeof(uint32_t)));
-
}
void
union ia_css_dvs_statistics_host *host_stats,
const union ia_css_dvs_statistics_isp *isp_stats)
{
-
- if (DVS_STATISTICS == type)
+ if (type == DVS_STATISTICS)
{
ia_css_get_dvs_statistics(host_stats->p_dvs_statistics_host,
isp_stats->p_dvs_statistics_isp);
- } else if (DVS2_STATISTICS == type)
+ } else if (type == DVS2_STATISTICS)
{
ia_css_get_dvs2_statistics(host_stats->p_dvs2_statistics_host,
isp_stats->p_dvs_statistics_isp);
}
return;
}
-
#define DVS_NUM_BLOCKS_X_CHROMA(X) (CEIL_DIV((X), DVS_BLOCKDIM_X))
#define DVS_NUM_BLOCKS_Y_CHROMA(X) (CEIL_DIV((X), DVS_BLOCKDIM_Y_CHROMA))
-
#endif
#define DVS_TABLE_IN_BLOCKDIM_X_LUMA(X) (DVS_NUM_BLOCKS_X(X) + 1) /* N blocks have N + 1 set of coords */
#define DVS_TABLE_IN_BLOCKDIM_X_CHROMA(X) (DVS_NUM_BLOCKS_X_CHROMA(X) + 1)
copy_dvs_6axis_table(struct ia_css_dvs_6axis_config *dvs_config_dst,
const struct ia_css_dvs_6axis_config *dvs_config_src);
-
#endif
unsigned short *in_ptr,
*out_ptr;
- assert(in_table != NULL);
- assert(out_table != NULL);
+ assert(in_table);
+ assert(out_table);
sensor_width = in_table->sensor_width;
sensor_height = in_table->sensor_height;
out_cell_size = CEIL_DIV(padded_width, out_table->width - 1);
in_cell_size = CEIL_DIV(sensor_width, table_width - 1);
- out_start_col = ((int)sensor_width - (int)cropped_width)/2 - left_padding;
- out_start_row = ((int)sensor_height - (int)cropped_height)/2 - top_padding;
- table_cell_w = (int)((table_width-1) * in_cell_size);
- table_cell_h = (table_height-1) * in_cell_size;
+ out_start_col = ((int)sensor_width - (int)cropped_width) / 2 - left_padding;
+ out_start_row = ((int)sensor_height - (int)cropped_height) / 2 - top_padding;
+ table_cell_w = (int)((table_width - 1) * in_cell_size);
+ table_cell_h = (table_height - 1) * in_cell_size;
for (i = 0; i < out_table->height; i++) {
int ty, src_y0, src_y1;
src_y1 = (ty + out_cell_size) / in_cell_size;
else
src_y1 = src_y0 + 1;
- src_y0 = clamp(src_y0, 0, (int)table_height-1);
- src_y1 = clamp(src_y1, 0, (int)table_height-1);
- ty = min(clamp(ty, 0, (int)sensor_height-1),
+ src_y0 = clamp(src_y0, 0, (int)table_height - 1);
+ src_y1 = clamp(src_y1, 0, (int)table_height - 1);
+ ty = min(clamp(ty, 0, (int)sensor_height - 1),
(int)table_cell_h);
/* calculate closest source points for distance computation */
- sy0 = min(src_y0 * in_cell_size, sensor_height-1);
- sy1 = min(src_y1 * in_cell_size, sensor_height-1);
+ sy0 = min(src_y0 * in_cell_size, sensor_height - 1);
+ sy1 = min(src_y1 * in_cell_size, sensor_height - 1);
/* calculate distance between source and target pixels */
dy0 = ty - sy0;
dy1 = sy1 - ty;
src_x1 = src_x0 + 1;
}
/* if src points fall in padding, select closest ones.*/
- src_x0 = clamp(src_x0, 0, (int)table_width-1);
- src_x1 = clamp(src_x1, 0, (int)table_width-1);
- tx = min(clamp(tx, 0, (int)sensor_width-1),
+ src_x0 = clamp(src_x0, 0, (int)table_width - 1);
+ src_x1 = clamp(src_x1, 0, (int)table_width - 1);
+ tx = min(clamp(tx, 0, (int)sensor_width - 1),
(int)table_cell_w);
/* calculate closest source points for distance
computation */
- sx0 = min(src_x0 * in_cell_size, sensor_width-1);
- sx1 = min(src_x1 * in_cell_size, sensor_width-1);
+ sx0 = min(src_x0 * in_cell_size, sensor_width - 1);
+ sx1 = min(src_x1 * in_cell_size, sensor_width - 1);
/* calculate distances between source and target
pixels */
dx0 = tx - sx0;
}
/* get source pixel values */
- s_ul = in_ptr[(table_width*src_y0)+src_x0];
- s_ur = in_ptr[(table_width*src_y0)+src_x1];
- s_ll = in_ptr[(table_width*src_y1)+src_x0];
- s_lr = in_ptr[(table_width*src_y1)+src_x1];
+ s_ul = in_ptr[(table_width * src_y0) + src_x0];
+ s_ur = in_ptr[(table_width * src_y0) + src_x1];
+ s_ll = in_ptr[(table_width * src_y1) + src_x0];
+ s_lr = in_ptr[(table_width * src_y1) + src_x1];
- *out_ptr = (unsigned short) ((dx0*dy0*s_lr + dx0*dy1*s_ur + dx1*dy0*s_ll + dx1*dy1*s_ul) /
- (divx*divy));
+ *out_ptr = (unsigned short)((dx0 * dy0 * s_lr + dx0 * dy1 * s_ur + dx1 * dy0 * s_ll + dx1 * dy1 * s_ul) /
+ (divx * divy));
}
}
}
#endif
struct ia_css_shading_table *result;
- assert(target_table != NULL);
+ assert(target_table);
#ifndef ISP2401
- assert(binary != NULL);
+ assert(binary);
#endif
#ifndef ISP2401
table_height = binary->sctbl_height;
#endif
result = ia_css_shading_table_alloc(table_width, table_height);
- if (result == NULL) {
+ if (!result) {
*target_table = NULL;
return;
}
struct ia_css_shading_table *result;
- assert(target_table != NULL);
- assert(binary != NULL);
+ assert(target_table);
+ assert(binary);
if (!in_table) {
#ifndef ISP2401
shading correction is performed in the bayer domain (before bayer
down scaling). */
#if defined(USE_INPUT_SYSTEM_VERSION_2401)
- padded_width = CEIL_MUL(binary->effective_in_frame_res.width + 2*ISP_VEC_NELEMS,
- 2*ISP_VEC_NELEMS);
+ padded_width = CEIL_MUL(binary->effective_in_frame_res.width + 2 * ISP_VEC_NELEMS,
+ 2 * ISP_VEC_NELEMS);
#endif
input_height = binary->in_frame_info.res.height;
input_width = binary->in_frame_info.res.width;
left_padding = binary->left_padding;
left_cropping = (binary->info->sp.pipeline.left_cropping == 0) ?
- binary->dvs_envelope.width : 2*ISP_VEC_NELEMS;
+ binary->dvs_envelope.width : 2 * ISP_VEC_NELEMS;
sh_css_bds_factor_get_numerator_denominator
(bds_factor, &bds_numerator, &bds_denominator);
#endif
result = ia_css_shading_table_alloc(table_width, table_height);
- if (result == NULL) {
+ if (!result) {
*target_table = NULL;
return;
}
for (i = 0; i < IA_CSS_SC_NUM_COLORS; i++) {
me->data[i] =
sh_css_malloc(width * height * sizeof(*me->data[0]));
- if (me->data[i] == NULL) {
+ if (!me->data[i]) {
unsigned int j;
+
for (j = 0; j < i; j++) {
sh_css_free(me->data[j]);
me->data[j] = NULL;
{
unsigned int i;
- if (table == NULL)
+ if (!table)
return;
/* We only output logging when the table is not NULL, otherwise
IA_CSS_LEAVE("");
}
-
unsigned int bds_factor);
#endif /* __SH_CSS_PARAMS_SHADING_H */
-
};
#else /* defined(CONFIG_CSI2_PLUS) */
static const int zoom_table[4][HRT_GDC_N] = {
- { 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
- -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
- -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
- -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
- -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
- -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
- -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4,
- -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4,
- -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4,
- -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4,
- -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
- -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
- -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
- -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
- -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4,
- -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4,
- -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4,
- -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4,
- -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4,
- -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4,
- -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
- -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
- -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
- -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
- -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4,
- -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4,
- -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4,
- -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4,
- -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4,
- -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4,
- -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
- -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
- -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
- -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
- -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4,
- -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4,
- -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
- -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
- -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
- -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
- -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
- -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
- -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
- -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
- -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
- -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
- -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
- -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
- -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
- -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
- -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
- -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
- -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
- -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
- -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
- -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
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},
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- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4,
- 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4,
- 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4,
- 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4,
- 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4,
- 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4,
- 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4,
- 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4,
- 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4,
- 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4,
- 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4,
- 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4,
- 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4,
- 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4,
- 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4,
- 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4,
- 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4,
- 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4,
- 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4,
- 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4,
- 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4,
- 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4,
- 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4,
- 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4,
- 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4,
- 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4,
- 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4,
- 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4,
- 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4,
- 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4,
- 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4,
- 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4,
- 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4,
- 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4,
- 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4,
- 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4,
- 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4,
- 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4,
- 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4,
- 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4,
- 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4,
- 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4,
- 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4,
- 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4,
- 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4,
- 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4,
- 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4,
- 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4,
- 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4,
- 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4,
- 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4,
- 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4,
- 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4,
- 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4,
- 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4,
- 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4,
- 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4,
- 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4,
- 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4,
- 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4,
- 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4,
- 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4,
- 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4,
- 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4,
- 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4,
- 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4,
- 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4,
- 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4,
- 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4,
- 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4,
- 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4,
- 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4,
- 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4,
- 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4,
- 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4,
- 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4,
- 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4,
- 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4,
- 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4,
- 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4,
- 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4,
- 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4,
- 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4,
- 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4,
- 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4,
- 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4,
- 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4,
- 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4,
- 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4,
- 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4,
- 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4,
- 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4,
- 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4,
- 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4,
- 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4,
- 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4,
- 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4,
- 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4,
- 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4,
- 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4,
- 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4,
- 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4,
- 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4,
- 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4,
- 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4,
- 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4,
- 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4,
- 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4,
- 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4,
- 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4,
- 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4,
- 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4,
- 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4,
- 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4,
- 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4,
- 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4,
- 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4,
- 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4,
- 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4,
- 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4,
- 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4,
- 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4,
- 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4,
- 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4,
- 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4,
- 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4
+ { 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4,
+ 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4,
+ 2 << 4, 2 << 4, 2 << 4, 2 << 4, 2 << 4, 2 << 4, 2 << 4, 2 << 4,
+ 2 << 4, 2 << 4, 2 << 4, 2 << 4, 2 << 4, 2 << 4, 2 << 4, 2 << 4,
+ 4 << 4, 4 << 4, 4 << 4, 4 << 4, 4 << 4, 4 << 4, 4 << 4, 4 << 4,
+ 4 << 4, 4 << 4, 4 << 4, 4 << 4, 4 << 4, 4 << 4, 4 << 4, 4 << 4,
+ 7 << 4, 7 << 4, 7 << 4, 7 << 4, 7 << 4, 7 << 4, 7 << 4, 7 << 4,
+ 7 << 4, 7 << 4, 7 << 4, 7 << 4, 7 << 4, 7 << 4, 7 << 4, 7 << 4,
+ 9 << 4, 9 << 4, 9 << 4, 9 << 4, 9 << 4, 9 << 4, 9 << 4, 9 << 4,
+ 9 << 4, 9 << 4, 9 << 4, 9 << 4, 9 << 4, 9 << 4, 9 << 4, 9 << 4,
+ 12 << 4, 12 << 4, 12 << 4, 12 << 4, 12 << 4, 12 << 4, 12 << 4, 12 << 4,
+ 12 << 4, 12 << 4, 12 << 4, 12 << 4, 12 << 4, 12 << 4, 12 << 4, 12 << 4,
+ 16 << 4, 16 << 4, 16 << 4, 16 << 4, 16 << 4, 16 << 4, 16 << 4, 16 << 4,
+ 16 << 4, 16 << 4, 16 << 4, 16 << 4, 16 << 4, 16 << 4, 16 << 4, 16 << 4,
+ 19 << 4, 19 << 4, 19 << 4, 19 << 4, 19 << 4, 19 << 4, 19 << 4, 19 << 4,
+ 19 << 4, 19 << 4, 19 << 4, 19 << 4, 19 << 4, 19 << 4, 19 << 4, 19 << 4,
+ 23 << 4, 23 << 4, 23 << 4, 23 << 4, 23 << 4, 23 << 4, 23 << 4, 23 << 4,
+ 23 << 4, 23 << 4, 23 << 4, 23 << 4, 23 << 4, 23 << 4, 23 << 4, 23 << 4,
+ 27 << 4, 27 << 4, 27 << 4, 27 << 4, 27 << 4, 27 << 4, 27 << 4, 27 << 4,
+ 27 << 4, 27 << 4, 27 << 4, 27 << 4, 27 << 4, 27 << 4, 27 << 4, 27 << 4,
+ 31 << 4, 31 << 4, 31 << 4, 31 << 4, 31 << 4, 31 << 4, 31 << 4, 31 << 4,
+ 31 << 4, 31 << 4, 31 << 4, 31 << 4, 31 << 4, 31 << 4, 31 << 4, 31 << 4,
+ 35 << 4, 35 << 4, 35 << 4, 35 << 4, 35 << 4, 35 << 4, 35 << 4, 35 << 4,
+ 35 << 4, 35 << 4, 35 << 4, 35 << 4, 35 << 4, 35 << 4, 35 << 4, 35 << 4,
+ 39 << 4, 39 << 4, 39 << 4, 39 << 4, 39 << 4, 39 << 4, 39 << 4, 39 << 4,
+ 39 << 4, 39 << 4, 39 << 4, 39 << 4, 39 << 4, 39 << 4, 39 << 4, 39 << 4,
+ 43 << 4, 43 << 4, 43 << 4, 43 << 4, 43 << 4, 43 << 4, 43 << 4, 43 << 4,
+ 43 << 4, 43 << 4, 43 << 4, 43 << 4, 43 << 4, 43 << 4, 43 << 4, 43 << 4,
+ 48 << 4, 48 << 4, 48 << 4, 48 << 4, 48 << 4, 48 << 4, 48 << 4, 48 << 4,
+ 48 << 4, 48 << 4, 48 << 4, 48 << 4, 48 << 4, 48 << 4, 48 << 4, 48 << 4,
+ 53 << 4, 53 << 4, 53 << 4, 53 << 4, 53 << 4, 53 << 4, 53 << 4, 53 << 4,
+ 53 << 4, 53 << 4, 53 << 4, 53 << 4, 53 << 4, 53 << 4, 53 << 4, 53 << 4,
+ 58 << 4, 58 << 4, 58 << 4, 58 << 4, 58 << 4, 58 << 4, 58 << 4, 58 << 4,
+ 58 << 4, 58 << 4, 58 << 4, 58 << 4, 58 << 4, 58 << 4, 58 << 4, 58 << 4,
+ 62 << 4, 62 << 4, 62 << 4, 62 << 4, 62 << 4, 62 << 4, 62 << 4, 62 << 4,
+ 62 << 4, 62 << 4, 62 << 4, 62 << 4, 62 << 4, 62 << 4, 62 << 4, 62 << 4,
+ 67 << 4, 67 << 4, 67 << 4, 67 << 4, 67 << 4, 67 << 4, 67 << 4, 67 << 4,
+ 67 << 4, 67 << 4, 67 << 4, 67 << 4, 67 << 4, 67 << 4, 67 << 4, 67 << 4,
+ 73 << 4, 73 << 4, 73 << 4, 73 << 4, 73 << 4, 73 << 4, 73 << 4, 73 << 4,
+ 73 << 4, 73 << 4, 73 << 4, 73 << 4, 73 << 4, 73 << 4, 73 << 4, 73 << 4,
+ 78 << 4, 78 << 4, 78 << 4, 78 << 4, 78 << 4, 78 << 4, 78 << 4, 78 << 4,
+ 78 << 4, 78 << 4, 78 << 4, 78 << 4, 78 << 4, 78 << 4, 78 << 4, 78 << 4,
+ 83 << 4, 83 << 4, 83 << 4, 83 << 4, 83 << 4, 83 << 4, 83 << 4, 83 << 4,
+ 83 << 4, 83 << 4, 83 << 4, 83 << 4, 83 << 4, 83 << 4, 83 << 4, 83 << 4,
+ 88 << 4, 88 << 4, 88 << 4, 88 << 4, 88 << 4, 88 << 4, 88 << 4, 88 << 4,
+ 88 << 4, 88 << 4, 88 << 4, 88 << 4, 88 << 4, 88 << 4, 88 << 4, 88 << 4,
+ 94 << 4, 94 << 4, 94 << 4, 94 << 4, 94 << 4, 94 << 4, 94 << 4, 94 << 4,
+ 94 << 4, 94 << 4, 94 << 4, 94 << 4, 94 << 4, 94 << 4, 94 << 4, 94 << 4,
+ 99 << 4, 99 << 4, 99 << 4, 99 << 4, 99 << 4, 99 << 4, 99 << 4, 99 << 4,
+ 99 << 4, 99 << 4, 99 << 4, 99 << 4, 99 << 4, 99 << 4, 99 << 4, 99 << 4,
+ 105 << 4, 105 << 4, 105 << 4, 105 << 4, 105 << 4, 105 << 4, 105 << 4, 105 << 4,
+ 105 << 4, 105 << 4, 105 << 4, 105 << 4, 105 << 4, 105 << 4, 105 << 4, 105 << 4,
+ 110 << 4, 110 << 4, 110 << 4, 110 << 4, 110 << 4, 110 << 4, 110 << 4, 110 << 4,
+ 110 << 4, 110 << 4, 110 << 4, 110 << 4, 110 << 4, 110 << 4, 110 << 4, 110 << 4,
+ 116 << 4, 116 << 4, 116 << 4, 116 << 4, 116 << 4, 116 << 4, 116 << 4, 116 << 4,
+ 116 << 4, 116 << 4, 116 << 4, 116 << 4, 116 << 4, 116 << 4, 116 << 4, 116 << 4,
+ 121 << 4, 121 << 4, 121 << 4, 121 << 4, 121 << 4, 121 << 4, 121 << 4, 121 << 4,
+ 121 << 4, 121 << 4, 121 << 4, 121 << 4, 121 << 4, 121 << 4, 121 << 4, 121 << 4,
+ 127 << 4, 127 << 4, 127 << 4, 127 << 4, 127 << 4, 127 << 4, 127 << 4, 127 << 4,
+ 127 << 4, 127 << 4, 127 << 4, 127 << 4, 127 << 4, 127 << 4, 127 << 4, 127 << 4,
+ 132 << 4, 132 << 4, 132 << 4, 132 << 4, 132 << 4, 132 << 4, 132 << 4, 132 << 4,
+ 132 << 4, 132 << 4, 132 << 4, 132 << 4, 132 << 4, 132 << 4, 132 << 4, 132 << 4,
+ 138 << 4, 138 << 4, 138 << 4, 138 << 4, 138 << 4, 138 << 4, 138 << 4, 138 << 4,
+ 138 << 4, 138 << 4, 138 << 4, 138 << 4, 138 << 4, 138 << 4, 138 << 4, 138 << 4,
+ 144 << 4, 144 << 4, 144 << 4, 144 << 4, 144 << 4, 144 << 4, 144 << 4, 144 << 4,
+ 144 << 4, 144 << 4, 144 << 4, 144 << 4, 144 << 4, 144 << 4, 144 << 4, 144 << 4,
+ 149 << 4, 149 << 4, 149 << 4, 149 << 4, 149 << 4, 149 << 4, 149 << 4, 149 << 4,
+ 149 << 4, 149 << 4, 149 << 4, 149 << 4, 149 << 4, 149 << 4, 149 << 4, 149 << 4,
+ 154 << 4, 154 << 4, 154 << 4, 154 << 4, 154 << 4, 154 << 4, 154 << 4, 154 << 4,
+ 154 << 4, 154 << 4, 154 << 4, 154 << 4, 154 << 4, 154 << 4, 154 << 4, 154 << 4,
+ 160 << 4, 160 << 4, 160 << 4, 160 << 4, 160 << 4, 160 << 4, 160 << 4, 160 << 4,
+ 160 << 4, 160 << 4, 160 << 4, 160 << 4, 160 << 4, 160 << 4, 160 << 4, 160 << 4,
+ 165 << 4, 165 << 4, 165 << 4, 165 << 4, 165 << 4, 165 << 4, 165 << 4, 165 << 4,
+ 165 << 4, 165 << 4, 165 << 4, 165 << 4, 165 << 4, 165 << 4, 165 << 4, 165 << 4,
+ 170 << 4, 170 << 4, 170 << 4, 170 << 4, 170 << 4, 170 << 4, 170 << 4, 170 << 4,
+ 170 << 4, 170 << 4, 170 << 4, 170 << 4, 170 << 4, 170 << 4, 170 << 4, 170 << 4,
+ 176 << 4, 176 << 4, 176 << 4, 176 << 4, 176 << 4, 176 << 4, 176 << 4, 176 << 4,
+ 176 << 4, 176 << 4, 176 << 4, 176 << 4, 176 << 4, 176 << 4, 176 << 4, 176 << 4,
+ 181 << 4, 181 << 4, 181 << 4, 181 << 4, 181 << 4, 181 << 4, 181 << 4, 181 << 4,
+ 181 << 4, 181 << 4, 181 << 4, 181 << 4, 181 << 4, 181 << 4, 181 << 4, 181 << 4,
+ 186 << 4, 186 << 4, 186 << 4, 186 << 4, 186 << 4, 186 << 4, 186 << 4, 186 << 4,
+ 186 << 4, 186 << 4, 186 << 4, 186 << 4, 186 << 4, 186 << 4, 186 << 4, 186 << 4,
+ 191 << 4, 191 << 4, 191 << 4, 191 << 4, 191 << 4, 191 << 4, 191 << 4, 191 << 4,
+ 191 << 4, 191 << 4, 191 << 4, 191 << 4, 191 << 4, 191 << 4, 191 << 4, 191 << 4,
+ 195 << 4, 195 << 4, 195 << 4, 195 << 4, 195 << 4, 195 << 4, 195 << 4, 195 << 4,
+ 195 << 4, 195 << 4, 195 << 4, 195 << 4, 195 << 4, 195 << 4, 195 << 4, 195 << 4,
+ 200 << 4, 200 << 4, 200 << 4, 200 << 4, 200 << 4, 200 << 4, 200 << 4, 200 << 4,
+ 200 << 4, 200 << 4, 200 << 4, 200 << 4, 200 << 4, 200 << 4, 200 << 4, 200 << 4,
+ 205 << 4, 205 << 4, 205 << 4, 205 << 4, 205 << 4, 205 << 4, 205 << 4, 205 << 4,
+ 205 << 4, 205 << 4, 205 << 4, 205 << 4, 205 << 4, 205 << 4, 205 << 4, 205 << 4,
+ 209 << 4, 209 << 4, 209 << 4, 209 << 4, 209 << 4, 209 << 4, 209 << 4, 209 << 4,
+ 209 << 4, 209 << 4, 209 << 4, 209 << 4, 209 << 4, 209 << 4, 209 << 4, 209 << 4,
+ 213 << 4, 213 << 4, 213 << 4, 213 << 4, 213 << 4, 213 << 4, 213 << 4, 213 << 4,
+ 213 << 4, 213 << 4, 213 << 4, 213 << 4, 213 << 4, 213 << 4, 213 << 4, 213 << 4,
+ 218 << 4, 218 << 4, 218 << 4, 218 << 4, 218 << 4, 218 << 4, 218 << 4, 218 << 4,
+ 218 << 4, 218 << 4, 218 << 4, 218 << 4, 218 << 4, 218 << 4, 218 << 4, 218 << 4,
+ 222 << 4, 222 << 4, 222 << 4, 222 << 4, 222 << 4, 222 << 4, 222 << 4, 222 << 4,
+ 222 << 4, 222 << 4, 222 << 4, 222 << 4, 222 << 4, 222 << 4, 222 << 4, 222 << 4,
+ 225 << 4, 225 << 4, 225 << 4, 225 << 4, 225 << 4, 225 << 4, 225 << 4, 225 << 4,
+ 225 << 4, 225 << 4, 225 << 4, 225 << 4, 225 << 4, 225 << 4, 225 << 4, 225 << 4,
+ 229 << 4, 229 << 4, 229 << 4, 229 << 4, 229 << 4, 229 << 4, 229 << 4, 229 << 4,
+ 229 << 4, 229 << 4, 229 << 4, 229 << 4, 229 << 4, 229 << 4, 229 << 4, 229 << 4,
+ 232 << 4, 232 << 4, 232 << 4, 232 << 4, 232 << 4, 232 << 4, 232 << 4, 232 << 4,
+ 232 << 4, 232 << 4, 232 << 4, 232 << 4, 232 << 4, 232 << 4, 232 << 4, 232 << 4,
+ 236 << 4, 236 << 4, 236 << 4, 236 << 4, 236 << 4, 236 << 4, 236 << 4, 236 << 4,
+ 236 << 4, 236 << 4, 236 << 4, 236 << 4, 236 << 4, 236 << 4, 236 << 4, 236 << 4,
+ 239 << 4, 239 << 4, 239 << 4, 239 << 4, 239 << 4, 239 << 4, 239 << 4, 239 << 4,
+ 239 << 4, 239 << 4, 239 << 4, 239 << 4, 239 << 4, 239 << 4, 239 << 4, 239 << 4,
+ 241 << 4, 241 << 4, 241 << 4, 241 << 4, 241 << 4, 241 << 4, 241 << 4, 241 << 4,
+ 241 << 4, 241 << 4, 241 << 4, 241 << 4, 241 << 4, 241 << 4, 241 << 4, 241 << 4,
+ 244 << 4, 244 << 4, 244 << 4, 244 << 4, 244 << 4, 244 << 4, 244 << 4, 244 << 4,
+ 244 << 4, 244 << 4, 244 << 4, 244 << 4, 244 << 4, 244 << 4, 244 << 4, 244 << 4,
+ 246 << 4, 246 << 4, 246 << 4, 246 << 4, 246 << 4, 246 << 4, 246 << 4, 246 << 4,
+ 246 << 4, 246 << 4, 246 << 4, 246 << 4, 246 << 4, 246 << 4, 246 << 4, 246 << 4,
+ 248 << 4, 248 << 4, 248 << 4, 248 << 4, 248 << 4, 248 << 4, 248 << 4, 248 << 4,
+ 248 << 4, 248 << 4, 248 << 4, 248 << 4, 248 << 4, 248 << 4, 248 << 4, 248 << 4,
+ 250 << 4, 250 << 4, 250 << 4, 250 << 4, 250 << 4, 250 << 4, 250 << 4, 250 << 4,
+ 250 << 4, 250 << 4, 250 << 4, 250 << 4, 250 << 4, 250 << 4, 250 << 4, 250 << 4,
+ 252 << 4, 252 << 4, 252 << 4, 252 << 4, 252 << 4, 252 << 4, 252 << 4, 252 << 4,
+ 252 << 4, 252 << 4, 252 << 4, 252 << 4, 252 << 4, 252 << 4, 252 << 4, 252 << 4,
+ 253 << 4, 253 << 4, 253 << 4, 253 << 4, 253 << 4, 253 << 4, 253 << 4, 253 << 4,
+ 253 << 4, 253 << 4, 253 << 4, 253 << 4, 253 << 4, 253 << 4, 253 << 4, 253 << 4,
+ 254 << 4, 254 << 4, 254 << 4, 254 << 4, 254 << 4, 254 << 4, 254 << 4, 254 << 4,
+ 254 << 4, 254 << 4, 254 << 4, 254 << 4, 254 << 4, 254 << 4, 254 << 4, 254 << 4,
+ 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4,
+ 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4,
+ 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4,
+ 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4
},
- { 256<<4, 256<<4, 256<<4, 256<<4, 256<<4, 256<<4, 256<<4, 256<<4,
- 256<<4, 256<<4, 256<<4, 256<<4, 256<<4, 256<<4, 256<<4, 256<<4,
- 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4,
- 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4,
- 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4,
- 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4, 255<<4,
- 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4,
- 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4, 254<<4,
- 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4,
- 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4, 253<<4,
- 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4,
- 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4, 252<<4,
- 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4,
- 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4, 250<<4,
- 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4,
- 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4, 248<<4,
- 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4,
- 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4, 246<<4,
- 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4,
- 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4, 244<<4,
- 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4,
- 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4, 241<<4,
- 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4,
- 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4, 239<<4,
- 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4,
- 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4, 236<<4,
- 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4,
- 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4, 232<<4,
- 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4,
- 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4, 229<<4,
- 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4,
- 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4, 225<<4,
- 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4,
- 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4, 222<<4,
- 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4,
- 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4, 218<<4,
- 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4,
- 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4, 213<<4,
- 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4,
- 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4, 209<<4,
- 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4,
- 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4, 205<<4,
- 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4,
- 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4, 200<<4,
- 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4,
- 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4, 195<<4,
- 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4,
- 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4, 191<<4,
- 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4,
- 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4, 186<<4,
- 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4,
- 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4, 181<<4,
- 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4,
- 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4, 176<<4,
- 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4,
- 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4, 170<<4,
- 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4,
- 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4, 165<<4,
- 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4,
- 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4, 160<<4,
- 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4,
- 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4, 154<<4,
- 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4,
- 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4, 149<<4,
- 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4,
- 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4, 144<<4,
- 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4,
- 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4, 138<<4,
- 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4,
- 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4, 132<<4,
- 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4,
- 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4, 127<<4,
- 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4,
- 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4, 121<<4,
- 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4,
- 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4, 116<<4,
- 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4,
- 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4, 110<<4,
- 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4,
- 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4, 105<<4,
- 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4,
- 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4, 99<<4,
- 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4,
- 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4, 94<<4,
- 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4,
- 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4, 88<<4,
- 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4,
- 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4, 83<<4,
- 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4,
- 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4, 78<<4,
- 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4,
- 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4, 73<<4,
- 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4,
- 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4, 67<<4,
- 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4,
- 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4, 62<<4,
- 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4,
- 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4, 58<<4,
- 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4,
- 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4, 53<<4,
- 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4,
- 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4, 48<<4,
- 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4,
- 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4, 43<<4,
- 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4,
- 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4, 39<<4,
- 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4,
- 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4, 35<<4,
- 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4,
- 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4, 31<<4,
- 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4,
- 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4, 27<<4,
- 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4,
- 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4, 23<<4,
- 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4,
- 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4, 19<<4,
- 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4,
- 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4, 16<<4,
- 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4,
- 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4, 12<<4,
- 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4,
- 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4, 9<<4,
- 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4,
- 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4, 7<<4,
- 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4,
- 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4, 4<<4,
- 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4,
- 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4, 2<<4
+ { 256 << 4, 256 << 4, 256 << 4, 256 << 4, 256 << 4, 256 << 4, 256 << 4, 256 << 4,
+ 256 << 4, 256 << 4, 256 << 4, 256 << 4, 256 << 4, 256 << 4, 256 << 4, 256 << 4,
+ 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4,
+ 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4,
+ 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4,
+ 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4, 255 << 4,
+ 254 << 4, 254 << 4, 254 << 4, 254 << 4, 254 << 4, 254 << 4, 254 << 4, 254 << 4,
+ 254 << 4, 254 << 4, 254 << 4, 254 << 4, 254 << 4, 254 << 4, 254 << 4, 254 << 4,
+ 253 << 4, 253 << 4, 253 << 4, 253 << 4, 253 << 4, 253 << 4, 253 << 4, 253 << 4,
+ 253 << 4, 253 << 4, 253 << 4, 253 << 4, 253 << 4, 253 << 4, 253 << 4, 253 << 4,
+ 252 << 4, 252 << 4, 252 << 4, 252 << 4, 252 << 4, 252 << 4, 252 << 4, 252 << 4,
+ 252 << 4, 252 << 4, 252 << 4, 252 << 4, 252 << 4, 252 << 4, 252 << 4, 252 << 4,
+ 250 << 4, 250 << 4, 250 << 4, 250 << 4, 250 << 4, 250 << 4, 250 << 4, 250 << 4,
+ 250 << 4, 250 << 4, 250 << 4, 250 << 4, 250 << 4, 250 << 4, 250 << 4, 250 << 4,
+ 248 << 4, 248 << 4, 248 << 4, 248 << 4, 248 << 4, 248 << 4, 248 << 4, 248 << 4,
+ 248 << 4, 248 << 4, 248 << 4, 248 << 4, 248 << 4, 248 << 4, 248 << 4, 248 << 4,
+ 246 << 4, 246 << 4, 246 << 4, 246 << 4, 246 << 4, 246 << 4, 246 << 4, 246 << 4,
+ 246 << 4, 246 << 4, 246 << 4, 246 << 4, 246 << 4, 246 << 4, 246 << 4, 246 << 4,
+ 244 << 4, 244 << 4, 244 << 4, 244 << 4, 244 << 4, 244 << 4, 244 << 4, 244 << 4,
+ 244 << 4, 244 << 4, 244 << 4, 244 << 4, 244 << 4, 244 << 4, 244 << 4, 244 << 4,
+ 241 << 4, 241 << 4, 241 << 4, 241 << 4, 241 << 4, 241 << 4, 241 << 4, 241 << 4,
+ 241 << 4, 241 << 4, 241 << 4, 241 << 4, 241 << 4, 241 << 4, 241 << 4, 241 << 4,
+ 239 << 4, 239 << 4, 239 << 4, 239 << 4, 239 << 4, 239 << 4, 239 << 4, 239 << 4,
+ 239 << 4, 239 << 4, 239 << 4, 239 << 4, 239 << 4, 239 << 4, 239 << 4, 239 << 4,
+ 236 << 4, 236 << 4, 236 << 4, 236 << 4, 236 << 4, 236 << 4, 236 << 4, 236 << 4,
+ 236 << 4, 236 << 4, 236 << 4, 236 << 4, 236 << 4, 236 << 4, 236 << 4, 236 << 4,
+ 232 << 4, 232 << 4, 232 << 4, 232 << 4, 232 << 4, 232 << 4, 232 << 4, 232 << 4,
+ 232 << 4, 232 << 4, 232 << 4, 232 << 4, 232 << 4, 232 << 4, 232 << 4, 232 << 4,
+ 229 << 4, 229 << 4, 229 << 4, 229 << 4, 229 << 4, 229 << 4, 229 << 4, 229 << 4,
+ 229 << 4, 229 << 4, 229 << 4, 229 << 4, 229 << 4, 229 << 4, 229 << 4, 229 << 4,
+ 225 << 4, 225 << 4, 225 << 4, 225 << 4, 225 << 4, 225 << 4, 225 << 4, 225 << 4,
+ 225 << 4, 225 << 4, 225 << 4, 225 << 4, 225 << 4, 225 << 4, 225 << 4, 225 << 4,
+ 222 << 4, 222 << 4, 222 << 4, 222 << 4, 222 << 4, 222 << 4, 222 << 4, 222 << 4,
+ 222 << 4, 222 << 4, 222 << 4, 222 << 4, 222 << 4, 222 << 4, 222 << 4, 222 << 4,
+ 218 << 4, 218 << 4, 218 << 4, 218 << 4, 218 << 4, 218 << 4, 218 << 4, 218 << 4,
+ 218 << 4, 218 << 4, 218 << 4, 218 << 4, 218 << 4, 218 << 4, 218 << 4, 218 << 4,
+ 213 << 4, 213 << 4, 213 << 4, 213 << 4, 213 << 4, 213 << 4, 213 << 4, 213 << 4,
+ 213 << 4, 213 << 4, 213 << 4, 213 << 4, 213 << 4, 213 << 4, 213 << 4, 213 << 4,
+ 209 << 4, 209 << 4, 209 << 4, 209 << 4, 209 << 4, 209 << 4, 209 << 4, 209 << 4,
+ 209 << 4, 209 << 4, 209 << 4, 209 << 4, 209 << 4, 209 << 4, 209 << 4, 209 << 4,
+ 205 << 4, 205 << 4, 205 << 4, 205 << 4, 205 << 4, 205 << 4, 205 << 4, 205 << 4,
+ 205 << 4, 205 << 4, 205 << 4, 205 << 4, 205 << 4, 205 << 4, 205 << 4, 205 << 4,
+ 200 << 4, 200 << 4, 200 << 4, 200 << 4, 200 << 4, 200 << 4, 200 << 4, 200 << 4,
+ 200 << 4, 200 << 4, 200 << 4, 200 << 4, 200 << 4, 200 << 4, 200 << 4, 200 << 4,
+ 195 << 4, 195 << 4, 195 << 4, 195 << 4, 195 << 4, 195 << 4, 195 << 4, 195 << 4,
+ 195 << 4, 195 << 4, 195 << 4, 195 << 4, 195 << 4, 195 << 4, 195 << 4, 195 << 4,
+ 191 << 4, 191 << 4, 191 << 4, 191 << 4, 191 << 4, 191 << 4, 191 << 4, 191 << 4,
+ 191 << 4, 191 << 4, 191 << 4, 191 << 4, 191 << 4, 191 << 4, 191 << 4, 191 << 4,
+ 186 << 4, 186 << 4, 186 << 4, 186 << 4, 186 << 4, 186 << 4, 186 << 4, 186 << 4,
+ 186 << 4, 186 << 4, 186 << 4, 186 << 4, 186 << 4, 186 << 4, 186 << 4, 186 << 4,
+ 181 << 4, 181 << 4, 181 << 4, 181 << 4, 181 << 4, 181 << 4, 181 << 4, 181 << 4,
+ 181 << 4, 181 << 4, 181 << 4, 181 << 4, 181 << 4, 181 << 4, 181 << 4, 181 << 4,
+ 176 << 4, 176 << 4, 176 << 4, 176 << 4, 176 << 4, 176 << 4, 176 << 4, 176 << 4,
+ 176 << 4, 176 << 4, 176 << 4, 176 << 4, 176 << 4, 176 << 4, 176 << 4, 176 << 4,
+ 170 << 4, 170 << 4, 170 << 4, 170 << 4, 170 << 4, 170 << 4, 170 << 4, 170 << 4,
+ 170 << 4, 170 << 4, 170 << 4, 170 << 4, 170 << 4, 170 << 4, 170 << 4, 170 << 4,
+ 165 << 4, 165 << 4, 165 << 4, 165 << 4, 165 << 4, 165 << 4, 165 << 4, 165 << 4,
+ 165 << 4, 165 << 4, 165 << 4, 165 << 4, 165 << 4, 165 << 4, 165 << 4, 165 << 4,
+ 160 << 4, 160 << 4, 160 << 4, 160 << 4, 160 << 4, 160 << 4, 160 << 4, 160 << 4,
+ 160 << 4, 160 << 4, 160 << 4, 160 << 4, 160 << 4, 160 << 4, 160 << 4, 160 << 4,
+ 154 << 4, 154 << 4, 154 << 4, 154 << 4, 154 << 4, 154 << 4, 154 << 4, 154 << 4,
+ 154 << 4, 154 << 4, 154 << 4, 154 << 4, 154 << 4, 154 << 4, 154 << 4, 154 << 4,
+ 149 << 4, 149 << 4, 149 << 4, 149 << 4, 149 << 4, 149 << 4, 149 << 4, 149 << 4,
+ 149 << 4, 149 << 4, 149 << 4, 149 << 4, 149 << 4, 149 << 4, 149 << 4, 149 << 4,
+ 144 << 4, 144 << 4, 144 << 4, 144 << 4, 144 << 4, 144 << 4, 144 << 4, 144 << 4,
+ 144 << 4, 144 << 4, 144 << 4, 144 << 4, 144 << 4, 144 << 4, 144 << 4, 144 << 4,
+ 138 << 4, 138 << 4, 138 << 4, 138 << 4, 138 << 4, 138 << 4, 138 << 4, 138 << 4,
+ 138 << 4, 138 << 4, 138 << 4, 138 << 4, 138 << 4, 138 << 4, 138 << 4, 138 << 4,
+ 132 << 4, 132 << 4, 132 << 4, 132 << 4, 132 << 4, 132 << 4, 132 << 4, 132 << 4,
+ 132 << 4, 132 << 4, 132 << 4, 132 << 4, 132 << 4, 132 << 4, 132 << 4, 132 << 4,
+ 127 << 4, 127 << 4, 127 << 4, 127 << 4, 127 << 4, 127 << 4, 127 << 4, 127 << 4,
+ 127 << 4, 127 << 4, 127 << 4, 127 << 4, 127 << 4, 127 << 4, 127 << 4, 127 << 4,
+ 121 << 4, 121 << 4, 121 << 4, 121 << 4, 121 << 4, 121 << 4, 121 << 4, 121 << 4,
+ 121 << 4, 121 << 4, 121 << 4, 121 << 4, 121 << 4, 121 << 4, 121 << 4, 121 << 4,
+ 116 << 4, 116 << 4, 116 << 4, 116 << 4, 116 << 4, 116 << 4, 116 << 4, 116 << 4,
+ 116 << 4, 116 << 4, 116 << 4, 116 << 4, 116 << 4, 116 << 4, 116 << 4, 116 << 4,
+ 110 << 4, 110 << 4, 110 << 4, 110 << 4, 110 << 4, 110 << 4, 110 << 4, 110 << 4,
+ 110 << 4, 110 << 4, 110 << 4, 110 << 4, 110 << 4, 110 << 4, 110 << 4, 110 << 4,
+ 105 << 4, 105 << 4, 105 << 4, 105 << 4, 105 << 4, 105 << 4, 105 << 4, 105 << 4,
+ 105 << 4, 105 << 4, 105 << 4, 105 << 4, 105 << 4, 105 << 4, 105 << 4, 105 << 4,
+ 99 << 4, 99 << 4, 99 << 4, 99 << 4, 99 << 4, 99 << 4, 99 << 4, 99 << 4,
+ 99 << 4, 99 << 4, 99 << 4, 99 << 4, 99 << 4, 99 << 4, 99 << 4, 99 << 4,
+ 94 << 4, 94 << 4, 94 << 4, 94 << 4, 94 << 4, 94 << 4, 94 << 4, 94 << 4,
+ 94 << 4, 94 << 4, 94 << 4, 94 << 4, 94 << 4, 94 << 4, 94 << 4, 94 << 4,
+ 88 << 4, 88 << 4, 88 << 4, 88 << 4, 88 << 4, 88 << 4, 88 << 4, 88 << 4,
+ 88 << 4, 88 << 4, 88 << 4, 88 << 4, 88 << 4, 88 << 4, 88 << 4, 88 << 4,
+ 83 << 4, 83 << 4, 83 << 4, 83 << 4, 83 << 4, 83 << 4, 83 << 4, 83 << 4,
+ 83 << 4, 83 << 4, 83 << 4, 83 << 4, 83 << 4, 83 << 4, 83 << 4, 83 << 4,
+ 78 << 4, 78 << 4, 78 << 4, 78 << 4, 78 << 4, 78 << 4, 78 << 4, 78 << 4,
+ 78 << 4, 78 << 4, 78 << 4, 78 << 4, 78 << 4, 78 << 4, 78 << 4, 78 << 4,
+ 73 << 4, 73 << 4, 73 << 4, 73 << 4, 73 << 4, 73 << 4, 73 << 4, 73 << 4,
+ 73 << 4, 73 << 4, 73 << 4, 73 << 4, 73 << 4, 73 << 4, 73 << 4, 73 << 4,
+ 67 << 4, 67 << 4, 67 << 4, 67 << 4, 67 << 4, 67 << 4, 67 << 4, 67 << 4,
+ 67 << 4, 67 << 4, 67 << 4, 67 << 4, 67 << 4, 67 << 4, 67 << 4, 67 << 4,
+ 62 << 4, 62 << 4, 62 << 4, 62 << 4, 62 << 4, 62 << 4, 62 << 4, 62 << 4,
+ 62 << 4, 62 << 4, 62 << 4, 62 << 4, 62 << 4, 62 << 4, 62 << 4, 62 << 4,
+ 58 << 4, 58 << 4, 58 << 4, 58 << 4, 58 << 4, 58 << 4, 58 << 4, 58 << 4,
+ 58 << 4, 58 << 4, 58 << 4, 58 << 4, 58 << 4, 58 << 4, 58 << 4, 58 << 4,
+ 53 << 4, 53 << 4, 53 << 4, 53 << 4, 53 << 4, 53 << 4, 53 << 4, 53 << 4,
+ 53 << 4, 53 << 4, 53 << 4, 53 << 4, 53 << 4, 53 << 4, 53 << 4, 53 << 4,
+ 48 << 4, 48 << 4, 48 << 4, 48 << 4, 48 << 4, 48 << 4, 48 << 4, 48 << 4,
+ 48 << 4, 48 << 4, 48 << 4, 48 << 4, 48 << 4, 48 << 4, 48 << 4, 48 << 4,
+ 43 << 4, 43 << 4, 43 << 4, 43 << 4, 43 << 4, 43 << 4, 43 << 4, 43 << 4,
+ 43 << 4, 43 << 4, 43 << 4, 43 << 4, 43 << 4, 43 << 4, 43 << 4, 43 << 4,
+ 39 << 4, 39 << 4, 39 << 4, 39 << 4, 39 << 4, 39 << 4, 39 << 4, 39 << 4,
+ 39 << 4, 39 << 4, 39 << 4, 39 << 4, 39 << 4, 39 << 4, 39 << 4, 39 << 4,
+ 35 << 4, 35 << 4, 35 << 4, 35 << 4, 35 << 4, 35 << 4, 35 << 4, 35 << 4,
+ 35 << 4, 35 << 4, 35 << 4, 35 << 4, 35 << 4, 35 << 4, 35 << 4, 35 << 4,
+ 31 << 4, 31 << 4, 31 << 4, 31 << 4, 31 << 4, 31 << 4, 31 << 4, 31 << 4,
+ 31 << 4, 31 << 4, 31 << 4, 31 << 4, 31 << 4, 31 << 4, 31 << 4, 31 << 4,
+ 27 << 4, 27 << 4, 27 << 4, 27 << 4, 27 << 4, 27 << 4, 27 << 4, 27 << 4,
+ 27 << 4, 27 << 4, 27 << 4, 27 << 4, 27 << 4, 27 << 4, 27 << 4, 27 << 4,
+ 23 << 4, 23 << 4, 23 << 4, 23 << 4, 23 << 4, 23 << 4, 23 << 4, 23 << 4,
+ 23 << 4, 23 << 4, 23 << 4, 23 << 4, 23 << 4, 23 << 4, 23 << 4, 23 << 4,
+ 19 << 4, 19 << 4, 19 << 4, 19 << 4, 19 << 4, 19 << 4, 19 << 4, 19 << 4,
+ 19 << 4, 19 << 4, 19 << 4, 19 << 4, 19 << 4, 19 << 4, 19 << 4, 19 << 4,
+ 16 << 4, 16 << 4, 16 << 4, 16 << 4, 16 << 4, 16 << 4, 16 << 4, 16 << 4,
+ 16 << 4, 16 << 4, 16 << 4, 16 << 4, 16 << 4, 16 << 4, 16 << 4, 16 << 4,
+ 12 << 4, 12 << 4, 12 << 4, 12 << 4, 12 << 4, 12 << 4, 12 << 4, 12 << 4,
+ 12 << 4, 12 << 4, 12 << 4, 12 << 4, 12 << 4, 12 << 4, 12 << 4, 12 << 4,
+ 9 << 4, 9 << 4, 9 << 4, 9 << 4, 9 << 4, 9 << 4, 9 << 4, 9 << 4,
+ 9 << 4, 9 << 4, 9 << 4, 9 << 4, 9 << 4, 9 << 4, 9 << 4, 9 << 4,
+ 7 << 4, 7 << 4, 7 << 4, 7 << 4, 7 << 4, 7 << 4, 7 << 4, 7 << 4,
+ 7 << 4, 7 << 4, 7 << 4, 7 << 4, 7 << 4, 7 << 4, 7 << 4, 7 << 4,
+ 4 << 4, 4 << 4, 4 << 4, 4 << 4, 4 << 4, 4 << 4, 4 << 4, 4 << 4,
+ 4 << 4, 4 << 4, 4 << 4, 4 << 4, 4 << 4, 4 << 4, 4 << 4, 4 << 4,
+ 2 << 4, 2 << 4, 2 << 4, 2 << 4, 2 << 4, 2 << 4, 2 << 4, 2 << 4,
+ 2 << 4, 2 << 4, 2 << 4, 2 << 4, 2 << 4, 2 << 4, 2 << 4, 2 << 4
},
- { 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
- -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
- -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
- -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
- -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4,
- -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4,
- -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
- -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
- -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4,
- -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4,
- -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
- -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
- -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4,
- -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4,
- -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
- -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
- -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
- -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
- -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
- -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
- -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
- -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
- -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
- -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
- -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
- -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
- -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
- -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
- -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
- -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
- -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
- -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
- -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
- -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
- -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
- -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
- -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4,
- -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4,
- -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4,
- -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4,
- -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
- -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
- -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
- -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
- -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4,
- -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4,
- -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
- -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
- -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4,
- -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4, -19<<4,
- -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
- -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4,
- -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
- -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
- -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
- -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
- -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
- -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4,
- -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
- -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
- -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
- -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
- -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
- -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4,
- -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
- -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4,
- -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
- -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
- -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
- -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4,
- -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
- -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4,
- -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
- -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
- -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
- -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
- -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
- -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4,
- -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
- -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
- -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
- -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4,
- -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
- -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
- -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
- -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
- -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
- -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4,
- -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4,
- -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4,
- -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
- -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
- -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
- -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
- -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
- -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4,
- -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4,
- -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4,
- -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4,
- -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4,
- -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
- -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
- -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4,
- -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4,
- -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
- -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4,
- -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4,
- -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4,
- -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4,
- -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4,
- -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
- -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
- -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 1<<4, 1<<4, 1<<4, 1<<4, 1<<4, 1<<4, 1<<4, 1<<4,
- 1<<4, 1<<4, 1<<4, 1<<4, 1<<4, 1<<4, 1<<4, 1<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4,
- 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4
+ { 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4,
+ 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4,
+ -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4,
+ -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4,
+ -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4,
+ -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4,
+ -5 << 4, -5 << 4, -5 << 4, -5 << 4, -5 << 4, -5 << 4, -5 << 4, -5 << 4,
+ -5 << 4, -5 << 4, -5 << 4, -5 << 4, -5 << 4, -5 << 4, -5 << 4, -5 << 4,
+ -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4,
+ -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4,
+ -8 << 4, -8 << 4, -8 << 4, -8 << 4, -8 << 4, -8 << 4, -8 << 4, -8 << 4,
+ -8 << 4, -8 << 4, -8 << 4, -8 << 4, -8 << 4, -8 << 4, -8 << 4, -8 << 4,
+ -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4,
+ -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4,
+ -10 << 4, -10 << 4, -10 << 4, -10 << 4, -10 << 4, -10 << 4, -10 << 4, -10 << 4,
+ -10 << 4, -10 << 4, -10 << 4, -10 << 4, -10 << 4, -10 << 4, -10 << 4, -10 << 4,
+ -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4,
+ -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4,
+ -13 << 4, -13 << 4, -13 << 4, -13 << 4, -13 << 4, -13 << 4, -13 << 4, -13 << 4,
+ -13 << 4, -13 << 4, -13 << 4, -13 << 4, -13 << 4, -13 << 4, -13 << 4, -13 << 4,
+ -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4,
+ -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4,
+ -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4,
+ -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4,
+ -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4,
+ -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4,
+ -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4,
+ -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4,
+ -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4,
+ -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4,
+ -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4,
+ -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4,
+ -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4,
+ -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4,
+ -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4,
+ -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4,
+ -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4,
+ -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4,
+ -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4,
+ -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4,
+ -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4,
+ -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4,
+ -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4,
+ -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4,
+ -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4,
+ -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4,
+ -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4,
+ -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4,
+ -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4,
+ -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4,
+ -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4,
+ -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4, -19 << 4,
+ -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4,
+ -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4, -18 << 4,
+ -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4,
+ -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4,
+ -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4,
+ -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4,
+ -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4,
+ -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4, -17 << 4,
+ -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4,
+ -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4,
+ -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4,
+ -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4,
+ -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4,
+ -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4, -16 << 4,
+ -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4,
+ -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4, -15 << 4,
+ -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4,
+ -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4,
+ -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4,
+ -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4, -14 << 4,
+ -13 << 4, -13 << 4, -13 << 4, -13 << 4, -13 << 4, -13 << 4, -13 << 4, -13 << 4,
+ -13 << 4, -13 << 4, -13 << 4, -13 << 4, -13 << 4, -13 << 4, -13 << 4, -13 << 4,
+ -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4,
+ -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4,
+ -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4,
+ -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4,
+ -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4,
+ -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4, -12 << 4,
+ -11 << 4, -11 << 4, -11 << 4, -11 << 4, -11 << 4, -11 << 4, -11 << 4, -11 << 4,
+ -11 << 4, -11 << 4, -11 << 4, -11 << 4, -11 << 4, -11 << 4, -11 << 4, -11 << 4,
+ -11 << 4, -11 << 4, -11 << 4, -11 << 4, -11 << 4, -11 << 4, -11 << 4, -11 << 4,
+ -11 << 4, -11 << 4, -11 << 4, -11 << 4, -11 << 4, -11 << 4, -11 << 4, -11 << 4,
+ -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4,
+ -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4,
+ -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4,
+ -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4,
+ -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4,
+ -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4, -9 << 4,
+ -8 << 4, -8 << 4, -8 << 4, -8 << 4, -8 << 4, -8 << 4, -8 << 4, -8 << 4,
+ -8 << 4, -8 << 4, -8 << 4, -8 << 4, -8 << 4, -8 << 4, -8 << 4, -8 << 4,
+ -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4,
+ -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4,
+ -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4,
+ -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4,
+ -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4,
+ -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4, -6 << 4,
+ -5 << 4, -5 << 4, -5 << 4, -5 << 4, -5 << 4, -5 << 4, -5 << 4, -5 << 4,
+ -5 << 4, -5 << 4, -5 << 4, -5 << 4, -5 << 4, -5 << 4, -5 << 4, -5 << 4,
+ -4 << 4, -4 << 4, -4 << 4, -4 << 4, -4 << 4, -4 << 4, -4 << 4, -4 << 4,
+ -4 << 4, -4 << 4, -4 << 4, -4 << 4, -4 << 4, -4 << 4, -4 << 4, -4 << 4,
+ -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4,
+ -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4,
+ -4 << 4, -4 << 4, -4 << 4, -4 << 4, -4 << 4, -4 << 4, -4 << 4, -4 << 4,
+ -4 << 4, -4 << 4, -4 << 4, -4 << 4, -4 << 4, -4 << 4, -4 << 4, -4 << 4,
+ -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4,
+ -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4,
+ -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4,
+ -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4,
+ -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4,
+ -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4,
+ -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4,
+ -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4,
+ 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4,
+ 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4,
+ -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4,
+ -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4,
+ 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4,
+ 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4,
+ 1 << 4, 1 << 4, 1 << 4, 1 << 4, 1 << 4, 1 << 4, 1 << 4, 1 << 4,
+ 1 << 4, 1 << 4, 1 << 4, 1 << 4, 1 << 4, 1 << 4, 1 << 4, 1 << 4,
+ 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4,
+ 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4,
+ 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4,
+ 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4,
+ 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4,
+ 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4
}
};
#endif
1 /* enable shading table conversion in the css
(This matches the legacy way.) */
};
+
/* ------ deprecated(bz675) : to ------ */
struct ia_css_isp_skc_dvs_statistics {
static enum ia_css_err
sh_css_params_write_to_ddr_internal(
struct ia_css_pipe *pipe,
- unsigned pipe_id,
+ unsigned int pipe_id,
struct ia_css_isp_parameters *params,
const struct ia_css_pipeline_stage *stage,
struct sh_css_ddr_address_map *ddr_map,
short *data_ptr;
struct ia_css_host_data *me;
unsigned int isp_format_data_size;
- uint32_t *isp_format_data_ptr;
+ u32 *isp_format_data_ptr;
- assert(params != NULL);
+ assert(params);
data_ptr = params->fpn_config.data;
isp_format_data_size = params->fpn_config.height * params->fpn_config.width * sizeof(uint32_t);
{
struct ia_css_host_data *isp_data;
- assert(params != NULL);
+ assert(params);
assert(ptr != mmgr_NULL);
isp_data = convert_allocate_fpntbl(params);
int maxval = 0;
unsigned int i;
- assert(params != NULL);
+ assert(params);
/* Find the maximum value in the table */
for (i = 0; i < params->fpn_config.height * params->fpn_config.width; i++) {
}
/* Adjust the values in the table for the shift value */
for (i = 0; i < params->fpn_config.height * params->fpn_config.width; i++)
- ((unsigned short *) params->fpn_config.data)[i] >>= params->fpn_config.shift;
+ ((unsigned short *)params->fpn_config.data)[i] >>= params->fpn_config.shift;
}
static void
ia_css_process_kernel(struct ia_css_stream *stream,
struct ia_css_isp_parameters *params,
- void (*process)(unsigned pipe_id,
+ void (*process)(unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params))
{
int i;
+
for (i = 0; i < stream->num_pipes; i++) {
struct ia_css_pipe *pipe = stream->pipes[i];
struct ia_css_pipeline *pipeline = ia_css_pipe_get_pipeline(pipe);
static enum ia_css_err
sh_css_select_dp_10bpp_config(const struct ia_css_pipe *pipe, bool *is_dp_10bpp) {
-
enum ia_css_err err = IA_CSS_SUCCESS;
/* Currently we check if 10bpp DPC configuration is required based
* on the use case,i.e. if BDS and DPC is both enabled. The more cleaner
* implementation. (This is because the configuration is set before a
* binary is selected, and the binary info is not available)
*/
- if((pipe == NULL) || (is_dp_10bpp == NULL)) {
+ if ((!pipe) || (!is_dp_10bpp)) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INTERNAL_ERROR);
err = IA_CSS_ERR_INTERNAL_ERROR;
} else {
if (pipe->config.enable_dpc) {
/*check if BDS is enabled*/
unsigned int required_bds_factor = SH_CSS_BDS_FACTOR_1_00;
+
if ((pipe->config.bayer_ds_out_res.width != 0) &&
(pipe->config.bayer_ds_out_res.height != 0)) {
if (IA_CSS_SUCCESS == binarydesc_calculate_bds_factor(
pipe->config.input_effective_res,
pipe->config.bayer_ds_out_res,
&required_bds_factor)) {
- if (SH_CSS_BDS_FACTOR_1_00 != required_bds_factor) {
+ if (required_bds_factor != SH_CSS_BDS_FACTOR_1_00) {
/*we use 10bpp BDS configuration*/
*is_dp_10bpp = true;
}
unsigned int height, width, y, x, k, data;
hrt_vaddress ptr;
- assert(stream != NULL);
- assert(raw_black_frame != NULL);
+ assert(stream);
+ assert(raw_black_frame);
params = stream->isp_params_configs;
height = raw_black_frame->info.res.height;
sh_css_free(params->fpn_config.data);
params->fpn_config.data = NULL;
}
- if (params->fpn_config.data == NULL) {
+ if (!params->fpn_config.data) {
params->fpn_config.data = sh_css_malloc(height * width * sizeof(short));
if (!params->fpn_config.data) {
IA_CSS_ERROR("out of memory");
for (y = 0; y < height; y++) {
for (x = 0; x < width; x += (ISP_VEC_NELEMS * 2)) {
int ofs = y * width + x;
+
for (k = 0; k < ISP_VEC_NELEMS; k += 2) {
mmgr_load(ptr, (void *)(&data), sizeof(int));
params->fpn_config.data[ofs + 2 * k] =
- (short) (data & 0xFFFF);
+ (short)(data & 0xFFFF);
params->fpn_config.data[ofs + 2 * k + 2] =
- (short) ((data >> 16) & 0xFFFF);
+ (short)((data >> 16) & 0xFFFF);
ptr += sizeof(int); /* byte system address */
}
for (k = 0; k < ISP_VEC_NELEMS; k += 2) {
mmgr_load(ptr, (void *)(&data), sizeof(int));
params->fpn_config.data[ofs + 2 * k + 1] =
- (short) (data & 0xFFFF);
+ (short)(data & 0xFFFF);
params->fpn_config.data[ofs + 2 * k + 3] =
- (short) ((data >> 16) & 0xFFFF);
+ (short)((data >> 16) & 0xFFFF);
ptr += sizeof(int); /* byte system address */
}
}
struct ia_css_isp_parameters *params;
IA_CSS_ENTER_PRIVATE("void");
- assert(stream != NULL);
+ assert(stream);
params = stream->isp_params_configs;
const struct ia_css_shading_table *table)
{
IA_CSS_ENTER_PRIVATE("");
- if (table == NULL)
+ if (!table)
return;
- assert(stream != NULL);
+ assert(stream);
if (!table->enable)
table = NULL;
hrt_vaddress ddr_addr,
struct ia_css_host_data *data)
{
- assert(data != NULL);
- assert(data->address != NULL);
+ assert(data);
+ assert(data->address);
assert(ddr_addr != mmgr_NULL);
IA_CSS_ENTER_PRIVATE("");
unsigned int sctbl_size;
short int *ptr;
- assert(binary != NULL);
- assert(shading_table != NULL);
+ assert(binary);
+ assert(shading_table);
IA_CSS_ENTER_PRIVATE("");
- if (shading_table == NULL) {
+ if (!shading_table) {
IA_CSS_LEAVE_PRIVATE("void");
return NULL;
}
if (!sctbl)
return NULL;
- ptr = (short int*)sctbl->address;
+ ptr = (short int *)sctbl->address;
memset(ptr,
0,
sctbl_size);
for (j = 0; j < IA_CSS_SC_NUM_COLORS; j++) {
memcpy(ptr,
&shading_table->data[j]
- [i*shading_table->width],
+ [i * shading_table->width],
shading_table->width * sizeof(short));
ptr += aligned_width;
}
IA_CSS_ENTER_PRIVATE("");
- if (sc_config == NULL) {
+ if (!sc_config) {
IA_CSS_LEAVE_PRIVATE("void");
return IA_CSS_SUCCESS;
}
const struct ia_css_pipeline_stage *stage;
enum ia_css_err err = IA_CSS_SUCCESS;
struct ia_css_resolution pipe_in_res;
+
pipe_in_res.width = 0;
pipe_in_res.height = 0;
- assert(params != NULL);
+ assert(params);
IA_CSS_ENTER_PRIVATE("");
/* Go through all stages to udate uds and cropping */
for (stage = first_stage; stage; stage = stage->next) {
-
struct ia_css_binary *binary;
/* note: the var below is made static as it is quite large;
if it is not static it ends up on the stack which could
} else {
const struct sh_css_binary_args *args = &stage->args;
const struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS] = {NULL};
+
if (args->out_frame[0])
out_infos[0] = &args->out_frame[0]->info;
info = &stage->firmware->info.isp;
pipe_in_res,
stage->enable_zoom);
if (err != IA_CSS_SUCCESS)
- return err;
+ return err;
}
}
params->isp_params_changed = true;
sh_css_set_gamma_table(struct ia_css_isp_parameters *params,
const struct ia_css_gamma_table *table)
{
- if (table == NULL)
+ if (!table)
return;
IA_CSS_ENTER_PRIVATE("table=%p", table);
- assert(params != NULL);
+ assert(params);
params->gc_table = *table;
params->config_changed[IA_CSS_GC_ID] = true;
sh_css_get_gamma_table(const struct ia_css_isp_parameters *params,
struct ia_css_gamma_table *table)
{
- if (table == NULL)
+ if (!table)
return;
IA_CSS_ENTER_PRIVATE("table=%p", table);
- assert(params != NULL);
+ assert(params);
*table = params->gc_table;
IA_CSS_LEAVE_PRIVATE("void");
sh_css_set_ctc_table(struct ia_css_isp_parameters *params,
const struct ia_css_ctc_table *table)
{
- if (table == NULL)
+ if (!table)
return;
IA_CSS_ENTER_PRIVATE("table=%p", table);
- assert(params != NULL);
+ assert(params);
params->ctc_table = *table;
params->config_changed[IA_CSS_CTC_ID] = true;
sh_css_get_ctc_table(const struct ia_css_isp_parameters *params,
struct ia_css_ctc_table *table)
{
- if (table == NULL)
+ if (!table)
return;
IA_CSS_ENTER_PRIVATE("table=%p", table);
- assert(params != NULL);
+ assert(params);
*table = params->ctc_table;
IA_CSS_LEAVE_PRIVATE("void");
sh_css_set_macc_table(struct ia_css_isp_parameters *params,
const struct ia_css_macc_table *table)
{
- if (table == NULL)
+ if (!table)
return;
IA_CSS_ENTER_PRIVATE("table=%p", table);
- assert(params != NULL);
+ assert(params);
params->macc_table = *table;
params->config_changed[IA_CSS_MACC_ID] = true;
sh_css_get_macc_table(const struct ia_css_isp_parameters *params,
struct ia_css_macc_table *table)
{
- if (table == NULL)
+ if (!table)
return;
IA_CSS_ENTER_PRIVATE("table=%p", table);
- assert(params != NULL);
+ assert(params);
*table = params->macc_table;
IA_CSS_LEAVE_PRIVATE("void");
void ia_css_morph_table_free(
struct ia_css_morph_table *me)
{
-
unsigned int i;
- if (me == NULL)
+ if (!me)
return;
IA_CSS_ENTER("");
-
-
for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) {
if (me->coordinates_x[i]) {
sh_css_free(me->coordinates_x[i]);
sh_css_free(me);
IA_CSS_LEAVE("void");
-
}
-
struct ia_css_morph_table *ia_css_morph_table_allocate(
unsigned int width,
unsigned int height)
{
-
unsigned int i;
struct ia_css_morph_table *me;
IA_CSS_ENTER("");
me = sh_css_malloc(sizeof(*me));
- if (me == NULL) {
+ if (!me) {
IA_CSS_ERROR("out of memory");
return me;
}
sh_css_malloc(height * width *
sizeof(*me->coordinates_y[i]));
- if ((me->coordinates_x[i] == NULL) ||
- (me->coordinates_y[i] == NULL)) {
+ if ((!me->coordinates_x[i]) ||
+ (!me->coordinates_y[i])) {
ia_css_morph_table_free(me);
me = NULL;
return me;
me->height = height;
IA_CSS_LEAVE("");
return me;
-
}
-
static enum ia_css_err sh_css_params_default_morph_table(
struct ia_css_morph_table **table,
const struct ia_css_binary *binary)
start_y[IA_CSS_MORPH_TABLE_NUM_PLANES] = { 0, 0, -8, -8, -8, 0 };
struct ia_css_morph_table *tab;
- assert(table != NULL);
- assert(binary != NULL);
+ assert(table);
+ assert(binary);
IA_CSS_ENTER_PRIVATE("");
height = binary->morph_tbl_height;
tab = ia_css_morph_table_allocate(width, height);
- if (tab == NULL)
+ if (!tab)
return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) {
short val_y = start_y[i];
+
for (j = 0; j < height; j++) {
short val_x = start_x[i];
unsigned short *x_ptr, *y_ptr;
sh_css_set_morph_table(struct ia_css_isp_parameters *params,
const struct ia_css_morph_table *table)
{
- if (table == NULL)
+ if (!table)
return;
IA_CSS_ENTER_PRIVATE("table=%p", table);
- assert(params != NULL);
+ assert(params);
if (table->enable == false)
table = NULL;
params->morph_table = table;
}
me->data_ptr = data_ptr;
- me->data_allocated = data_ptr == NULL;
+ me->data_allocated = !data_ptr;
if (!data_ptr) {
me->data_ptr = sh_css_malloc(isp_stats->size);
if (!me->data_ptr) {
if (me)
sh_css_free(me);
return NULL;
-
}
enum ia_css_err
IA_CSS_ENTER("host_stats=%p, isp_stats=%p", host_stats, isp_stats);
- assert(host_stats != NULL);
- assert(isp_stats != NULL);
+ assert(host_stats);
+ assert(isp_stats);
map = ia_css_isp_3a_statistics_map_allocate(isp_stats, NULL);
if (map) {
ia_css_set_param_exceptions(const struct ia_css_pipe *pipe,
struct ia_css_isp_parameters *params)
{
- assert(params != NULL);
+ assert(params);
/* Copy also to DP. Should be done by the driver. */
params->dp_config.gr = params->wb_config.gr;
params->dp_config.b = params->wb_config.b;
params->dp_config.gb = params->wb_config.gb;
#ifdef ISP2401
- assert(pipe != NULL);
+ assert(pipe);
assert(pipe->mode < IA_CSS_PIPE_ID_NUM);
if (pipe->mode < IA_CSS_PIPE_ID_NUM) {
struct ia_css_isp_parameters *params,
const struct ia_css_dp_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- assert(pipe != NULL);
+ assert(params);
+ assert(pipe);
assert(pipe->mode < IA_CSS_PIPE_ID_NUM);
IA_CSS_ENTER_PRIVATE("config=%p", config);
const struct ia_css_isp_parameters *params,
struct ia_css_dp_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
- assert(pipe != NULL);
+ assert(params);
+ assert(pipe);
IA_CSS_ENTER_PRIVATE("config=%p", config);
*config = params->pipe_dp_config[pipe->mode];
sh_css_set_nr_config(struct ia_css_isp_parameters *params,
const struct ia_css_nr_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
IA_CSS_ENTER_PRIVATE("config=%p", config);
sh_css_set_ee_config(struct ia_css_isp_parameters *params,
const struct ia_css_ee_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
IA_CSS_ENTER_PRIVATE("config=%p", config);
ia_css_ee_debug_dtrace(config, IA_CSS_DEBUG_TRACE_PRIVATE);
sh_css_get_ee_config(const struct ia_css_isp_parameters *params,
struct ia_css_ee_config *config)
{
- if (config == NULL)
+ if (!config)
return;
IA_CSS_ENTER_PRIVATE("config=%p", config);
- assert(params != NULL);
+ assert(params);
*config = params->ee_config;
ia_css_ee_debug_dtrace(config, IA_CSS_DEBUG_TRACE_PRIVATE);
struct ia_css_isp_parameters *params,
const struct ia_css_dvs_6axis_config *dvs_config)
{
- if (dvs_config == NULL)
+ if (!dvs_config)
return;
- assert(params != NULL);
- assert(pipe != NULL);
+ assert(params);
+ assert(pipe);
assert(dvs_config->height_y == dvs_config->height_uv);
assert((dvs_config->width_y - 1) == 2 * (dvs_config->width_uv - 1));
assert(pipe->mode < IA_CSS_PIPE_ID_NUM);
const struct ia_css_isp_parameters *params,
struct ia_css_dvs_6axis_config *dvs_config)
{
- if (dvs_config == NULL)
+ if (!dvs_config)
return;
- assert(params != NULL);
- assert(pipe != NULL);
+ assert(params);
+ assert(pipe);
assert(dvs_config->height_y == dvs_config->height_uv);
assert((dvs_config->width_y - 1) == 2 * dvs_config->width_uv - 1);
sh_css_set_baa_config(struct ia_css_isp_parameters *params,
const struct ia_css_aa_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
IA_CSS_ENTER_PRIVATE("config=%p", config);
sh_css_get_baa_config(const struct ia_css_isp_parameters *params,
struct ia_css_aa_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
IA_CSS_ENTER_PRIVATE("config=%p", config);
sh_css_set_dz_config(struct ia_css_isp_parameters *params,
const struct ia_css_dz_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
IA_CSS_ENTER_PRIVATE("dx=%d, dy=%d", config->dx, config->dy);
sh_css_get_dz_config(const struct ia_css_isp_parameters *params,
struct ia_css_dz_config *config)
{
- if (config == NULL)
+ if (!config)
return;
- assert(params != NULL);
+ assert(params);
IA_CSS_ENTER_PRIVATE("config=%p", config);
sh_css_set_motion_vector(struct ia_css_isp_parameters *params,
const struct ia_css_vector *motion)
{
- if (motion == NULL)
+ if (!motion)
return;
- assert(params != NULL);
+ assert(params);
IA_CSS_ENTER_PRIVATE("x=%d, y=%d", motion->x, motion->y);
sh_css_get_motion_vector(const struct ia_css_isp_parameters *params,
struct ia_css_vector *motion)
{
- if (motion == NULL)
+ if (!motion)
return;
- assert(params != NULL);
+ assert(params);
IA_CSS_ENTER_PRIVATE("motion=%p", motion);
struct ia_css_isp_config *
sh_css_pipe_isp_config_get(struct ia_css_pipe *pipe)
{
- if (pipe == NULL)
+ if (!pipe)
{
IA_CSS_ERROR("pipe=%p", NULL);
return NULL;
{
enum ia_css_err err = IA_CSS_SUCCESS;
- if ((stream == NULL) || (config == NULL))
+ if ((!stream) || (!config))
return IA_CSS_ERR_INVALID_ARGUMENTS;
IA_CSS_ENTER("stream=%p, config=%p, pipe=%p", stream, config, pipe);
IA_CSS_ENTER("pipe=%p", pipe);
- if ((pipe == NULL) || (pipe->stream == NULL))
+ if ((!pipe) || (!pipe->stream))
return IA_CSS_ERR_INVALID_ARGUMENTS;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "config=%p\n", config);
* but instead continue with updating the ISP params to enable testing of features
* which are currently in TR phase. */
- err = (err1 != IA_CSS_SUCCESS ) ? err1 : ((err2 != IA_CSS_SUCCESS) ? err2 : err);
+ err = (err1 != IA_CSS_SUCCESS) ? err1 : ((err2 != IA_CSS_SUCCESS) ? err2 : err);
IA_CSS_LEAVE_ERR_PRIVATE(err);
return err;
const struct ia_css_isp_config *config,
struct ia_css_pipe *pipe)
{
- unsigned i;
+ unsigned int i;
bool per_frame_config_created = false;
enum ia_css_err err = IA_CSS_SUCCESS;
enum ia_css_err err1 = IA_CSS_SUCCESS;
{
err = sh_css_create_isp_params(stream,
&stream->per_frame_isp_params_configs);
- if(err != IA_CSS_SUCCESS)
+ if (err != IA_CSS_SUCCESS)
goto exit;
per_frame_config_created = true;
}
{
enum ia_css_err err = IA_CSS_SUCCESS;
bool is_dp_10bpp = true;
- assert(pipe != NULL);
+
+ assert(pipe);
IA_CSS_ENTER_PRIVATE("pipe=%p, config=%p, params=%p", pipe, config, params);
ia_css_set_configs(params, config);
-
sh_css_set_nr_config(params, config->nr_config);
sh_css_set_ee_config(params, config->ee_config);
sh_css_set_baa_config(params, config->baa_config);
sh_css_set_shading_settings(params, config->shading_settings);
/* ------ deprecated(bz675) : to ------ */
- params->dis_coef_table_changed = (config->dvs_coefs != NULL);
- params->dvs2_coef_table_changed = (config->dvs2_coefs != NULL);
+ params->dis_coef_table_changed = (config->dvs_coefs);
+ params->dvs2_coef_table_changed = (config->dvs2_coefs);
params->output_frame = config->output_frame;
params->isp_parameters_id = config->isp_config_id;
* user. */
/* we do not exit from this point immediately to allow internal
* firmware feature testing. */
- if(is_dp_10bpp) {
+ if (is_dp_10bpp) {
err = IA_CSS_ERR_INVALID_ARGUMENTS;
}
} else {
{
struct ia_css_isp_parameters *params = NULL;
- assert(config != NULL);
+ assert(config);
IA_CSS_ENTER("config=%p", config);
params = pipe->stream->isp_params_configs;
- assert(params != NULL);
+ assert(params);
ia_css_get_configs(params, config);
enum ia_css_err *err,
uint16_t mmgr_attribute)
{
- int32_t id;
+ s32 id;
*err = IA_CSS_SUCCESS;
/* Possible optimization: add a function sh_css_isp_css_mm_realloc()
enum ia_css_err *err)
{
bool ret;
- uint16_t mmgr_attribute = MMGR_ATTRIBUTE_DEFAULT;
+ u16 mmgr_attribute = MMGR_ATTRIBUTE_DEFAULT;
IA_CSS_ENTER_PRIVATE("void");
IA_CSS_ENTER("grid=%p", grid);
- assert(grid != NULL);
+ assert(grid);
/* MW: Does "grid->enable" also control the histogram output ?? */
if (!grid->enable)
if (me->hmem_size)
me->data_hmem.rgby_tbl = me->data_ptr + me->dmem_size + 2 * me->vmem_size;
-
err:
IA_CSS_LEAVE("return=%p", me);
return me;
void
ia_css_isp_3a_statistics_free(struct ia_css_isp_3a_statistics *me)
{
- if (me != NULL) {
+ if (me) {
hmm_free(me->data_ptr);
sh_css_free(me);
}
return NULL;
md = sh_css_malloc(sizeof(*md));
- if (md == NULL)
+ if (!md)
goto error;
md->info = *metadata_info;
void
ia_css_metadata_free(struct ia_css_metadata *me)
{
- if (me != NULL) {
+ if (me) {
/* The enter and leave macros are placed inside
* the condition to avoid false logging of metadata
* free events when metadata is disabled.
{
unsigned int i;
- if (bufs != NULL) {
+ if (bufs) {
for (i = 0; i < num_bufs; i++)
ia_css_metadata_free(bufs[i]);
}
}
-static unsigned g_param_buffer_dequeue_count = 0;
-static unsigned g_param_buffer_enqueue_count = 0;
+static unsigned int g_param_buffer_dequeue_count;
+static unsigned int g_param_buffer_enqueue_count;
enum ia_css_err
ia_css_stream_isp_parameters_init(struct ia_css_stream *stream)
{
enum ia_css_err err = IA_CSS_SUCCESS;
- unsigned i;
+ unsigned int i;
struct sh_css_ddr_address_map *ddr_ptrs;
struct sh_css_ddr_address_map_size *ddr_ptrs_size;
struct ia_css_isp_parameters *params;
- assert(stream != NULL);
+ assert(stream);
IA_CSS_ENTER_PRIVATE("void");
- if (stream == NULL) {
+ if (!stream) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS);
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
stream->per_frame_isp_params_configs = NULL;
err = sh_css_create_isp_params(stream,
&stream->isp_params_configs);
- if(err != IA_CSS_SUCCESS)
- goto ERR;
+ if (err != IA_CSS_SUCCESS)
+ goto ERR;
params = stream->isp_params_configs;
if (!sh_css_init_isp_params_from_global(stream, params, true, NULL)) {
struct ia_css_isp_parameters **isp_params_out)
{
bool succ = true;
- unsigned i;
+ unsigned int i;
struct sh_css_ddr_address_map *ddr_ptrs;
struct sh_css_ddr_address_map_size *ddr_ptrs_size;
enum ia_css_err err = IA_CSS_SUCCESS;
bool retval = true;
int i = 0;
bool is_dp_10bpp = true;
- unsigned isp_pipe_version = ia_css_pipe_get_isp_pipe_version(stream->pipes[0]);
+ unsigned int isp_pipe_version = ia_css_pipe_get_isp_pipe_version(stream->pipes[0]);
struct ia_css_isp_parameters *stream_params = stream->isp_params_configs;
if (!use_default_config && !stream_params) {
#else
for (i = 0; i < stream->num_pipes; i++) {
- if (IA_CSS_SUCCESS == sh_css_select_dp_10bpp_config(stream->pipes[i], &is_dp_10bpp)) {
+ if (sh_css_select_dp_10bpp_config(stream->pipes[i], &is_dp_10bpp) == IA_CSS_SUCCESS) {
/* set the return value as false if both DPC and
* BDS is enabled by the user. But we do not return
* the value immediately to enable internal firmware
* feature testing. */
- if(is_dp_10bpp) {
+ if (is_dp_10bpp) {
sh_css_set_dp_config(stream->pipes[i], params, &default_dp_10bpp_config);
} else {
sh_css_set_dp_config(stream->pipes[i], params, &default_dp_config);
#ifdef ISP2401
ia_css_tnr3_set_default_config(¶ms->tnr3_config);
#endif
- }
- else
+ } else
{
ia_css_set_xnr3_config(params, &stream_params->xnr3_config);
if (stream_params->sc_table) {
sh_css_update_shading_table_status(pipe_in, params);
sh_css_set_shading_table(stream, params, stream_params->sc_table);
- }
- else {
+ } else {
params->sc_table = NULL;
params->sc_table_changed = true;
params->sc_table_dirty = false;
static void host_lut_store(const void *lut)
{
- unsigned i;
+ unsigned int i;
for (i = 0; i < N_GDC_ID; i++)
gdc_lut_store((gdc_ID_t)i, (const int (*)[HRT_GDC_N]) lut);
#endif
IA_CSS_ENTER("pipe=%p lut=%p", pipe, lut);
- if (lut == NULL || pipe == NULL) {
+ if (!lut || !pipe) {
err = IA_CSS_ERR_INVALID_ARGUMENTS;
IA_CSS_LEAVE("err=%d", err);
return err;
/* if pipe is NULL, returns default lut addr. */
hrt_vaddress sh_css_pipe_get_pp_gdc_lut(const struct ia_css_pipe *pipe)
{
- assert(pipe != NULL);
+ assert(pipe);
if (pipe->scaler_pp_lut != mmgr_NULL)
return pipe->scaler_pp_lut;
default_gdc_lut = mmgr_NULL;
IA_CSS_LEAVE_PRIVATE("void");
-
}
hrt_vaddress sh_css_params_get_default_gdc_lut(void)
do { \
ia_css_refcount_decrement(id, x); \
(x) = mmgr_NULL; \
- } while(0)
+ } while (0)
static void free_map(struct sh_css_ddr_address_map *map)
{
IA_CSS_ENTER_PRIVATE("void");
/* free buffers */
- for (i = 0; i < (sizeof(struct sh_css_ddr_address_map_size)/
+ for (i = 0; i < (sizeof(struct sh_css_ddr_address_map_size) /
sizeof(size_t)); i++) {
if (addrs[i] == mmgr_NULL)
continue;
stream->per_frame_isp_params_configs;
IA_CSS_ENTER_PRIVATE("void");
- if (params == NULL) {
+ if (!params) {
IA_CSS_LEAVE_PRIVATE("isp_param_configs is NULL");
return;
}
free_map(&per_frame_params->pipe_ddr_ptrs[i]);
/* Free up theDVS table memory blocks before recomputing new table */
if (params->pipe_dvs_6axis_config[i])
- free_dvs_6axis_table(&(params->pipe_dvs_6axis_config[i]));
+ free_dvs_6axis_table(¶ms->pipe_dvs_6axis_config[i]);
if (per_frame_params && per_frame_params->pipe_dvs_6axis_config[i])
- free_dvs_6axis_table(&(per_frame_params->pipe_dvs_6axis_config[i]));
+ free_dvs_6axis_table(&per_frame_params->pipe_dvs_6axis_config[i]);
}
free_map(¶ms->ddr_ptrs);
if (per_frame_params)
void
sh_css_params_uninit(void)
{
- unsigned p, i;
+ unsigned int p, i;
IA_CSS_ENTER_PRIVATE("void");
unsigned int i, j, padding, w;
struct ia_css_host_data *me;
unsigned int isp_data_size;
- uint16_t *isp_data_ptr;
+ u16 *isp_data_ptr;
IA_CSS_ENTER_PRIVATE("void");
}
isp_data_size = height * (w + padding) * sizeof(uint16_t);
- me = ia_css_host_data_allocate((size_t) isp_data_size);
+ me = ia_css_host_data_allocate((size_t)isp_data_size);
if (!me) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY);
IA_CSS_ENTER_PRIVATE("void");
- assert(params != NULL);
+ assert(params);
- mmgr_store(ddr_ptr, &(params->uds), size);
+ mmgr_store(ddr_ptr, ¶ms->uds, size);
IA_CSS_LEAVE_PRIVATE("void");
}
for (i = 0; SH_CSS_INVALID_QUEUE_ID != param_queue_ids[i]; i++) {
cpy = (hrt_vaddress)0;
/* clean-up old copy */
- while (IA_CSS_SUCCESS == ia_css_bufq_dequeue_buffer(param_queue_ids[i], (uint32_t *)&cpy)) {
+ while (ia_css_bufq_dequeue_buffer(param_queue_ids[i], (uint32_t *)&cpy) == IA_CSS_SUCCESS) {
/* TMP: keep track of dequeued param set count
*/
g_param_buffer_dequeue_count++;
unsigned int isp_pipe_version,
unsigned int raw_bit_depth)
{
- unsigned param_id;
+ unsigned int param_id;
(void)isp_pipe_version;
(void)raw_bit_depth;
(void)acc_cluster_params_changed;
- assert(curr_pipe != NULL);
+ assert(curr_pipe);
IA_CSS_ENTER_PRIVATE("pipe=%p, isp_parameters_id=%d", pipe_in, params->isp_parameters_id);
raw_bit_depth = ia_css_stream_input_format_bits_per_pixel(curr_pipe->stream);
err = ia_css_process_zoom_and_motion(params,
pipeline->stages);
if (err != IA_CSS_SUCCESS)
- return err;
+ return err;
}
/* check if to actually update the parameters for this pipe */
/* When API change is implemented making good distinction between
/* BZ 125915, should be moved till after "update other buff" */
/* update the other buffers to the pipe specific copies */
for (stage = pipeline->stages; stage; stage = stage->next) {
- unsigned mem;
+ unsigned int mem;
if (!stage || !stage->binary)
continue;
IA_CSS_LOG("queue param set %x to %d", cpy, thread_id);
err = ia_css_bufq_enqueue_buffer(thread_id, queue_id, (uint32_t)cpy);
- if (IA_CSS_SUCCESS != err) {
+ if (err != IA_CSS_SUCCESS) {
free_ia_css_isp_parameter_set_info(cpy);
#if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS)
IA_CSS_LOG("pfp: FAILED to add config id %d for OF %d to q %d on thread %d",
queue_id, thread_id);
#endif
break;
- }
- else {
+ } else {
/* TMP: check discrepancy between nr of enqueued
* parameter sets and dequeued sets
*/
g_param_buffer_enqueue_count++;
- assert(g_param_buffer_enqueue_count < g_param_buffer_dequeue_count+50);
+ assert(g_param_buffer_enqueue_count < g_param_buffer_dequeue_count + 50);
#ifdef ISP2401
ia_css_save_latest_paramset_ptr(pipe, cpy);
#endif
static enum ia_css_err
sh_css_params_write_to_ddr_internal(
struct ia_css_pipe *pipe,
- unsigned pipe_id,
+ unsigned int pipe_id,
struct ia_css_isp_parameters *params,
const struct ia_css_pipeline_stage *stage,
struct sh_css_ddr_address_map *ddr_map,
enum ia_css_err err;
const struct ia_css_binary *binary;
- unsigned stage_num;
- unsigned mem;
+ unsigned int stage_num;
+ unsigned int mem;
bool buff_realloced;
/* struct is > 128 bytes so it should not be on stack (see checkpatch) */
static struct ia_css_macc_table converted_macc_table;
IA_CSS_ENTER_PRIVATE("void");
- assert(params != NULL);
- assert(ddr_map != NULL);
- assert(ddr_map_size != NULL);
- assert(stage != NULL);
+ assert(params);
+ assert(ddr_map);
+ assert(ddr_map_size);
+ assert(stage);
binary = stage->binary;
- assert(binary != NULL);
-
+ assert(binary);
stage_num = stage->stage_num;
}
if (binary->info->sp.enable.sc) {
- uint32_t enable_conv = params->
+ u32 enable_conv = params->
shading_settings.enable_shading_table_conversion;
buff_realloced = reallocate_buffer(&ddr_map->sc_tbl,
sh_css_params_shading_id_table_generate(¶ms->sc_config,
binary->sctbl_width_per_color, binary->sctbl_height);
#endif
- if (params->sc_config == NULL) {
+ if (!params->sc_config) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY);
return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
}
params->sensor_binning,
¶ms->sc_config,
binary, pipe->required_bds_factor);
- if (params->sc_config == NULL) {
+ if (!params->sc_config) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY);
return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
}
* DPC kernel. The code below sets the pipe specific configuration to
* individual binaries. */
if (params->pipe_dpc_config_changed[pipe_id] && binary->info->sp.enable.dpc) {
- unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.dp.size;
+ unsigned int size = stage->binary->info->mem_offsets.offsets.param->dmem.dp.size;
+
+ unsigned int offset = stage->binary->info->mem_offsets.offsets.param->dmem.dp.offset;
- unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.dp.offset;
if (size) {
ia_css_dp_encode((struct sh_css_isp_dp_params *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset],
0, 1, 3, 2, 6, 7, 5, 4, 12, 13, 15, 14, 10, 11, 9, 8};
for (i = 0; i < IA_CSS_MACC_NUM_AXES; i++) {
- idx = 4*idx_map[i];
- j = 4*i;
+ idx = 4 * idx_map[i];
+ j = 4 * i;
if (binary->info->sp.pipeline.isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_1) {
converted_macc_table.data[idx] =
(int16_t)sDIGIT_FITTING(params->macc_table.data[j],
13, SH_CSS_MACC_COEF_SHIFT);
- converted_macc_table.data[idx+1] =
- (int16_t)sDIGIT_FITTING(params->macc_table.data[j+1],
+ converted_macc_table.data[idx + 1] =
+ (int16_t)sDIGIT_FITTING(params->macc_table.data[j + 1],
13, SH_CSS_MACC_COEF_SHIFT);
- converted_macc_table.data[idx+2] =
- (int16_t)sDIGIT_FITTING(params->macc_table.data[j+2],
+ converted_macc_table.data[idx + 2] =
+ (int16_t)sDIGIT_FITTING(params->macc_table.data[j + 2],
13, SH_CSS_MACC_COEF_SHIFT);
- converted_macc_table.data[idx+3] =
- (int16_t)sDIGIT_FITTING(params->macc_table.data[j+3],
+ converted_macc_table.data[idx + 3] =
+ (int16_t)sDIGIT_FITTING(params->macc_table.data[j + 3],
13, SH_CSS_MACC_COEF_SHIFT);
} else if (binary->info->sp.pipeline.isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_2_2) {
converted_macc_table.data[idx] =
params->macc_table.data[j];
- converted_macc_table.data[idx+1] =
- params->macc_table.data[j+1];
- converted_macc_table.data[idx+2] =
- params->macc_table.data[j+2];
- converted_macc_table.data[idx+3] =
- params->macc_table.data[j+3];
+ converted_macc_table.data[idx + 1] =
+ params->macc_table.data[j + 1];
+ converted_macc_table.data[idx + 2] =
+ params->macc_table.data[j + 2];
+ converted_macc_table.data[idx + 3] =
+ params->macc_table.data[j + 3];
}
}
reallocate_buffer(&ddr_map->macc_tbl,
if (params->pipe_dvs_6axis_config_changed[pipe_id] || buff_realloced) {
const struct ia_css_frame_info *dvs_in_frame_info;
- if ( stage->args.delay_frames[0] ) {
+ if (stage->args.delay_frames[0]) {
/*When delay frames are present(as in case of video),
they are used for dvs. Configure DVS using those params*/
dvs_in_frame_info = &stage->args.delay_frames[0]->info;
}
/* Generate default DVS unity table on start up*/
- if (params->pipe_dvs_6axis_config[pipe_id] == NULL) {
-
+ if (!params->pipe_dvs_6axis_config[pipe_id]) {
#ifndef ISP2401
struct ia_css_resolution dvs_offset;
+
dvs_offset.width =
#else
struct ia_css_resolution dvs_offset = {0, 0};
+
if (binary->dvs_envelope.width || binary->dvs_envelope.height) {
dvs_offset.width =
#endif
params->pipe_dvs_6axis_config[pipe_id] =
generate_dvs_6axis_table(&binary->out_frame_info[0].res, &dvs_offset);
- if (params->pipe_dvs_6axis_config[pipe_id] == NULL) {
+ if (!params->pipe_dvs_6axis_config[pipe_id]) {
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY);
return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
}
const struct ia_css_morph_table *table = params->morph_table;
struct ia_css_morph_table *id_table = NULL;
- if ((table != NULL) &&
+ if ((table) &&
(table->width < binary->morph_tbl_width ||
table->height < binary->morph_tbl_height)) {
table = NULL;
}
- if (table == NULL) {
+ if (!table) {
err = sh_css_params_default_morph_table(&id_table,
binary);
if (err != IA_CSS_SUCCESS) {
*virt_addr_tetra_y[i],
binary->morph_tbl_aligned_width);
}
- if (id_table != NULL)
+ if (id_table)
ia_css_morph_table_free(id_table);
}
}
const struct ia_css_isp_data *isp_data =
ia_css_isp_param_get_isp_mem_init(&binary->info->sp.mem_initializers, IA_CSS_PARAM_CLASS_PARAM, mem);
size_t size = isp_data->size;
+
if (!size) continue;
buff_realloced = reallocate_buffer(&ddr_map->isp_mem_param[stage_num][mem],
&ddr_map_size->isp_mem_param[stage_num][mem],
struct ia_css_isp_parameters *params;
IA_CSS_ENTER_LEAVE("void");
- assert(stream != NULL);
+ assert(stream);
params = stream->isp_params_configs;
- return &(params->fpn_config);
+ return ¶ms->fpn_config;
}
struct ia_css_shading_table *ia_css_get_shading_table(struct ia_css_stream *stream)
IA_CSS_ENTER("void");
- assert(stream != NULL);
+ assert(stream);
params = stream->isp_params_configs;
if (!params)
pipe = stream->pipes[0];
if (stream->num_pipes == 2) {
- assert(stream->pipes[1] != NULL);
+ assert(stream->pipes[1]);
if (stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_VIDEO ||
stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_PREVIEW)
pipe = stream->pipes[1];
return table;
}
-
hrt_vaddress sh_css_store_sp_group_to_ddr(void)
{
IA_CSS_ENTER_LEAVE_PRIVATE("void");
}
hrt_vaddress sh_css_store_sp_stage_to_ddr(
- unsigned pipe,
- unsigned stage)
+ unsigned int pipe,
+ unsigned int stage)
{
IA_CSS_ENTER_LEAVE_PRIVATE("void");
mmgr_store(xmem_sp_stage_ptrs[pipe][stage],
}
hrt_vaddress sh_css_store_isp_stage_to_ddr(
- unsigned pipe,
- unsigned stage)
+ unsigned int pipe,
+ unsigned int stage)
{
IA_CSS_ENTER_LEAVE_PRIVATE("void");
mmgr_store(xmem_isp_stage_ptrs[pipe][stage],
} in_addrs, to_addrs;
IA_CSS_ENTER_PRIVATE("void");
- assert(map != NULL);
- assert(out != NULL);
+ assert(map);
+ assert(out);
in_addrs.map = map;
to_addrs.map = out;
- assert(sizeof(struct sh_css_ddr_address_map_size)/sizeof(size_t) ==
- sizeof(struct sh_css_ddr_address_map)/sizeof(hrt_vaddress));
+ assert(sizeof(struct sh_css_ddr_address_map_size) / sizeof(size_t) ==
+ sizeof(struct sh_css_ddr_address_map) / sizeof(hrt_vaddress));
/* copy map using size info */
- for (i = 0; i < (sizeof(struct sh_css_ddr_address_map_size)/
+ for (i = 0; i < (sizeof(struct sh_css_ddr_address_map_size) /
sizeof(size_t)); i++) {
if (in_addrs.addrs[i] == mmgr_NULL)
to_addrs.addrs[i] = mmgr_NULL;
IA_CSS_ENTER_PRIVATE("void");
- assert(me != NULL);
- assert(out != NULL);
+ assert(me);
+ assert(out);
*out = ia_css_refcount_increment(IA_CSS_REFCOUNT_PARAM_SET_POOL, mmgr_malloc(
sizeof(struct ia_css_isp_parameter_set_info)));
mmgr_load(ptr, &isp_params_info.mem_map, sizeof(struct sh_css_ddr_address_map));
/* copy map using size info */
- for (i = 0; i < (sizeof(struct sh_css_ddr_address_map_size)/
+ for (i = 0; i < (sizeof(struct sh_css_ddr_address_map_size) /
sizeof(size_t)); i++) {
if (addrs[i] == mmgr_NULL)
continue;
sh_css_invalidate_params(struct ia_css_stream *stream)
{
struct ia_css_isp_parameters *params;
- unsigned i, j, mem;
+ unsigned int i, j, mem;
IA_CSS_ENTER_PRIVATE("void");
- assert(stream != NULL);
+ assert(stream);
params = stream->isp_params_configs;
params->isp_params_changed = true;
/*Free up theDVS table memory blocks before recomputing new table */
for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) {
if (params->pipe_dvs_6axis_config[i]) {
- free_dvs_6axis_table(&(params->pipe_dvs_6axis_config[i]));
+ free_dvs_6axis_table(¶ms->pipe_dvs_6axis_config[i]);
params->pipe_dvs_6axis_config_changed[i] = true;
}
}
const struct ia_css_vector *motion_vector,
struct sh_css_uds_info *uds, /* out */
struct sh_css_crop_pos *sp_out_crop_pos, /* out */
+
bool enable_zoom)
{
IA_CSS_ENTER_PRIVATE("void");
- assert(info != NULL);
- assert(in_frame_info != NULL);
- assert(out_frame_info != NULL);
- assert(dvs_env != NULL);
- assert(zoom != NULL);
- assert(motion_vector != NULL);
- assert(uds != NULL);
- assert(sp_out_crop_pos != NULL);
+ assert(info);
+ assert(in_frame_info);
+ assert(out_frame_info);
+ assert(dvs_env);
+ assert(zoom);
+ assert(motion_vector);
+ assert(uds);
+ assert(sp_out_crop_pos);
uds->curr_dx = enable_zoom ? (uint16_t)zoom->dx : HRT_GDC_N;
uds->curr_dy = enable_zoom ? (uint16_t)zoom->dy : HRT_GDC_N;
motion_y = clamp(motion_y, -half_env_y, half_env_y);
/* for video with downscaling, the envelope is included
in the input resolution. */
- uds_xc = in_frame_info->res.width/2 + motion_x;
- uds_yc = in_frame_info->res.height/2 + motion_y;
+ uds_xc = in_frame_info->res.width / 2 + motion_x;
+ uds_yc = in_frame_info->res.height / 2 + motion_y;
crop_x = info->pipeline.left_cropping;
/* ds == 2 (yuv_ds) can be pipelined, remove top
lines */
uds->yc = (uint16_t)uds_yc;
sp_out_crop_pos->x = (uint16_t)crop_x;
sp_out_crop_pos->y = (uint16_t)crop_y;
- }
- else {
+ } else {
/* for down scaling, we always use the center of the image */
uds->xc = (uint16_t)in_frame_info->res.width / 2;
uds->yc = (uint16_t)in_frame_info->res.height / 2;
* Ideally, That should be done on host side not on sp side.
*/
unsigned int filter_envelope = 0;
+
IA_CSS_ENTER_PRIVATE("void");
- assert(info != NULL);
- assert(in_frame_info != NULL);
- assert(out_frame_info != NULL);
- assert(dvs_env != NULL);
- assert(zoom != NULL);
- assert(motion_vector != NULL);
- assert(uds != NULL);
- assert(sp_out_crop_pos != NULL);
+ assert(info);
+ assert(in_frame_info);
+ assert(out_frame_info);
+ assert(dvs_env);
+ assert(zoom);
+ assert(motion_vector);
+ assert(uds);
+ assert(sp_out_crop_pos);
x0 = zoom->zoom_region.origin.x;
y0 = zoom->zoom_region.origin.y;
x1 = zoom->zoom_region.resolution.width + x0;
y1 = zoom->zoom_region.resolution.height + y0;
if ((x0 > x1) || (y0 > y1) || (x1 > pipe_in_res.width) || (y1 > pipe_in_res.height))
- return IA_CSS_ERR_INVALID_ARGUMENTS;
+ return IA_CSS_ERR_INVALID_ARGUMENTS;
if (!enable_zoom) {
uds->curr_dx = HRT_GDC_N;
((y1 - y0 - filter_envelope) * HRT_GDC_N) / in_frame_info->res.height;
/* B. Calculate xc/yc based on crop region */
- uds->xc = (uint16_t) x0 + (((x1)-(x0)) / 2);
- uds->yc = (uint16_t) y0 + (((y1)-(y0)) / 2);
+ uds->xc = (uint16_t)x0 + (((x1) - (x0)) / 2);
+ uds->yc = (uint16_t)y0 + (((y1) - (y0)) / 2);
} else {
uds->xc = (uint16_t)in_frame_info->res.width / 2;
uds->yc = (uint16_t)in_frame_info->res.height / 2;
IA_CSS_ENTER("grid=%p", grid);
- assert(grid != NULL);
+ assert(grid);
me = sh_css_calloc(1, sizeof(*me));
if (!me)
{
struct ia_css_dvs_statistics *me;
- assert(grid != NULL);
+ assert(grid);
me = sh_css_calloc(1, sizeof(*me));
if (!me)
err:
ia_css_dvs_statistics_free(me);
return NULL;
-
}
void
{
struct ia_css_dvs_coefficients *me;
- assert(grid != NULL);
+ assert(grid);
me = sh_css_calloc(1, sizeof(*me));
if (!me)
{
struct ia_css_dvs2_statistics *me;
- assert(grid != NULL);
+ assert(grid);
me = sh_css_calloc(1, sizeof(*me));
if (!me)
err:
ia_css_dvs2_statistics_free(me);
return NULL;
-
}
void
}
}
-
struct ia_css_dvs2_coefficients *
ia_css_dvs2_coefficients_allocate(const struct ia_css_dvs_grid_info *grid)
{
struct ia_css_dvs2_coefficients *me;
- assert(grid != NULL);
+ assert(grid);
me = sh_css_calloc(1, sizeof(*me));
if (!me)
unsigned int width_uv;
unsigned int height_uv;
- assert(stream != NULL);
+ assert(stream);
params = stream->isp_params_configs;
/* Backward compatibility by default consider pipe as Video*/
enum ia_css_err err;
int i;
- if (stream == NULL)
+ if (!stream)
return;
for (i = 0; i < stream->num_pipes; i++) {
}
}
}
-
#include "uds/uds_1.0/ia_css_uds_param.h"
#include "crop/crop_1.0/ia_css_crop_types.h"
-
#define PIX_SHIFT_FILTER_RUN_IN_X 12
#define PIX_SHIFT_FILTER_RUN_IN_Y 12
struct sh_css_isp_ob_stream_config ob;
};
-
/* Isp parameters per stream */
struct ia_css_isp_parameters {
/* UDS */
struct ia_css_dvs2_coefficients dvs2_coefs;
bool isp_params_changed;
+
bool isp_mem_params_changed
[IA_CSS_PIPE_ID_NUM][SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES];
bool dz_config_changed;
struct sh_css_ddr_address_map ddr_ptrs;
struct sh_css_ddr_address_map_size ddr_ptrs_size;
struct ia_css_frame *output_frame; /** Output frame the config is to be applied to (optional) */
- uint32_t isp_parameters_id; /** Unique ID to track which config was actually applied to a particular frame */
+ u32 isp_parameters_id; /** Unique ID to track which config was actually applied to a particular frame */
};
void
void
ia_css_get_properties(struct ia_css_properties *properties)
{
- assert(properties != NULL);
+ assert(properties);
#if defined(HAS_GDC_VERSION_2) || defined(HAS_GDC_VERSION_3)
/*
* MW: We don't want to store the coordinates
* full range in memory: Truncate
*/
- properties->gdc_coord_one = gdc_get_unity(GDC0_ID)/HRT_GDC_COORD_SCALE;
+ properties->gdc_coord_one = gdc_get_unity(GDC0_ID) / HRT_GDC_COORD_SCALE;
#else
#error "Unknown GDC version"
#endif
#include "ia_css_spctrl.h"
#ifndef offsetof
-#define offsetof(T, x) ((unsigned)&(((T *)0)->x))
+#define offsetof(T, x) ((unsigned int)&(((T *)0)->x))
#endif
#define IA_CSS_INCLUDE_CONFIGURATIONS
static enum ia_css_err
set_output_frame_buffer(const struct ia_css_frame *frame,
- unsigned idx);
+ unsigned int idx);
static void
sh_css_copy_buffer_attr_to_spbuffer(struct ia_css_buffer_sp *dest_buf,
copy_isp_stage_to_sp_stage(void)
{
/* [WW07.5]type casting will cause potential issues */
- sh_css_sp_stage.num_stripes = (uint8_t) sh_css_isp_stage.binary_info.iterator.num_stripes;
- sh_css_sp_stage.row_stripes_height = (uint16_t) sh_css_isp_stage.binary_info.iterator.row_stripes_height;
- sh_css_sp_stage.row_stripes_overlap_lines = (uint16_t) sh_css_isp_stage.binary_info.iterator.row_stripes_overlap_lines;
- sh_css_sp_stage.top_cropping = (uint16_t) sh_css_isp_stage.binary_info.pipeline.top_cropping;
+ sh_css_sp_stage.num_stripes = (uint8_t)sh_css_isp_stage.binary_info.iterator.num_stripes;
+ sh_css_sp_stage.row_stripes_height = (uint16_t)sh_css_isp_stage.binary_info.iterator.row_stripes_height;
+ sh_css_sp_stage.row_stripes_overlap_lines = (uint16_t)sh_css_isp_stage.binary_info.iterator.row_stripes_overlap_lines;
+ sh_css_sp_stage.top_cropping = (uint16_t)sh_css_isp_stage.binary_info.pipeline.top_cropping;
/* moved to sh_css_sp_init_stage
sh_css_sp_stage.enable.vf_output =
sh_css_isp_stage.binary_info.enable.vf_veceven ||
}
void
-store_sp_stage_data(enum ia_css_pipe_id id, unsigned int pipe_num, unsigned stage)
+store_sp_stage_data(enum ia_css_pipe_id id, unsigned int pipe_num, unsigned int stage)
{
unsigned int thread_id;
+
ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id);
copy_isp_stage_to_sp_stage();
if (id != IA_CSS_PIPE_ID_COPY)
{
unsigned int HIVE_ADDR_sp_per_frame_data = 0;
- assert(fw != NULL);
+ assert(fw);
switch (fw->type) {
case ia_css_sp_firmware:
{
const struct ia_css_fw_info *fw = &sh_css_sp_fw;
unsigned int HIVE_ADDR_sp_output = fw->info.sp.output;
- unsigned i;
- unsigned offset = (unsigned int)offsetof(struct sh_css_sp_output, debug)/sizeof(int);
+ unsigned int i;
+ unsigned int offset = (unsigned int)offsetof(struct sh_css_sp_output, debug) / sizeof(int);
- assert(state != NULL);
+ assert(state);
(void)HIVE_ADDR_sp_output; /* To get rid of warning in CRUN */
- for (i = 0; i < sizeof(*state)/sizeof(int); i++)
- ((unsigned *)state)[i] = load_sp_array_uint(sp_output, i+offset);
+ for (i = 0; i < sizeof(*state) / sizeof(int); i++)
+ ((unsigned *)state)[i] = load_sp_array_uint(sp_output, i + offset);
}
#endif
void
sh_css_sp_start_binary_copy(unsigned int pipe_num, struct ia_css_frame *out_frame,
- unsigned two_ppc)
+ unsigned int two_ppc)
{
enum ia_css_pipe_id pipe_id;
unsigned int thread_id;
struct sh_css_sp_pipeline *pipe;
- uint8_t stage_num = 0;
+ u8 stage_num = 0;
- assert(out_frame != NULL);
+ assert(out_frame);
pipe_id = IA_CSS_PIPE_ID_CAPTURE;
ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id);
pipe = &sh_css_sp_group.pipe[thread_id];
static void
sh_css_sp_start_raw_copy(struct ia_css_frame *out_frame,
- unsigned pipe_num,
- unsigned two_ppc,
- unsigned max_input_width,
+ unsigned int pipe_num,
+ unsigned int two_ppc,
+ unsigned int max_input_width,
enum sh_css_pipe_config_override pipe_conf_override,
unsigned int if_config_index)
{
enum ia_css_pipe_id pipe_id;
unsigned int thread_id;
- uint8_t stage_num = 0;
+ u8 stage_num = 0;
struct sh_css_sp_pipeline *pipe;
- assert(out_frame != NULL);
+ assert(out_frame);
{
/*
* program_input_circuit must be saved as it is set outside
* this function.
*/
- uint8_t program_input_circuit;
+ u8 program_input_circuit;
+
program_input_circuit = sh_css_sp_stage.program_input_circuit;
memset(&sh_css_sp_stage, 0, sizeof(sh_css_sp_stage));
sh_css_sp_stage.program_input_circuit = program_input_circuit;
sh_css_sp_stage.xmem_bin_addr = 0x0;
sh_css_sp_stage.stage_type = SH_CSS_SP_STAGE_TYPE;
sh_css_sp_stage.func = (unsigned int)IA_CSS_PIPELINE_RAW_COPY;
- sh_css_sp_stage.if_config_index = (uint8_t) if_config_index;
+ sh_css_sp_stage.if_config_index = (uint8_t)if_config_index;
set_output_frame_buffer(out_frame, 0);
ia_css_debug_pipe_graph_dump_sp_raw_copy(out_frame);
static void
sh_css_sp_start_isys_copy(struct ia_css_frame *out_frame,
- unsigned pipe_num, unsigned max_input_width, unsigned int if_config_index)
+ unsigned int pipe_num, unsigned int max_input_width, unsigned int if_config_index)
{
enum ia_css_pipe_id pipe_id;
unsigned int thread_id;
- uint8_t stage_num = 0;
+ u8 stage_num = 0;
struct sh_css_sp_pipeline *pipe;
#if defined SH_CSS_ENABLE_METADATA
enum sh_css_queue_id queue_id;
#endif
- assert(out_frame != NULL);
+ assert(out_frame);
{
/*
* program_input_circuit must be saved as it is set outside
* this function.
*/
- uint8_t program_input_circuit;
+ u8 program_input_circuit;
+
program_input_circuit = sh_css_sp_stage.program_input_circuit;
memset(&sh_css_sp_stage, 0, sizeof(sh_css_sp_stage));
sh_css_sp_stage.program_input_circuit = program_input_circuit;
sh_css_sp_stage.xmem_bin_addr = 0x0;
sh_css_sp_stage.stage_type = SH_CSS_SP_STAGE_TYPE;
sh_css_sp_stage.func = (unsigned int)IA_CSS_PIPELINE_ISYS_COPY;
- sh_css_sp_stage.if_config_index = (uint8_t) if_config_index;
+ sh_css_sp_stage.if_config_index = (uint8_t)if_config_index;
set_output_frame_buffer(out_frame, 0);
unsigned int offset = (unsigned int)offsetof(struct sh_css_sp_output, sw_interrupt_value)
/ sizeof(int);
(void)HIVE_ADDR_sp_output; /* To get rid of warning in CRUN */
- return load_sp_array_uint(sp_output, offset+irq);
+ return load_sp_array_uint(sp_output, offset + irq);
}
static void
sh_css_copy_frame_to_spframe(struct ia_css_frame_sp *sp_frame_out,
const struct ia_css_frame *frame_in)
{
- assert(frame_in != NULL);
+ assert(frame_in);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"sh_css_copy_frame_to_spframe():\n");
-
sh_css_copy_buffer_attr_to_spbuffer(&sp_frame_out->buf_attr,
frame_in->dynamic_queue_id,
frame_in->data,
memset(&sp_frame_out->planes, 0, sizeof(sp_frame_out->planes));
break;
}
-
}
static enum ia_css_err
set_input_frame_buffer(const struct ia_css_frame *frame)
{
- if (frame == NULL)
+ if (!frame)
return IA_CSS_ERR_INVALID_ARGUMENTS;
switch (frame->info.format) {
static enum ia_css_err
set_output_frame_buffer(const struct ia_css_frame *frame,
- unsigned idx)
+ unsigned int idx)
{
- if (frame == NULL)
+ if (!frame)
return IA_CSS_ERR_INVALID_ARGUMENTS;
switch (frame->info.format) {
static enum ia_css_err
set_view_finder_buffer(const struct ia_css_frame *frame)
{
- if (frame == NULL)
+ if (!frame)
return IA_CSS_ERR_INVALID_ARGUMENTS;
switch (frame->info.format) {
)
{
assert(if_config_index < SH_CSS_MAX_IF_CONFIGS);
- assert(config_a != NULL);
+ assert(config_a);
sh_css_sp_group.config.input_formatter.set[if_config_index].config_a = *config_a;
sh_css_sp_group.config.input_formatter.a_changed = true;
- if (config_b != NULL) {
+ if (config_b) {
sh_css_sp_group.config.input_formatter.set[if_config_index].config_b = *config_b;
sh_css_sp_group.config.input_formatter.b_changed = true;
}
enum ia_css_err err = IA_CSS_SUCCESS;
int i;
- assert(args != NULL);
+ assert(args);
if (args->in_frame)
err = set_input_frame_buffer(args->in_frame);
void
sh_css_stage_write_binary_info(struct ia_css_binary_info *info)
{
- assert(info != NULL);
+ assert(info);
sh_css_isp_stage.binary_info = *info;
}
static bool
is_sp_stage(struct ia_css_pipeline_stage *stage)
{
- assert(stage != NULL);
+ assert(stage);
return stage->sp_func != IA_CSS_PIPELINE_NO_FUNC;
}
const struct ia_css_blob_info *blob_info,
const struct sh_css_binary_args *args,
unsigned int pipe_num,
- unsigned stage,
+ unsigned int stage,
bool xnr,
const struct ia_css_isp_param_css_segments *isp_mem_if,
unsigned int if_config_index,
enum sh_css_queue_id queue_id;
bool continuous = sh_css_continuous_is_enabled((uint8_t)pipe_num);
- assert(binary != NULL);
- assert(blob_info != NULL);
- assert(args != NULL);
- assert(isp_mem_if != NULL);
+ assert(binary);
+ assert(blob_info);
+ assert(args);
+ assert(isp_mem_if);
xinfo = binary->info;
info = &xinfo->sp;
* program_input_circuit must be saved as it is set outside
* this function.
*/
- uint8_t program_input_circuit;
+ u8 program_input_circuit;
+
program_input_circuit = sh_css_sp_stage.program_input_circuit;
memset(&sh_css_sp_stage, 0, sizeof(sh_css_sp_stage));
sh_css_sp_stage.program_input_circuit = (uint8_t)program_input_circuit;
ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id);
- if (info == NULL) {
+ if (!info) {
sh_css_sp_group.pipe[thread_id].sp_stage_addr[stage] = mmgr_NULL;
return IA_CSS_SUCCESS;
}
sh_css_sp_stage.isp_deci_log_factor = (uint8_t)binary->deci_factor_log2;
sh_css_sp_stage.isp_vf_downscale_bits = (uint8_t)binary->vf_downscale_log2;
- sh_css_sp_stage.if_config_index = (uint8_t) if_config_index;
+ sh_css_sp_stage.if_config_index = (uint8_t)if_config_index;
sh_css_sp_stage.sp_enable_xnr = (uint8_t)xnr;
sh_css_sp_stage.xmem_bin_addr = xinfo->xmem_addr;
sh_css_stage_write_binary_info((struct ia_css_binary_info *)info);
/* Make sure binary name is smaller than allowed string size */
- assert(strlen(binary_name) < SH_CSS_MAX_BINARY_NAME-1);
- strncpy(sh_css_isp_stage.binary_name, binary_name, SH_CSS_MAX_BINARY_NAME-1);
+ assert(strlen(binary_name) < SH_CSS_MAX_BINARY_NAME - 1);
+ strncpy(sh_css_isp_stage.binary_name, binary_name, SH_CSS_MAX_BINARY_NAME - 1);
sh_css_isp_stage.binary_name[SH_CSS_MAX_BINARY_NAME - 1] = 0;
sh_css_isp_stage.mem_initializers = *isp_mem_if;
#ifndef ISP2401
if (args->in_frame) {
pipe = find_pipe_by_num(sh_css_sp_group.pipe[thread_id].pipe_num);
- if (pipe == NULL)
+ if (!pipe)
return IA_CSS_ERR_INTERNAL_ERROR;
ia_css_get_crop_offsets(pipe, &args->in_frame->info);
} else if (&binary->in_frame_info) {
pipe = find_pipe_by_num(sh_css_sp_group.pipe[thread_id].pipe_num);
- if (pipe == NULL)
+ if (!pipe)
return IA_CSS_ERR_INTERNAL_ERROR;
ia_css_get_crop_offsets(pipe, &binary->in_frame_info);
#else
if (stage == 0) {
if (args->in_frame) {
pipe = find_pipe_by_num(sh_css_sp_group.pipe[thread_id].pipe_num);
- if (pipe == NULL)
+ if (!pipe)
return IA_CSS_ERR_INTERNAL_ERROR;
ia_css_get_crop_offsets(pipe, &args->in_frame->info);
} else if (&binary->in_frame_info) {
pipe = find_pipe_by_num(sh_css_sp_group.pipe[thread_id].pipe_num);
- if (pipe == NULL)
+ if (!pipe)
return IA_CSS_ERR_INTERNAL_ERROR;
ia_css_get_crop_offsets(pipe, &binary->in_frame_info);
}
struct ia_css_binary *binary;
const struct ia_css_fw_info *firmware;
const struct sh_css_binary_args *args;
- unsigned stage_num;
+ unsigned int stage_num;
/*
* Initialiser required because of the "else" path below.
* Is this a valid path ?
enum ia_css_err err = IA_CSS_SUCCESS;
- assert(stage != NULL);
+ assert(stage);
binary = stage->binary;
firmware = stage->firmware;
args = &stage->args;
stage_num = stage->stage_num;
-
if (binary) {
info = binary->info;
binary_name = (const char *)(info->blob->name);
ia_css_init_memory_interface(mem_if, &binary->mem_params, &binary->css_params);
} else if (firmware) {
const struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS] = {NULL};
+
if (args->out_frame[0])
out_infos[0] = &args->out_frame[0]->info;
info = &firmware->info.isp;
static void
sp_init_sp_stage(struct ia_css_pipeline_stage *stage,
- unsigned pipe_num,
+ unsigned int pipe_num,
bool two_ppc,
enum sh_css_pipe_config_override copy_ovrd,
unsigned int if_config_index)
{
const struct sh_css_binary_args *args = &stage->args;
- assert(stage != NULL);
+ assert(stage);
switch (stage->sp_func) {
case IA_CSS_PIPELINE_RAW_COPY:
sh_css_sp_start_raw_copy(args->out_frame[0],
void
sh_css_sp_init_pipeline(struct ia_css_pipeline *me,
enum ia_css_pipe_id id,
- uint8_t pipe_num,
+ u8 pipe_num,
bool xnr,
bool two_ppc,
bool continuous,
struct ia_css_pipeline_stage *stage = NULL;
struct ia_css_binary *first_binary = NULL;
struct ia_css_pipe *pipe = NULL;
- unsigned num;
+ unsigned int num;
enum ia_css_pipe_id pipe_id = id;
unsigned int thread_id;
- uint8_t if_config_index, tmp_if_config_index;
+ u8 if_config_index, tmp_if_config_index;
- assert(me != NULL);
+ assert(me);
#if !defined(HAS_NO_INPUT_SYSTEM)
- assert(me->stages != NULL);
+ assert(me->stages);
first_binary = me->stages->binary;
assert(port_id < N_MIPI_PORT_ID);
if (port_id >= N_MIPI_PORT_ID) /* should not happen but KW does not know */
return; /* we should be able to return an error */
- if_config_index = (uint8_t) (port_id - MIPI_PORT0_ID);
+ if_config_index = (uint8_t)(port_id - MIPI_PORT0_ID);
} else if (input_mode == IA_CSS_INPUT_MODE_MEMORY) {
if_config_index = SH_CSS_IF_CONFIG_NOT_NEEDED;
} else {
}
me->num_stages = num;
- if (first_binary != NULL) {
+ if (first_binary) {
/* Init pipeline data */
sh_css_sp_init_group(two_ppc, first_binary->input_format,
offline, if_config_index);
sh_css_sp_group.pipe[thread_id].inout_port_config = me->inout_port_config;
pipe = find_pipe_by_num(pipe_num);
- assert(pipe != NULL);
- if (pipe == NULL) {
+ assert(pipe);
+ if (!pipe) {
return;
}
sh_css_sp_group.pipe[thread_id].scaler_pp_lut = sh_css_pipe_get_pp_gdc_lut(pipe);
#if defined(SH_CSS_ENABLE_METADATA)
- if (md_info != NULL && md_info->size > 0) {
+ if (md_info && md_info->size > 0) {
sh_css_sp_group.pipe[thread_id].metadata.width = md_info->resolution.width;
sh_css_sp_group.pipe[thread_id].metadata.height = md_info->resolution.height;
sh_css_sp_group.pipe[thread_id].metadata.stride = md_info->stride;
#if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS)
sh_css_sp_group.pipe[thread_id].output_frame_queue_id = (uint32_t)SH_CSS_INVALID_QUEUE_ID;
- if (IA_CSS_PIPE_ID_COPY != pipe_id) {
+ if (pipe_id != IA_CSS_PIPE_ID_COPY) {
ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_OUTPUT_FRAME, thread_id, (enum sh_css_queue_id *)(&sh_css_sp_group.pipe[thread_id].output_frame_queue_id));
}
#endif
/* For the shading correction type 1 (the legacy shading table conversion in css is not used),
* the parameters are passed to the isp for the shading table centering.
*/
- if (internal_frame_origin_bqs_on_sctbl != NULL &&
- params != NULL && params->shading_settings.enable_shading_table_conversion == 0) {
+ if (internal_frame_origin_bqs_on_sctbl &&
+ params && params->shading_settings.enable_shading_table_conversion == 0) {
sh_css_sp_group.pipe[thread_id].shading.internal_frame_origin_x_bqs_on_sctbl
= (uint32_t)internal_frame_origin_bqs_on_sctbl->x;
sh_css_sp_group.pipe[thread_id].shading.internal_frame_origin_y_bqs_on_sctbl
sh_css_sp_group.pipe[thread_id].pipe_config |= (uint32_t)
(me->acquire_isp_each_stage << IA_CSS_ACQUIRE_ISP_POS);
store_sp_group_data();
-
}
void
sh_css_sp_uninit_pipeline(unsigned int pipe_num)
{
unsigned int thread_id;
+
ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id);
/*memset(&sh_css_sp_group.pipe[thread_id], 0, sizeof(struct sh_css_sp_pipeline));*/
sh_css_sp_group.pipe[thread_id].num_stages = 0;
return (enum host2sp_commands)load_sp_array_uint(host_sp_com, offset);
}
-
/*
* Frame data is no longer part of the sp_stage structure but part of a
* separate structure. The aim is to make the sp_data struct static
*/
}
-
/*
* @brief Update the offline frame information in host_sp_communication.
* Refer to "sh_css_sp.h" for more details.
*/
void
sh_css_update_host2sp_offline_frame(
- unsigned frame_num,
+ unsigned int frame_num,
struct ia_css_frame *frame,
struct ia_css_metadata *metadata)
{
*/
void
sh_css_update_host2sp_mipi_frame(
- unsigned frame_num,
+ unsigned int frame_num,
struct ia_css_frame *frame)
{
unsigned int HIVE_ADDR_host_sp_com;
*/
void
sh_css_update_host2sp_mipi_metadata(
- unsigned frame_num,
+ unsigned int frame_num,
struct ia_css_metadata *metadata)
{
unsigned int HIVE_ADDR_host_sp_com;
}
void
-sh_css_update_host2sp_num_mipi_frames(unsigned num_frames)
+sh_css_update_host2sp_num_mipi_frames(unsigned int num_frames)
{
unsigned int HIVE_ADDR_host_sp_com;
unsigned int offset;
#endif
void
-sh_css_update_host2sp_cont_num_raw_frames(unsigned num_frames, bool set_avail)
+sh_css_update_host2sp_cont_num_raw_frames(unsigned int num_frames, bool set_avail)
{
const struct ia_css_fw_info *fw;
unsigned int HIVE_ADDR_host_sp_com;
(unsigned int)sp_address_of(host_sp_com) + offset,
&event_irq_mask_init, sizeof(event_irq_mask_init));
}
-
}
enum ia_css_err
struct sh_css_event_irq_mask event_irq_mask;
unsigned int pipe_num;
- assert(pipe != NULL);
+ assert(pipe);
assert(IA_CSS_PIPE_ID_NUM == NR_OF_PIPELINES);
/* Linux kernel does not have UINT16_MAX
IA_CSS_ENTER_LEAVE("");
- assert(pipe != NULL);
+ assert(pipe);
assert(IA_CSS_PIPE_ID_NUM == NR_OF_PIPELINES);
pipe_num = ia_css_pipe_get_pipe_num(pipe);
fw = &sh_css_sp_fw;
HIVE_ADDR_sp_sw_state = fw->info.sp.sw_state;
-
if (sp_running)
return;
(unsigned int)sp_address_of(sp_sw_state),
(uint32_t)(IA_CSS_SP_SW_TERMINATED));
-
/* Note 1: The sp_start_isp function contains a wait till
* the input network is configured by the SP.
* Note 2: Not all SP binaries supports host2sp_commands.
mmu_invalidate_cache_all();
ia_css_spctrl_start(SP0_ID);
-
}
bool
return (bool)load_sp_uint(ia_css_ispctrl_sp_isp_started);
}
-
/*
* @brief Initialize the DMA software-mask in the debug mode.
* Refer to "sh_css_sp.h" for more details.
int request_type,
bool enable)
{
- uint32_t sw_reg;
- uint32_t bit_val;
- uint32_t bit_offset;
- uint32_t bit_mask;
+ u32 sw_reg;
+ u32 bit_val;
+ u32 bit_offset;
+ u32 bit_mask;
(void)dma_id;
sh_css_sp_store_init_dmem(const struct ia_css_fw_info *fw);
void
-store_sp_stage_data(enum ia_css_pipe_id id, unsigned int pipe_num, unsigned stage);
+store_sp_stage_data(enum ia_css_pipe_id id, unsigned int pipe_num, unsigned int stage);
void
sh_css_stage_write_binary_info(struct ia_css_binary_info *info);
/* Start binary (jpeg) copy on the SP */
void
sh_css_sp_start_binary_copy(unsigned int pipe_num, struct ia_css_frame *out_frame,
- unsigned two_ppc);
+ unsigned int two_ppc);
unsigned int
sh_css_sp_get_binary_copy_size(void);
void
sh_css_sp_init_pipeline(struct ia_css_pipeline *me,
enum ia_css_pipe_id id,
- uint8_t pipe_num,
+ u8 pipe_num,
bool xnr,
bool two_ppc,
bool continuous,
*/
void
sh_css_update_host2sp_offline_frame(
- unsigned frame_num,
+ unsigned int frame_num,
struct ia_css_frame *frame,
struct ia_css_metadata *metadata);
*/
void
sh_css_update_host2sp_mipi_frame(
- unsigned frame_num,
+ unsigned int frame_num,
struct ia_css_frame *frame);
/**
*/
void
sh_css_update_host2sp_mipi_metadata(
- unsigned frame_num,
+ unsigned int frame_num,
struct ia_css_metadata *metadata);
/**
* @param[in] num_frames The number of mipi frames to use.
*/
void
-sh_css_update_host2sp_num_mipi_frames(unsigned num_frames);
+sh_css_update_host2sp_num_mipi_frames(unsigned int num_frames);
#endif
/**
* @param[in] num_frames The number of raw frames to use.
*/
void
-sh_css_update_host2sp_cont_num_raw_frames(unsigned num_frames, bool set_avail);
+sh_css_update_host2sp_cont_num_raw_frames(unsigned int num_frames, bool set_avail);
void
sh_css_event_init_irq_mask(void);
int request_type,
bool enable);
-
extern struct sh_css_sp_group sh_css_sp_group;
extern struct sh_css_sp_stage sh_css_sp_stage;
extern struct sh_css_isp_stage sh_css_isp_stage;
unsigned int size_mem_words; /* \deprecated{Use ia_css_mipi_buffer_config instead.}*/
enum ia_css_irq_type irq_type;
unsigned int pipe_counter;
-
+
unsigned int type; /* 2400 or 2401 for now */
};
extern struct sh_css my_css;
#endif /* __SH_CSS_STRUCT_H */
-
/* Uds types, used in pipeline_global.h and sh_css_internal.h */
struct sh_css_uds_info {
- uint16_t curr_dx;
- uint16_t curr_dy;
- uint16_t xc;
- uint16_t yc;
+ u16 curr_dx;
+ u16 curr_dy;
+ u16 xc;
+ u16 yc;
};
struct sh_css_crop_pos {
- uint16_t x;
- uint16_t y;
+ u16 x;
+ u16 y;
};
#endif /* _SH_CSS_UDS_H_ */
{
hmm_mem_stat.res_size = res_pgnr;
/* If reserved mem pool is not enabled, set its "mem stat" values as -1. */
- if (0 == hmm_mem_stat.res_size) {
+ if (hmm_mem_stat.res_size == 0) {
hmm_mem_stat.res_size = -1;
hmm_mem_stat.res_cnt = -1;
}
this = rb_entry(node, struct hmm_buffer_object, node);
if (this->pgnr == pgnr ||
- (this->pgnr > pgnr && this->node.rb_left == NULL)) {
+ (this->pgnr > pgnr && !this->node.rb_left)) {
goto remove_bo_and_return;
} else {
if (this->pgnr < pgnr) {
* 1. check if 'this->next' is NULL:
* yes: erase 'this' node and rebalance rbtree, return 'this'.
*/
- if (this->next == NULL) {
+ if (!this->next) {
rb_erase(&this->node, &this->bdev->free_rbtree);
return this;
}
bo = rb_entry(n, struct hmm_buffer_object, node);
if (bo->start > start) {
- if (n->rb_left == NULL)
+ if (!n->rb_left)
return NULL;
n = n->rb_left;
} else if (bo->start < start) {
- if (n->rb_right == NULL)
+ if (!n->rb_right)
return NULL;
n = n->rb_right;
} else {
bo = rb_entry(n, struct hmm_buffer_object, node);
if (bo->start > start) {
- if (n->rb_left == NULL)
+ if (!n->rb_left)
return NULL;
n = n->rb_left;
} else {
if (bo->end > start)
return bo;
- if (n->rb_right == NULL)
+ if (!n->rb_right)
return NULL;
n = n->rb_right;
}
static void __bo_insert_to_free_rbtree(struct rb_root *root,
struct hmm_buffer_object *bo)
{
- struct rb_node **new = &(root->rb_node);
+ struct rb_node **new = &root->rb_node;
struct rb_node *parent = NULL;
struct hmm_buffer_object *this;
unsigned int pgnr = bo->pgnr;
static void __bo_insert_to_alloc_rbtree(struct rb_root *root,
struct hmm_buffer_object *bo)
{
- struct rb_node **new = &(root->rb_node);
+ struct rb_node **new = &root->rb_node;
struct rb_node *parent = NULL;
struct hmm_buffer_object *this;
unsigned int start = bo->start;
* and does not have a linked list after bo, to take off this bo,
* we just need erase bo directly and rebalance the free rbtree
*/
- if (bo->prev == NULL && bo->next == NULL) {
+ if (!bo->prev && !bo->next) {
rb_erase(&bo->node, &bdev->free_rbtree);
/* 2. when bo->next != NULL && bo->prev == NULL, bo is a rbtree node,
* and has a linked list,to take off this bo we need erase bo
* first, then, insert bo->next into free rbtree and rebalance
* the free rbtree
*/
- } else if (bo->prev == NULL && bo->next != NULL) {
+ } else if (!bo->prev && bo->next) {
bo->next->prev = NULL;
rb_erase(&bo->node, &bdev->free_rbtree);
__bo_insert_to_free_rbtree(&bdev->free_rbtree, bo->next);
* node, to take off this bo, we just need set the "prev/next"
* pointers to NULL, the free rbtree stays unchaged
*/
- } else if (bo->prev != NULL && bo->next == NULL) {
+ } else if (bo->prev && !bo->next) {
bo->prev->next = NULL;
bo->prev = NULL;
/* 4. when bo->prev != NULL && bo->next != NULL ,bo is not a rbtree
* to take off this bo, we just set take the "prev/next" pointers
* to NULL, the free rbtree stays unchaged
*/
- } else if (bo->prev != NULL && bo->next != NULL) {
+ } else if (bo->prev && bo->next) {
bo->next->prev = bo->prev;
bo->prev->next = bo->next;
bo->next = NULL;
found:
spin_unlock_irqrestore(&bdev->list_lock, flags);
return bo;
-
}
-
static void free_private_bo_pages(struct hmm_buffer_object *bo,
struct hmm_pool *dypool,
struct hmm_pool *repool,
ret = set_pages_uc(pages, blk_pgnr);
if (ret) {
dev_err(atomisp_dev,
- "set page uncacheable"
- "failed.\n");
+ "set page uncacheablefailed.\n");
__free_pages(pages, order);
down_read(¤t->mm->mmap_sem);
vma = find_vma(current->mm, (unsigned long)userptr);
up_read(¤t->mm->mmap_sem);
- if (vma == NULL) {
+ if (!vma) {
dev_err(atomisp_dev, "find_vma failed\n");
kfree(bo->page_obj);
kfree(pages);
/* can be written by caller, not forced */
if (page_nr != bo->pgnr) {
dev_err(atomisp_dev,
- "get_user_pages err: bo->pgnr = %d, "
- "pgnr actually pinned = %d.\n",
+ "get_user_pages err: bo->pgnr = %d, pgnr actually pinned = %d.\n",
bo->pgnr, page_nr);
goto out_of_mem;
}
*/
if ((start + pgnr_to_size(pgnr)) != end) {
dev_warn(atomisp_dev,
- "vma's address space size not equal"
- " to buffer object's size");
+ "vma's address space size not equal to buffer object's size");
return -EINVAL;
}
pfn = page_to_pfn(bo->page_obj[i].page);
if (remap_pfn_range(vma, virt, pfn, PAGE_SIZE, PAGE_SHARED)) {
dev_warn(atomisp_dev,
- "remap_pfn_range failed:"
- " virt = 0x%x, pfn = 0x%x,"
- " mapped_pgnr = %d\n", virt, pfn, 1);
+ "remap_pfn_range failed: virt = 0x%x, pfn = 0x%x, mapped_pgnr = %d\n",
+ virt, pfn, 1);
return -EINVAL;
}
virt += PAGE_SIZE;
vma->vm_private_data = bo;
vma->vm_ops = &hmm_bo_vm_ops;
- vma->vm_flags |= VM_IO|VM_DONTEXPAND|VM_DONTDUMP;
+ vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP;
/*
* call hmm_bo_vm_open explicitly.
if (repool_info->initialized) {
repool_pgnr = repool_info->index;
- for (j = repool_pgnr-1; j >= 0; j--) {
+ for (j = repool_pgnr - 1; j >= 0; j--) {
page_obj[i].page = repool_info->pages[j];
page_obj[i].type = HMM_PAGE_TYPE_RESERVED;
i++;
struct page *pages;
int j;
struct hmm_reserved_pool_info *repool_info;
+
if (pool_size == 0)
return 0;
*pool = repool_info;
dev_info(atomisp_dev,
- "hmm_reserved_pool init successfully,"
- "hmm_reserved_pool is with %d pages.\n",
+ "hmm_reserved_pool init successfully,hmm_reserved_pool is with %d pages.\n",
repool_info->pgnr);
return 0;
}
vm->cache = kmem_cache_create("atomisp_vm", sizeof(struct hmm_vm_node),
0, 0, NULL);
- return vm->cache != NULL ? 0 : -ENOMEM;
+ return vm->cache ? 0 : -ENOMEM;
}
void hmm_vm_clean(struct hmm_vm *vm)
udelay(1);
}
-static inline uint32_t _hrt_mem_store(uint32_t to, const void *from, size_t n)
+static inline u32 _hrt_mem_store(u32 to, const void *from, size_t n)
{
- unsigned i;
- uint32_t _to = to;
+ unsigned int i;
+ u32 _to = to;
const char *_from = (const char *)from;
+
for (i = 0; i < n; i++, _to++, _from++)
_hrt_master_port_store_8(_to, *_from);
return _to;
}
-static inline void *_hrt_mem_load(uint32_t from, void *to, size_t n)
+static inline void *_hrt_mem_load(u32 from, void *to, size_t n)
{
- unsigned i;
+ unsigned int i;
char *_to = (char *)to;
- uint32_t _from = from;
+ u32 _from = from;
+
for (i = 0; i < n; i++, _to++, _from++)
*_to = _hrt_master_port_load_8(_from);
return _to;
}
-static inline uint32_t _hrt_mem_set(uint32_t to, int c, size_t n)
+static inline u32 _hrt_mem_set(u32 to, int c, size_t n)
{
- unsigned i;
- uint32_t _to = to;
+ unsigned int i;
+ u32 _to = to;
+
for (i = 0; i < n; i++, _to++)
_hrt_master_port_store_8(_to, c);
return _to;
#include "hive_isp_css_mm_hrt.h"
#include "hmm/hmm.h"
-#define __page_align(size) (((size) + (PAGE_SIZE-1)) & (~(PAGE_SIZE-1)))
+#define __page_align(size) (((size) + (PAGE_SIZE - 1)) & (~(PAGE_SIZE - 1)))
static void __user *my_userptr;
-static unsigned my_num_pages;
+static unsigned int my_num_pages;
static enum hrt_userptr_type my_usr_type;
void hrt_isp_css_mm_set_user_ptr(void __user *userptr,
#endif
if (type == HRT_USR_PTR) {
- if (userptr == NULL)
+ if (!userptr)
return hmm_alloc(bytes, HMM_BO_PRIVATE, 0,
NULL, cached);
else {
if (num_pages < ((__page_align(bytes)) >> PAGE_SHIFT))
dev_err(atomisp_dev,
- "user space memory size is less"
- " than the expected size..\n");
+ "user space memory size is less than the expected size..\n");
else if (num_pages > ((__page_align(bytes))
>> PAGE_SHIFT))
dev_err(atomisp_dev,
- "user space memory size is"
- " large than the expected size..\n");
+ "user space memory size is large than the expected size..\n");
return hmm_alloc(bytes, HMM_BO_USER, 0,
userptr, cached);
ia_css_ptr hrt_isp_css_mm_alloc_cached(size_t bytes)
{
- if (my_userptr == NULL)
+ if (!my_userptr)
return hmm_alloc(bytes, HMM_BO_PRIVATE, 0, NULL,
HMM_CACHED);
else {
if (my_num_pages < ((__page_align(bytes)) >> PAGE_SHIFT))
dev_err(atomisp_dev,
- "user space memory size is less"
- " than the expected size..\n");
+ "user space memory size is less than the expected size..\n");
else if (my_num_pages > ((__page_align(bytes)) >> PAGE_SHIFT))
dev_err(atomisp_dev,
- "user space memory size is"
- " large than the expected size..\n");
+ "user space memory size is large than the expected size..\n");
return hmm_alloc(bytes, HMM_BO_USER, 0,
my_userptr, HMM_CACHED);
ia_css_ptr hrt_isp_css_mm_calloc(size_t bytes)
{
ia_css_ptr ptr = hrt_isp_css_mm_alloc(bytes);
+
if (ptr)
hmm_set(ptr, 0, bytes);
return ptr;
ia_css_ptr hrt_isp_css_mm_calloc_cached(size_t bytes)
{
ia_css_ptr ptr = hrt_isp_css_mm_alloc_cached(bytes);
+
if (ptr)
hmm_set(ptr, 0, bytes);
return ptr;
}
-
#include <hmm/hmm.h>
#include <hrt/hive_isp_css_custom_host_hrt.h>
-#define HRT_BUF_FLAG_CACHED (1 << 0)
+#define HRT_BUF_FLAG_CACHED BIT(0)
enum hrt_userptr_type {
HRT_USR_PTR = 0,
*/
void hmm_bo_unref(struct hmm_buffer_object *bo);
-
/*
* allocate/free physical pages for the bo. will try to alloc mem
* from highmem if from_highmem is set, and type indicate that the
* or by ISP driver itself.
*/
-
int hmm_bo_allocated(struct hmm_buffer_object *bo);
-
/*
* allocate/free physical pages for the bo. will try to alloc mem
* from highmem if from_highmem is set, and type indicate that the
struct hmm_buffer_object *hmm_bo_device_search_vmap_start(
struct hmm_bo_device *bdev, const void *vaddr);
-
#endif
unsigned int size;
struct hmm_vm *vm;
};
+
#define ISP_VM_START 0x0
#define ISP_VM_SIZE (0x7FFFFFFF) /* 2G address space */
#define ISP_PTR_NULL NULL
* same as kernel's page size.
*/
#define ISP_PAGE_OFFSET 12
-#define ISP_PAGE_SIZE (1U << ISP_PAGE_OFFSET)
+#define ISP_PAGE_SIZE BIT(ISP_PAGE_OFFSET)
#define ISP_PAGE_MASK (~(phys_addr_t)(ISP_PAGE_SIZE - 1))
#define ISP_L1PT_OFFSET 22
#define ISP_L1PT_MASK (~((1U << ISP_L1PT_OFFSET) - 1))
#define ISP_L2PT_OFFSET 12
-#define ISP_L2PT_MASK (~(ISP_L1PT_MASK|(~(ISP_PAGE_MASK))))
+#define ISP_L2PT_MASK (~(ISP_L1PT_MASK | (~(ISP_PAGE_MASK))))
#define ISP_L1PT_PTES 1024
#define ISP_L2PT_PTES 1024
#define ISP_PTR_TO_L2_IDX(x) ((((x) & ISP_L2PT_MASK)) \
>> ISP_L2PT_OFFSET)
-#define ISP_PAGE_ALIGN(x) (((x) + (ISP_PAGE_SIZE-1)) \
+#define ISP_PAGE_ALIGN(x) (((x) + (ISP_PAGE_SIZE - 1)) \
& ISP_PAGE_MASK)
#define ISP_PT_TO_VIRT(l1_idx, l2_idx, offset) do {\
*
* must be provided.
*/
- unsigned int (*get_pd_base) (struct isp_mmu *mmu, phys_addr_t pd_base);
+ unsigned int (*get_pd_base)(struct isp_mmu *mmu, phys_addr_t pd_base);
/*
* callback to flush tlb.
*
* tlb_flush_all is must be provided. if tlb_flush_range is
* not valid, it will set to tlb_flush_all by default.
*/
- void (*tlb_flush_range) (struct isp_mmu *mmu,
+ void (*tlb_flush_range)(struct isp_mmu *mmu,
unsigned int addr, unsigned int size);
- void (*tlb_flush_all) (struct isp_mmu *mmu);
- unsigned int (*phys_to_pte) (struct isp_mmu *mmu,
+ void (*tlb_flush_all)(struct isp_mmu *mmu);
+ unsigned int (*phys_to_pte)(struct isp_mmu *mmu,
phys_addr_t phys);
- phys_addr_t (*pte_to_phys) (struct isp_mmu *mmu,
+ phys_addr_t (*pte_to_phys)(struct isp_mmu *mmu,
unsigned int pte);
};
static unsigned int atomisp_get_pte(phys_addr_t pt, unsigned int idx)
{
unsigned int *pt_virt = phys_to_virt(pt);
+
return *(pt_virt + idx);
}
phys_addr_t phys)
{
unsigned int pte = mmu->driver->phys_to_pte(mmu, phys);
- return (unsigned int) (pte | ISP_PTE_VALID_MASK(mmu));
+
+ return (unsigned int)(pte | ISP_PTE_VALID_MASK(mmu));
}
/*
static void free_page_table(struct isp_mmu *mmu, phys_addr_t page)
{
void *virt;
+
page &= ISP_PAGE_MASK;
/*
* reset the page to write back before free
phys_addr_t new_phys)
{
dev_err(atomisp_dev, "address remap:\n\n"
- "\tL1 PT: virt = %p, phys = 0x%llx, "
- "idx = %d\n"
- "\tL2 PT: virt = %p, phys = 0x%llx, "
- "idx = %d\n"
+ "\tL1 PT: virt = %p, phys = 0x%llx, idx = %d\n"
+ "\tL2 PT: virt = %p, phys = 0x%llx, idx = %d\n"
"\told: isp_virt = 0x%x, phys = 0x%llx\n"
"\tnew: isp_virt = 0x%x, phys = 0x%llx\n",
isp_pt_phys_to_virt(l1_pt),
unsigned int isp_virt, unsigned int pte)
{
dev_err(atomisp_dev, "unmap invalid L2 pte:\n\n"
- "\tL1 PT: virt = %p, phys = 0x%llx, "
- "idx = %d\n"
- "\tL2 PT: virt = %p, phys = 0x%llx, "
- "idx = %d\n"
+ "\tL1 PT: virt = %p, phys = 0x%llx, idx = %d\n"
+ "\tL2 PT: virt = %p, phys = 0x%llx, idx = %d\n"
"\tisp_virt = 0x%x, pte(page phys) = 0x%x\n",
isp_pt_phys_to_virt(l1_pt),
(u64)l1_pt, l1_idx,
unsigned int isp_virt, unsigned int pte)
{
dev_err(atomisp_dev, "unmap invalid L1 pte (L2 PT):\n\n"
- "\tL1 PT: virt = %p, phys = 0x%llx, "
- "idx = %d\n"
+ "\tL1 PT: virt = %p, phys = 0x%llx, idx = %d\n"
"\tisp_virt = 0x%x, l1_pte(L2 PT) = 0x%x\n",
isp_pt_phys_to_virt(l1_pt),
(u64)l1_pt, l1_idx, (unsigned int)isp_virt,
unsigned int l1_idx, phys_addr_t l2_pt,
unsigned int start, unsigned int end)
{
-
unsigned int ptr;
unsigned int idx;
unsigned int pte;
unsigned int pte)
{
unsigned int mask = mmu->driver->pte_valid_mask;
+
return (phys_addr_t)((pte & ~mask) << ISP_PAGE_OFFSET);
}
phys_addr_t phys)
{
unsigned int pte = sh_phys_to_pte(mmu, phys);
+
return HOST_ADDRESS(pte);
}
struct gmin_subdev *gs = find_gmin_subdev(subdev);
struct camera_vcm_control *vcm;
- if (client == NULL || gs == NULL)
+ if (!client || !gs)
return NULL;
if (!camera_module)
projects / linux.git / commitdiff