crypto: qat - allow detection of dc capabilities for 4xxx

Add logic to allow the detection of data compression capabilities for
4xxx devices.
The capability detection logic has been refactored to separate the
crypto capabilities from the compression ones.

This patch is not updating the returned capability mask as, up to now,
4xxx devices are configured only to handle crypto operations.

Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>
Reviewed-by: Fiona Trahe <fiona.trahe@intel.com>
Reviewed-by: Marco Chiappero <marco.chiappero@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c b/drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c
index ef71aa4efd646c7a406f32a2bb42f7dd481088ef..40f684103b2930d85b423f3003022039be70818a 100644 (file)
--- a/drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c
+++ b/drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c
@@ -96,46 +96,60 @@ static void set_msix_default_rttable(struct adf_accel_dev *accel_dev)
 static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
 {
        struct pci_dev *pdev = accel_dev->accel_pci_dev.pci_dev;
+       u32 capabilities_cy, capabilities_dc;
        u32 fusectl1;
-       u32 capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
-                          ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
-                          ICP_ACCEL_CAPABILITIES_CIPHER |
-                          ICP_ACCEL_CAPABILITIES_AUTHENTICATION |
-                          ICP_ACCEL_CAPABILITIES_SHA3 |
-                          ICP_ACCEL_CAPABILITIES_SHA3_EXT |
-                          ICP_ACCEL_CAPABILITIES_HKDF |
-                          ICP_ACCEL_CAPABILITIES_ECEDMONT |
-                          ICP_ACCEL_CAPABILITIES_CHACHA_POLY |
-                          ICP_ACCEL_CAPABILITIES_AESGCM_SPC |
-                          ICP_ACCEL_CAPABILITIES_AES_V2;
 
        /* Read accelerator capabilities mask */
        pci_read_config_dword(pdev, ADF_4XXX_FUSECTL1_OFFSET, &fusectl1);
 
+       capabilities_cy = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
+                         ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
+                         ICP_ACCEL_CAPABILITIES_CIPHER |
+                         ICP_ACCEL_CAPABILITIES_AUTHENTICATION |
+                         ICP_ACCEL_CAPABILITIES_SHA3 |
+                         ICP_ACCEL_CAPABILITIES_SHA3_EXT |
+                         ICP_ACCEL_CAPABILITIES_HKDF |
+                         ICP_ACCEL_CAPABILITIES_ECEDMONT |
+                         ICP_ACCEL_CAPABILITIES_CHACHA_POLY |
+                         ICP_ACCEL_CAPABILITIES_AESGCM_SPC |
+                         ICP_ACCEL_CAPABILITIES_AES_V2;
+
        /* A set bit in fusectl1 means the feature is OFF in this SKU */
        if (fusectl1 & ICP_ACCEL_4XXX_MASK_CIPHER_SLICE) {
-               capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
-               capabilities &= ~ICP_ACCEL_CAPABILITIES_HKDF;
-               capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
+               capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
+               capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_HKDF;
+               capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
        }
        if (fusectl1 & ICP_ACCEL_4XXX_MASK_UCS_SLICE) {
-               capabilities &= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY;
-               capabilities &= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC;
-               capabilities &= ~ICP_ACCEL_CAPABILITIES_AES_V2;
-               capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
+               capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY;
+               capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC;
+               capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_AES_V2;
+               capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
        }
        if (fusectl1 & ICP_ACCEL_4XXX_MASK_AUTH_SLICE) {
-               capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
-               capabilities &= ~ICP_ACCEL_CAPABILITIES_SHA3;
-               capabilities &= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT;
-               capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
+               capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
+               capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_SHA3;
+               capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT;
+               capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
        }
        if (fusectl1 & ICP_ACCEL_4XXX_MASK_PKE_SLICE) {
-               capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
-               capabilities &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;
+               capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
+               capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;
+       }
+
+       capabilities_dc = ICP_ACCEL_CAPABILITIES_COMPRESSION |
+                         ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION |
+                         ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION |
+                         ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
+
+       if (fusectl1 & ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE) {
+               capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
+               capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION;
+               capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION;
+               capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
        }
 
-       return capabilities;
+       return capabilities_cy;
 }
 
 static enum dev_sku_info get_sku(struct adf_hw_device_data *self)

diff --git a/drivers/crypto/qat/qat_common/icp_qat_hw.h b/drivers/crypto/qat/qat_common/icp_qat_hw.h
index 5770b2b2c09e5de24c54668b7fc037ce426bb109..433304cad2edf22a0a6f8c954e798e949b964f2b 100644 (file)
--- a/drivers/crypto/qat/qat_common/icp_qat_hw.h
+++ b/drivers/crypto/qat/qat_common/icp_qat_hw.h
@@ -98,7 +98,11 @@ enum icp_qat_capabilities_mask {
        ICP_ACCEL_CAPABILITIES_SHA3_EXT = BIT(15),
        ICP_ACCEL_CAPABILITIES_AESGCM_SPC = BIT(16),
        ICP_ACCEL_CAPABILITIES_CHACHA_POLY = BIT(17),
-       /* Bits 18-25 are currently reserved */
+       /* Bits 18-21 are currently reserved */
+       ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY = BIT(22),
+       ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64 = BIT(23),
+       ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION = BIT(24),
+       ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION = BIT(25),
        ICP_ACCEL_CAPABILITIES_AES_V2 = BIT(26)
 };