clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()

The bitmask << 16 is anyway set on both branches of if thus move it
before the if and set the lower bits of registers only in case clock is
enabled.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230912045157.177966-12-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index a1e820d2eb9e070e7d8feb015ca845bfbd786b92..115e19823b700dbac35d837de291ce3b42fe710d 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -909,10 +909,9 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
                enable ? "ON" : "OFF");
        spin_lock_irqsave(&priv->rmw_lock, flags);
 
+       value = bitmask << 16;
        if (enable)
-               value = (bitmask << 16) | bitmask;
-       else
-               value = bitmask << 16;
+               value |= bitmask;
        writel(value, priv->base + CLK_ON_R(reg));
 
        spin_unlock_irqrestore(&priv->rmw_lock, flags);