u8 has_flat_ccs:1;
/** @has_4tile: Whether tile-4 tiling is supported */
u8 has_4tile:1;
+ /** @has_llc: Device has a shared CPU+GPU last level cache */
+ u8 has_llc:1;
/** @has_range_tlb_invalidation: Has range based TLB invalidations */
u8 has_range_tlb_invalidation:1;
/** @has_link_copy_engines: Whether the platform has link copy engines */
* should eventually move entirely into the display code's own logic.
*/
u8 has_4tile:1;
+ u8 has_llc:1;
};
#define PLATFORM(x) \
.graphics = &graphics_xelp,
.media = &media_xem,
PLATFORM(XE_TIGERLAKE),
+ .has_llc = 1,
.require_force_probe = true,
};
.graphics = &graphics_xelp,
.media = &media_xem,
PLATFORM(XE_ALDERLAKE_S),
+ .has_llc = 1,
.require_force_probe = true,
};
.graphics = &graphics_xelp,
.media = &media_xem,
PLATFORM(XE_ALDERLAKE_P),
+ .has_llc = 1,
.require_force_probe = true,
.subplatforms = (const struct xe_subplatform_desc[]) {
{ XE_SUBPLATFORM_ADLP_RPLU, "RPLU", adlp_rplu_ids },
xe->info.graphics_name = graphics_desc->name;
xe->info.media_name = media_desc ? media_desc->name : "none";
xe->info.has_4tile = desc->has_4tile;
+ xe->info.has_llc = desc->has_llc;
xe->info.dma_mask_size = graphics_desc->dma_mask_size;
xe->info.vram_flags = graphics_desc->vram_flags;