arm64: dts: qcom: sm8450: add i2c13 and i2c14 device nodes

Add device tree nodes for two i2c blocks: i2c13 and i2c14.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211215043440.605624-12-vkoul@kernel.org

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 56e3e8f771bdeacab6640f54526243464d552282..62082ed5335dd8295f16c61725f5e0c59a18d9a1 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -582,6 +582,44 @@
                        };
                };
 
+               qupv3_id_1: geniqup@ac0000 {
+                       compatible = "qcom,geni-se-qup";
+                       reg = <0x0 0x00ac0000 0x0 0x6000>;
+                       clock-names = "m-ahb", "s-ahb";
+                       clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+                                <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+                       status = "disabled";
+
+                       i2c13: i2c@a94000 {
+                               compatible = "qcom,geni-i2c";
+                               reg = <0 0x00a94000 0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&qup_i2c13_data_clk>;
+                               interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       i2c14: i2c@a98000 {
+                               compatible = "qcom,geni-i2c";
+                               reg = <0 0x00a98000 0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&qup_i2c14_data_clk>;
+                               interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+               };
+
                tcsr_mutex: hwlock@1f40000 {
                        compatible = "qcom,tcsr-mutex";
                        reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -609,6 +647,20 @@
                        gpio-ranges = <&tlmm 0 0 211>;
                        wakeup-parent = <&pdc>;
 
+                       qup_i2c13_data_clk: qup-i2c13-data-clk {
+                               pins = "gpio48", "gpio49";
+                               function = "qup13";
+                               drive-strength = <2>;
+                               bias-pull-up;
+                       };
+
+                       qup_i2c14_data_clk: qup-i2c14-data-clk {
+                               pins = "gpio52", "gpio53";
+                               function = "qup14";
+                               drive-strength = <2>;
+                               bias-pull-up;
+                       };
+
                        qup_uart7_rx: qup-uart7-rx {
                                pins = "gpio26";
                                function = "qup7";