target-ppc: Explain why the whole TLB is flushed on SR write

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6947 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 80b53ebcbab35cfade2b2db67daf6ae971c2b568..a0d884ee1e6108945a26dff61c721d22f3f712a5 100644 (file)
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -2009,6 +2009,8 @@ void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value)
 #endif
     if (env->sr[srnum] != value) {
         env->sr[srnum] = value;
+/* Invalidating 256MB of virtual memory in 4kB pages is way longer than
+   flusing the whole TLB. */
 #if !defined(FLUSH_ALL_TLBS) && 0
         {
             target_ulong page, end;