phy: qcom-qmp-pcie: populate offsets configuration

Populate offsets configuration for the rest of UFS PHYs to make it
possible to switch them to the new (single-node) bindings style.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-7-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 84a14bffc891f4e3cc2ce3e0c851cfe02101bafe..565764c5ffeb7a01e81874e0dc9b91182f202a73 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -2294,6 +2294,56 @@ static const char * const sdm845_pciephy_reset_l[] = {
        "phy",
 };
 
+static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp = {
+       .serdes         = 0,
+       .pcs            = 0x1800,
+       .tx             = 0x0800,
+       /* no .rx for QHP */
+};
+
+static const struct qmp_pcie_offsets qmp_pcie_offsets_v2 = {
+       .serdes         = 0,
+       .pcs            = 0x0800,
+       .tx             = 0x0200,
+       .rx             = 0x0400,
+};
+
+static const struct qmp_pcie_offsets qmp_pcie_offsets_v3 = {
+       .serdes         = 0,
+       .pcs            = 0x0800,
+       .pcs_misc       = 0x0600,
+       .tx             = 0x0200,
+       .rx             = 0x0400,
+};
+
+static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = {
+       .serdes         = 0,
+       .pcs            = 0x0800,
+       .pcs_misc       = 0x0c00,
+       .tx             = 0x0200,
+       .rx             = 0x0400,
+};
+
+static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = {
+       .serdes         = 0,
+       .pcs            = 0x0a00,
+       .pcs_misc       = 0x0e00,
+       .tx             = 0x0200,
+       .rx             = 0x0400,
+       .tx2            = 0x0600,
+       .rx2            = 0x0800,
+};
+
+static const struct qmp_pcie_offsets qmp_pcie_offsets_v4_20 = {
+       .serdes         = 0x1000,
+       .pcs            = 0x1200,
+       .pcs_misc       = 0x1600,
+       .tx             = 0x0000,
+       .rx             = 0x0200,
+       .tx2            = 0x0800,
+       .rx2            = 0x0a00,
+};
+
 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = {
        .serdes         = 0,
        .pcs            = 0x0200,
@@ -2338,6 +2388,8 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = {
 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
        .lanes                  = 1,
 
+       .offsets                = &qmp_pcie_offsets_v2,
+
        .tbls = {
                .serdes         = ipq8074_pcie_serdes_tbl,
                .serdes_num     = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
@@ -2361,6 +2413,8 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
        .lanes                  = 1,
 
+       .offsets                = &qmp_pcie_offsets_v4x1,
+
        .tbls = {
                .serdes         = ipq8074_pcie_gen3_serdes_tbl,
                .serdes_num     = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
@@ -2388,6 +2442,8 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
        .lanes                  = 1,
 
+       .offsets                = &qmp_pcie_offsets_v4x1,
+
        .tbls = {
                .serdes         = ipq6018_pcie_serdes_tbl,
                .serdes_num     = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
@@ -2413,6 +2469,8 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
        .lanes                  = 1,
 
+       .offsets                = &qmp_pcie_offsets_v3,
+
        .tbls = {
                .serdes         = sdm845_qmp_pcie_serdes_tbl,
                .serdes_num     = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
@@ -2438,6 +2496,8 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
        .lanes                  = 1,
 
+       .offsets                = &qmp_pcie_offsets_qhp,
+
        .tbls = {
                .serdes         = sdm845_qhp_pcie_serdes_tbl,
                .serdes_num     = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
@@ -2459,6 +2519,8 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
        .lanes                  = 1,
 
+       .offsets                = &qmp_pcie_offsets_v4x1,
+
        .tbls = {
                .serdes         = sm8250_qmp_pcie_serdes_tbl,
                .serdes_num     = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
@@ -2494,6 +2556,8 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
        .lanes                  = 2,
 
+       .offsets                = &qmp_pcie_offsets_v4x2,
+
        .tbls = {
                .serdes         = sm8250_qmp_pcie_serdes_tbl,
                .serdes_num     = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
@@ -2529,6 +2593,8 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
 static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
        .lanes                  = 1,
 
+       .offsets                = &qmp_pcie_offsets_v3,
+
        .tbls = {
                .serdes         = msm8998_pcie_serdes_tbl,
                .serdes_num     = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
@@ -2554,6 +2620,8 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
        .lanes                  = 2,
 
+       .offsets                = &qmp_pcie_offsets_v4x2,
+
        .tbls = {
                .serdes         = sc8180x_qmp_pcie_serdes_tbl,
                .serdes_num     = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
@@ -2681,6 +2749,8 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = {
 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
        .lanes                  = 2,
 
+       .offsets                = &qmp_pcie_offsets_v4_20,
+
        .tbls = {
                .serdes         = sdx55_qmp_pcie_serdes_tbl,
                .serdes_num     = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
@@ -2818,6 +2888,8 @@ static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = {
 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
        .lanes                  = 1,
 
+       .offsets                = &qmp_pcie_offsets_v5,
+
        .tbls = {
                .serdes         = sm8450_qmp_gen3_pcie_serdes_tbl,
                .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
@@ -2851,6 +2923,8 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
        .lanes                  = 2,
 
+       .offsets                = &qmp_pcie_offsets_v5_20,
+
        .tbls = {
                .serdes         = sm8450_qmp_gen4x2_pcie_serdes_tbl,
                .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),