#define OV13858_ANA_GAIN_DEFAULT       0x80
 
 /* Digital gain control */
-#define OV13858_REG_DIGITAL_GAIN       0x350a
-#define OV13858_DGTL_GAIN_MASK         0xf3
-#define OV13858_DGTL_GAIN_SHIFT                2
-#define OV13858_DGTL_GAIN_MIN          1
-#define OV13858_DGTL_GAIN_MAX          4
-#define OV13858_DGTL_GAIN_STEP         1
-#define OV13858_DGTL_GAIN_DEFAULT      1
+#define OV13858_REG_B_MWB_GAIN         0x5100
+#define OV13858_REG_G_MWB_GAIN         0x5102
+#define OV13858_REG_R_MWB_GAIN         0x5104
+#define OV13858_DGTL_GAIN_MIN          0
+#define OV13858_DGTL_GAIN_MAX          16384   /* Max = 16 X */
+#define OV13858_DGTL_GAIN_DEFAULT      1024    /* Default gain = 1 X */
+#define OV13858_DGTL_GAIN_STEP         1       /* Each step = 1/1024 */
 
 /* Test Pattern Control */
 #define OV13858_REG_TEST_PATTERN       0x4503
 static int ov13858_update_digital_gain(struct ov13858 *ov13858, u32 d_gain)
 {
        int ret;
-       u32 val;
 
-       if (d_gain == 3)
-               return -EINVAL;
+       ret = ov13858_write_reg(ov13858, OV13858_REG_B_MWB_GAIN,
+                               OV13858_REG_VALUE_16BIT, d_gain);
+       if (ret)
+               return ret;
 
-       ret = ov13858_read_reg(ov13858, OV13858_REG_DIGITAL_GAIN,
-                              OV13858_REG_VALUE_08BIT, &val);
+       ret = ov13858_write_reg(ov13858, OV13858_REG_G_MWB_GAIN,
+                               OV13858_REG_VALUE_16BIT, d_gain);
        if (ret)
                return ret;
 
-       val &= OV13858_DGTL_GAIN_MASK;
-       val |= (d_gain - 1) << OV13858_DGTL_GAIN_SHIFT;
+       ret = ov13858_write_reg(ov13858, OV13858_REG_R_MWB_GAIN,
+                               OV13858_REG_VALUE_16BIT, d_gain);
 
-       return ov13858_write_reg(ov13858, OV13858_REG_DIGITAL_GAIN,
-                                OV13858_REG_VALUE_08BIT, val);
+       return ret;
 }
 
 static int ov13858_enable_test_pattern(struct ov13858 *ov13858, u32 pattern)