riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Fri, 29 Sep 2023 00:07:02 +0000 (01:07 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 5 Oct 2023 12:25:00 +0000 (14:25 +0200)
Now that noncoherent dma support for the RZ/Five SoC has been added, enable
the IP blocks which were disabled on the RZ/Five SMARC.  This adds
support for the below peripherals:
  * Ethernet
  * DMAC
  * SDHI
  * USB
  * RSPI
  * SSI

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929000704.53217-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi

index c62debc7ca7e4fdd8a9e89b7bc602b68e2ec9bc2..433ab5c6a626c30fe4d5c751d427629fbfbd87b9 100644 (file)
@@ -7,25 +7,8 @@
 
 #include <arm64/renesas/rzg2ul-smarc-som.dtsi>
 
-/ {
-       aliases {
-               /delete-property/ ethernet0;
-               /delete-property/ ethernet1;
-       };
-
-       chosen {
-               bootargs = "ignore_loglevel";
-       };
-};
-
-&dmac {
-       status = "disabled";
-};
-
 #if (!SW_ET0_EN_N)
 &eth0 {
-       status = "disabled";
-
        phy0: ethernet-phy@7 {
                /delete-property/ interrupt-parent;
                /delete-property/ interrupts;
 #endif
 
 &eth1 {
-       status = "disabled";
-
        phy1: ethernet-phy@7 {
                /delete-property/ interrupt-parent;
                /delete-property/ interrupts;
        };
 };
-
-&sdhi0 {
-       status = "disabled";
-};
index c07a487c4e5ad18b426811ca389a3b17e6cd79a9..a8573fdfd8b12e5da888417fb51d02cc13d80c2b 100644 (file)
@@ -6,59 +6,3 @@
  */
 
 #include <arm64/renesas/rzg2ul-smarc.dtsi>
-
-&ehci0 {
-       status = "disabled";
-};
-
-&ehci1 {
-       status = "disabled";
-};
-
-&hsusb {
-       status = "disabled";
-};
-
-&ohci0 {
-       status = "disabled";
-};
-
-&ohci1 {
-       status = "disabled";
-};
-
-&phyrst {
-       status = "disabled";
-};
-
-&sdhi1 {
-       status = "disabled";
-};
-
-&snd_rzg2l {
-       status = "disabled";
-};
-
-&spi1 {
-       status = "disabled";
-};
-
-&ssi1 {
-       status = "disabled";
-};
-
-&usb0_vbus_otg {
-       status = "disabled";
-};
-
-&usb2_phy0 {
-       status = "disabled";
-};
-
-&usb2_phy1 {
-       status = "disabled";
-};
-
-&vccq_sdhi1 {
-       status = "disabled";
-};