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target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
author
Frank Chang
<frank.chang@sifive.com>
Tue, 18 Jan 2022 01:45:13 +0000
(09:45 +0800)
committer
Alistair Francis
<alistair.francis@wdc.com>
Fri, 21 Jan 2022 05:52:56 +0000
(15:52 +1000)
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
20220118014522
.13613-11-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
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diff --git
a/target/riscv/cpu.c
b/target/riscv/cpu.c
index cdb893d601958cdc6696cbcbe9ef949415deecb3..4f3d733db4ea6223b78568a8552561df03bf3b62 100644
(file)
--- a/
target/riscv/cpu.c
+++ b/
target/riscv/cpu.c
@@
-688,6
+688,7
@@
static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
+ DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),