ARM: dts: r7s72100: Correct watchdog timer interrupt type

According to table 7.3 ("List of Interrupt IDs") in the RZ/A1H Hardware
User's Manual rev. 3.00, the watchdog timer interrupt is a level
interrupt.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 4a1aade0e751c3ff832da2b5e1b1d0b84f78868d..c7b3dca6d81cc3f92125384904950522dd5352ac 100644 (file)
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -387,7 +387,7 @@
                wdt: watchdog@fcfe0000 {
                        compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
                        reg = <0xfcfe0000 0x6>;
-                       interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
+                       interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&p0_clk>;
                };