Merge tag 'soc-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC DT updates from Arnd Bergmann:
 "There are a couple new SoCs that are supported for the first time:

   - AMD Pensando Elba is a data processing unit based on Cortex-A72 CPU
     cores

   - Sophgo makes RISC-V based chips, and we now support the CV1800B
     chip used in the milkv-duo board and the massive sg2042 chip in the
     milkv-pioneer, a 64-core developer workstation.

   - Qualcomm Snapdragon 720G (sm7125) is a close relative of Snapdragon
     7c and gets added with some Xiaomi phones

   - Renesas gains support for the R8A779F4 (R-Car S4-8) automotive SoC
     and the RZ/G3S (R9A08G045) embedded SoC.

  There are also a bunch of newly supported machines that use already
  supported chips. On the 32-bit side, we have:

   - USRobotics USR8200 is a NAS/Firewall/router based on the ancient
     Intel IXP4xx platform

   - A couple of machines based on the NXP i.MX5 and i.MX6 platforms

   - One machine each for Allwinner V3s, Aspeed AST2600, Microchip
     sama5d29 and ST STM32mp157

  The other ones all use arm64 cores on chips from allwinner, amlogic,
  freescale, mediatek, qualcomm and rockchip"

* tag 'soc-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (641 commits)
  ARM: dts: BCM5301X: Set switch ports for Linksys EA9200
  ARM: dts: BCM5301X: Set fixed-link for extra Netgear R8000 CPU ports
  ARM: dts: BCM5301X: Explicitly disable unused switch CPU ports
  ARM: dts: BCM5301X: Relicense Vivek's code to the GPL 2.0+ / MIT
  ARM: dts: BCM5301X: Relicense Felix's code to the GPL 2.0+ / MIT
  ARM: dts: BCM5301X: Set MAC address for Asus RT-AC87U
  arm64: dts: socionext: add missing cache properties
  riscv: dts: thead: convert isa detection to new properties
  arm64: dts: Update cache properties for socionext
  arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
  arm64: dts: ti: k3-am654-icssg2: add ICSSG2 Ethernet support
  arm64: dts: ti: k3-am65-main: Add ICSSG IEP nodes
  arm64: dts: ti: k3-am62p5-sk: Updates for SK EVM
  arm64: dts: ti: k3-am62p: Add nodes for more IPs
  arm64: dts: rockchip: Add Turing RK1 SoM support
  dt-bindings: arm: rockchip: Add Turing RK1
  dt-bindings: vendor-prefixes: add turing
  arm64: dts: rockchip: Add DFI to rk3588s
  arm64: dts: rockchip: Add DFI to rk356x
  arm64: dts: rockchip: Always enable DFI on rk3399
  ...

diff --cc Documentation/devicetree/bindings/riscv/cpus.yaml
Simple merge

diff --cc Documentation/devicetree/bindings/vendor-prefixes.yaml
Simple merge

diff --cc MAINTAINERS
Simple merge

diff --cc arch/arm/boot/dts/rockchip/rk3128.dtsi
Simple merge

diff --cc arch/arm/boot/dts/ti/omap/motorola-mapphone-common.dtsi
Simple merge

diff --cc arch/arm64/boot/dts/freescale/imx93.dtsi
index dcf6e4846ac9def75627e3e428ae481c385818da,4a0d604fd0dba77854f6274237d9f55d49b12fc6..ceccf476644072156319648f406610c827ee0792
--- 1/arch/arm64/boot/dts/freescale/imx93.dtsi
--- 2/arch/arm64/boot/dts/freescale/imx93.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
@@@ -185,7 -185,47 +185,47 @@@
                        #size-cells = <1>;
                        ranges;
  
 -                      anomix_ns_gpr: syscon@44210000 {
+                       edma1: dma-controller@44000000 {
+                               compatible = "fsl,imx93-edma3";
+                               reg = <0x44000000 0x200000>;
+                               #dma-cells = <3>;
+                               dma-channels = <31>;
+                               interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,  //  0: Reserved
+                                            <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,  //  1: CANFD1
+                                            <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,  //  2: Reserved
+                                            <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,  //  3: GPIO1 CH0
+                                            <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,  //  4: GPIO1 CH1
+                                            <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, //  5: I3C1 TO Bus
+                                            <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, //  6: I3C1 From Bus
+                                            <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, //  7: LPI2C1 M TX
+                                            <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, //  8: LPI2C1 S TX
+                                            <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, //  9: LPI2C2 M RX
+                                            <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, // 10: LPI2C2 S RX
+                                            <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, // 11: LPSPI1 TX
+                                            <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, // 12: LPSPI1 RX
+                                            <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, // 13: LPSPI2 TX
+                                            <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, // 14: LPSPI2 RX
+                                            <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, // 15: LPTMR1
+                                            <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, // 16: LPUART1 TX
+                                            <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, // 17: LPUART1 RX
+                                            <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, // 18: LPUART2 TX
+                                            <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, // 19: LPUART2 RX
+                                            <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, // 20: S400
+                                            <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, // 21: SAI TX
+                                            <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, // 22: SAI RX
+                                            <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 23: TPM1 CH0/CH2
+                                            <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, // 24: TPM1 CH1/CH3
+                                            <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, // 25: TPM1 Overflow
+                                            <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 26: TMP2 CH0/CH2
+                                            <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, // 27: TMP2 CH1/CH3
+                                            <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, // 28: TMP2 Overflow
+                                            <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, // 29: PDM
+                                            <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; // 30: ADC1
+                               clocks = <&clk IMX93_CLK_EDMA1_GATE>;
+                               clock-names = "dma";
+                       };
+ 
 +                      aonmix_ns_gpr: syscon@44210000 {
                                compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon";
                                reg = <0x44210000 0x1000>;
                        };

diff --cc arch/arm64/boot/dts/mediatek/mt8195-demo.dts
Simple merge

diff --cc arch/arm64/boot/dts/qcom/apq8096-db820c.dts
Simple merge

diff --cc arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
Simple merge

diff --cc arch/arm64/boot/dts/qcom/sm8150.dtsi
Simple merge

diff --cc arch/arm64/boot/dts/rockchip/rk3399.dtsi
Simple merge

diff --cc arch/riscv/boot/dts/thead/th1520.dtsi
Simple merge