drm/amd/display: fine tune logic of edid max TMDS clock check

[WHY]
Check max_tmds_clk_mhz firstly will restrict pixel clock under HDMI
1.4, thus HDMI2.0 port can't correctly support 4K 60Hz.

[HOW]
Fine tune the logic to check max_forum_tmds_clk_mhz firstly.

Signed-off-by: Dale Zhao <dale.zhao@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index f51e5766d8f5229f3fda94d483598cf2ac0e9180..d642414335485e80a4b0c214b3d769cb909f6b80 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -255,15 +255,14 @@ struct dc_edid_caps {
        uint8_t qs_bit;
        uint8_t qy_bit;
 
+       uint32_t max_tmds_clk_mhz;
+
        /*HDMI 2.0 caps*/
        bool lte_340mcsc_scramble;
 
        bool edid_hdmi;
        bool hdr_supported;
 
-       uint32_t max_tmds_clk_mhz;
-       uint32_t max_forum_tmds_clk_mhz;
-
        struct dc_panel_patch panel_patch;
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
index a9af3f6fd8ec294f5fd90bf0d6298074f72fa62f..81db0179f7ea8ac381b976c0ccbd28cbc36baa43 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -629,9 +629,6 @@ static bool dcn10_link_encoder_validate_hdmi_output(
        if (edid_caps->max_tmds_clk_mhz != 0 &&
                        adjusted_pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000)
                return false;
-       if (edid_caps->max_forum_tmds_clk_mhz != 0 &&
-                       adjusted_pix_clk_100hz > edid_caps->max_forum_tmds_clk_mhz * 10000)
-               return false;
 
        if (max_deep_color < crtc_timing->display_color_depth)
                return false;