drm/amd/display: Add check for vrr_active_fixed
authorAustin Zheng <austin.zheng@amd.com>
Fri, 25 Aug 2023 14:51:49 +0000 (10:51 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 11 Sep 2023 21:17:51 +0000 (17:17 -0400)
Why:
vrr_active_fixed should also be checked when
determining if DRR is in use

How:
Add check for vrr_active_fixed when allow_freesync
and vrr_active_variable are also checked

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Austin Zheng <austin.zheng@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

index 979f52ee56046d82f702842d7137053e048e2fa0..2f98dfa06dad1e6391f93cc30068d732cf810b73 100644 (file)
@@ -554,7 +554,7 @@ static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc,
                        vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable;
 
        if (vblank_pipe->stream->ignore_msa_timing_param &&
-               (vblank_pipe->stream->allow_freesync || vblank_pipe->stream->vrr_active_variable))
+               (vblank_pipe->stream->allow_freesync || vblank_pipe->stream->vrr_active_variable || vblank_pipe->stream->vrr_active_fixed))
                populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data);
 }
 
@@ -648,7 +648,7 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc,
        pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable;
        pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst;
        pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param &&
-               (subvp_pipe->stream->allow_freesync || subvp_pipe->stream->vrr_active_variable);
+               (subvp_pipe->stream->allow_freesync || subvp_pipe->stream->vrr_active_variable || subvp_pipe->stream->vrr_active_fixed);
 
        /* Calculate the scaling factor from the src and dst height.
         * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2.
index f5705b3e6e4216d73c9024c9ac63b014d04dd781..bc5f0db23d0c369ea9bbf6eb94d6b43b821b6df5 100644 (file)
@@ -706,7 +706,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)
                                non_subvp_pipes++;
                                drr_psr_capable = (drr_psr_capable || dcn32_is_psr_capable(pipe));
                                if (pipe->stream->ignore_msa_timing_param &&
-                                               (pipe->stream->allow_freesync || pipe->stream->vrr_active_variable)) {
+                                               (pipe->stream->allow_freesync || pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {
                                        drr_pipe_found = true;
                                }
                        }
@@ -764,7 +764,7 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int
                                non_subvp_pipes++;
                                vblank_psr_capable = (vblank_psr_capable || dcn32_is_psr_capable(pipe));
                                if (pipe->stream->ignore_msa_timing_param &&
-                                               (pipe->stream->allow_freesync || pipe->stream->vrr_active_variable)) {
+                                               (pipe->stream->allow_freesync || pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {
                                        drr_pipe_found = true;
                                }
                        }
index 2358c9100cff16f77ce07fd011962ff8e7041efb..92e2d1df5b3299cb0d9392c5704a68b7388175a0 100644 (file)
@@ -822,7 +822,7 @@ static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)
                        continue;
 
                if (drr_pipe->stream->mall_stream_config.type == SUBVP_NONE && drr_pipe->stream->ignore_msa_timing_param &&
-                               (drr_pipe->stream->allow_freesync || drr_pipe->stream->vrr_active_variable))
+                               (drr_pipe->stream->allow_freesync || drr_pipe->stream->vrr_active_variable || drr_pipe->stream->vrr_active_fixed))
                        break;
        }