cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW)
};
uint32_t ddw_extensions[] = {
- cpu_to_be32(1),
- cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW)
+ cpu_to_be32(2),
+ cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW),
+ cpu_to_be32(1), /* 1: ibm,query-pe-dma-window 6 outputs, PAPR 2.8 */
};
SpaprTceTable *tcet;
SpaprDrc *drc;
uint64_t buid;
uint32_t avail, addr, pgmask = 0;
- if ((nargs != 3) || (nret != 5)) {
+ if ((nargs != 3) || ((nret != 5) && (nret != 6))) {
goto param_error_exit;
}
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
rtas_st(rets, 1, avail);
- rtas_st(rets, 2, 0x80000000); /* The largest window we can possibly have */
- rtas_st(rets, 3, pgmask);
- rtas_st(rets, 4, 0); /* DMA migration mask, not supported */
+ if (nret == 6) {
+ /*
+ * Set the Max TCE number as 1<<(58-21) = 0x20.0000.0000
+ * 1<<59 is the huge window start and 21 is 2M page shift.
+ */
+ rtas_st(rets, 2, 0x00000020);
+ rtas_st(rets, 3, 0x00000000);
+ rtas_st(rets, 4, pgmask);
+ rtas_st(rets, 5, 0); /* DMA migration mask, not supported */
+ } else {
+ rtas_st(rets, 2, 0x80000000);
+ rtas_st(rets, 3, pgmask);
+ rtas_st(rets, 4, 0); /* DMA migration mask, not supported */
+ }
trace_spapr_iommu_ddw_query(buid, addr, avail, 0x80000000, pgmask);
return;