clk: renesas: r9a07g044: Add GbEthernet clock/reset

Add ETH{0,1} clock/reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922155145.28156-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index ce2c40a0213a29f3b3d38a4d1bef275d439c8e05..3c518b56c5a605f5a0cefb1375e6fa249d6050f7 100644 (file)
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -138,6 +138,14 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
                                0x578, 2),
        DEF_MOD("usb_pclk",     R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
                                0x578, 3),
+       DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0,
+                               0x57c, 0),
+       DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT,
+                               0x57c, 0),
+       DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0,
+                               0x57c, 1),
+       DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT,
+                               0x57c, 1),
        DEF_MOD("i2c0",         R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
                                0x580, 0),
        DEF_MOD("i2c1",         R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
@@ -182,6 +190,8 @@ static struct rzg2l_reset r9a07g044_resets[] = {
        DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
        DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
        DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
+       DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0),
+       DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1),
        DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
        DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
        DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),