phy: qcom-qmp-usb: define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME register

Other PHYs tables directly reference QPHY_PLL_LOCK_CHK_DLY_TIME register
without using reglayout. Define corresponding register to be used by
msm8996 PHY tables and use it directly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-29-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 150b58ba8cd0f0179c0a0f544daf0542c5ba6a87..c77e427a74cf26b09ec90049d6d68ffbfe05e5f8 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -121,7 +121,6 @@ enum qphy_reg_layout {
        QPHY_COM_START_CONTROL,
        QPHY_COM_PCS_READY_STATUS,
        /* PCS registers */
-       QPHY_PLL_LOCK_CHK_DLY_TIME,
        QPHY_SW_RESET,
        QPHY_START_CTRL,
        QPHY_PCS_READY_STATUS,

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
index 4517f05fe45f0cbe8de479d675f83b7197873447..be6a94439b6c53eb4f94b19fa2b00369b26301a4 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
@@ -121,7 +121,6 @@ enum qphy_reg_layout {
        QPHY_COM_START_CONTROL,
        QPHY_COM_PCS_READY_STATUS,
        /* PCS registers */
-       QPHY_PLL_LOCK_CHK_DLY_TIME,
        QPHY_SW_RESET,
        QPHY_START_CTRL,
        QPHY_PCS_READY_STATUS,
@@ -141,7 +140,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
        [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
        [QPHY_COM_START_CONTROL]        = 0x408,
        [QPHY_COM_PCS_READY_STATUS]     = 0x448,
-       [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
        [QPHY_SW_RESET]                 = 0x00,
        [QPHY_START_CTRL]               = 0x08,
        [QPHY_PCS_STATUS]               = 0x174,
@@ -216,7 +214,7 @@ static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
        QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
        QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 
-       QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x05),
 
        QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x05),
        QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_DOWN_CONTROL, 0x02),

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 59ba40c39ab3b9d5cf3e5b3a7afdc88a87498d23..2d65e1f56bfc34f7f43984b5aff5100f2826c16c 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -121,7 +121,6 @@ enum qphy_reg_layout {
        QPHY_COM_START_CONTROL,
        QPHY_COM_PCS_READY_STATUS,
        /* PCS registers */
-       QPHY_PLL_LOCK_CHK_DLY_TIME,
        QPHY_SW_RESET,
        QPHY_START_CTRL,
        QPHY_PCS_READY_STATUS,
@@ -148,7 +147,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
        [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
        [QPHY_COM_START_CONTROL]        = 0x408,
        [QPHY_COM_PCS_READY_STATUS]     = 0x448,
-       [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
        [QPHY_SW_RESET]                 = 0x00,
        [QPHY_START_CTRL]               = 0x08,
        [QPHY_PCS_STATUS]               = 0x174,
@@ -435,7 +433,7 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
        QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
        QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
        QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
-       QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
        QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
        QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
        QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
index 9593277cbd3a8a5e0eb4470aaf96fdb53e70fa66..c8515f5068720411974d59127c9cfec0dac1a859 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
@@ -24,6 +24,7 @@
 #define QPHY_V2_PCS_LOCK_DETECT_CONFIG3                        0x088
 #define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK                0x0a0
 #define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK          0x0a4
+#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME              0x0a8
 #define QPHY_V2_PCS_FLL_CNTRL1                         0x0c0
 #define QPHY_V2_PCS_FLL_CNTRL2                         0x0c4
 #define QPHY_V2_PCS_FLL_CNT_VAL_L                      0x0c8

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 7ab129cd739b52a1cb963e87819fce0ad92b454e..c8583f5a54bdbce9ead6afae52e5e5b2692515ab 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -121,7 +121,6 @@ enum qphy_reg_layout {
        QPHY_COM_START_CONTROL,
        QPHY_COM_PCS_READY_STATUS,
        /* PCS registers */
-       QPHY_PLL_LOCK_CHK_DLY_TIME,
        QPHY_SW_RESET,
        QPHY_START_CTRL,
        QPHY_PCS_READY_STATUS,

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index ff1e10bfdea316d40f0d33e1a62a5dc506083fa8..1d270356a97f6720af2835345f0e623cf58dc8cb 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -121,7 +121,6 @@ enum qphy_reg_layout {
        QPHY_COM_START_CONTROL,
        QPHY_COM_PCS_READY_STATUS,
        /* PCS registers */
-       QPHY_PLL_LOCK_CHK_DLY_TIME,
        QPHY_SW_RESET,
        QPHY_START_CTRL,
        QPHY_PCS_READY_STATUS,