* NOTE: it may also be possible to use 'pages' from struct firmware and avoid
  * bounce buffer
  */
-static int sram_write_dma_safe(struct wfx_dev *wdev, u32 addr, const u8 *buf,
-                              size_t len)
+static int wfx_sram_write_dma_safe(struct wfx_dev *wdev, u32 addr,
+                                  const u8 *buf, size_t len)
 {
        int ret;
        const u8 *tmp;
        } else {
                tmp = buf;
        }
-       ret = sram_buf_write(wdev, addr, tmp, len);
+       ret = wfx_sram_buf_write(wdev, addr, tmp, len);
        if (tmp != buf)
                kfree(tmp);
        return ret;
 
        start = ktime_get();
        for (;;) {
-               ret = sram_reg_read(wdev, WFX_DCA_NCP_STATUS, ®);
+               ret = wfx_sram_reg_read(wdev, WFX_DCA_NCP_STATUS, ®);
                if (ret < 0)
                        return -EIO;
                now = ktime_get();
                                break;
                        if (ktime_after(now, ktime_add_ms(start, DCA_TIMEOUT)))
                                return -ETIMEDOUT;
-                       ret = sram_reg_read(wdev, WFX_DCA_GET, &bytes_done);
+                       ret = wfx_sram_reg_read(wdev, WFX_DCA_GET, &bytes_done);
                        if (ret < 0)
                                return ret;
                }
                        dev_dbg(wdev->dev, "answer after %lldus\n",
                                ktime_us_delta(now, start));
 
-               ret = sram_write_dma_safe(wdev, WFX_DNLD_FIFO +
-                                         (offs % DNLD_FIFO_SIZE),
-                                         data + offs, DNLD_BLOCK_SIZE);
+               ret = wfx_sram_write_dma_safe(wdev,
+                                             WFX_DNLD_FIFO + (offs % DNLD_FIFO_SIZE),
+                                             data + offs, DNLD_BLOCK_SIZE);
                if (ret < 0)
                        return ret;
 
                 * during first loop
                 */
                offs += DNLD_BLOCK_SIZE;
-               ret = sram_reg_write(wdev, WFX_DCA_PUT, offs);
+               ret = wfx_sram_reg_write(wdev, WFX_DCA_PUT, offs);
                if (ret < 0)
                        return ret;
        }
 {
        u32 reg;
 
-       sram_reg_read(wdev, WFX_STATUS_INFO, ®);
+       wfx_sram_reg_read(wdev, WFX_STATUS_INFO, ®);
        if (reg == 0x12345678)
                return;
-       sram_reg_read(wdev, WFX_ERR_INFO, ®);
+       wfx_sram_reg_read(wdev, WFX_ERR_INFO, ®);
        if (reg < ARRAY_SIZE(fwio_errors) && fwio_errors[reg])
                dev_info(wdev->dev, "secure boot: %s\n", fwio_errors[reg]);
        else
        if (!buf)
                return -ENOMEM;
 
-       sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_READY);
+       wfx_sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_READY);
        ret = wait_ncp_status(wdev, NCP_INFO_READY);
        if (ret)
                goto error;
 
-       sram_buf_read(wdev, WFX_BOOTLOADER_LABEL, buf, BOOTLOADER_LABEL_SIZE);
+       wfx_sram_buf_read(wdev, WFX_BOOTLOADER_LABEL, buf, BOOTLOADER_LABEL_SIZE);
        buf[BOOTLOADER_LABEL_SIZE] = 0;
        dev_dbg(wdev->dev, "bootloader: \"%s\"\n", buf);
 
-       sram_buf_read(wdev, WFX_PTE_INFO, buf, PTE_INFO_SIZE);
+       wfx_sram_buf_read(wdev, WFX_PTE_INFO, buf, PTE_INFO_SIZE);
        ret = get_firmware(wdev, buf[PTE_INFO_KEYSET_IDX], &fw, &fw_offset);
        if (ret)
                goto error;
        header_size = fw_offset + FW_SIGNATURE_SIZE + FW_HASH_SIZE;
 
-       sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_INFO_READ);
+       wfx_sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_INFO_READ);
        ret = wait_ncp_status(wdev, NCP_READY);
        if (ret)
                goto error;
 
-       sram_reg_write(wdev, WFX_DNLD_FIFO, 0xFFFFFFFF); /* Fifo init */
-       sram_write_dma_safe(wdev, WFX_DCA_FW_VERSION, "\x01\x00\x00\x00",
-                           FW_VERSION_SIZE);
-       sram_write_dma_safe(wdev, WFX_DCA_FW_SIGNATURE, fw->data + fw_offset,
-                           FW_SIGNATURE_SIZE);
-       sram_write_dma_safe(wdev, WFX_DCA_FW_HASH,
-                           fw->data + fw_offset + FW_SIGNATURE_SIZE,
-                           FW_HASH_SIZE);
-       sram_reg_write(wdev, WFX_DCA_IMAGE_SIZE, fw->size - header_size);
-       sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_UPLOAD_PENDING);
+       wfx_sram_reg_write(wdev, WFX_DNLD_FIFO, 0xFFFFFFFF); /* Fifo init */
+       wfx_sram_write_dma_safe(wdev, WFX_DCA_FW_VERSION, "\x01\x00\x00\x00",
+                               FW_VERSION_SIZE);
+       wfx_sram_write_dma_safe(wdev, WFX_DCA_FW_SIGNATURE, fw->data + fw_offset,
+                               FW_SIGNATURE_SIZE);
+       wfx_sram_write_dma_safe(wdev, WFX_DCA_FW_HASH,
+                               fw->data + fw_offset + FW_SIGNATURE_SIZE,
+                               FW_HASH_SIZE);
+       wfx_sram_reg_write(wdev, WFX_DCA_IMAGE_SIZE, fw->size - header_size);
+       wfx_sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_UPLOAD_PENDING);
        ret = wait_ncp_status(wdev, NCP_DOWNLOAD_PENDING);
        if (ret)
                goto error;
        dev_dbg(wdev->dev, "firmware load after %lldus\n",
                ktime_us_delta(ktime_get(), start));
 
-       sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_UPLOAD_COMPLETE);
+       wfx_sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_UPLOAD_COMPLETE);
        ret = wait_ncp_status(wdev, NCP_AUTH_OK);
        /* Legacy ROM support */
        if (ret < 0)
                ret = wait_ncp_status(wdev, NCP_PUB_KEY_RDY);
        if (ret < 0)
                goto error;
-       sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_OK_TO_JUMP);
+       wfx_sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_OK_TO_JUMP);
 
 error:
        kfree(buf);
        };
 
        for (i = 0; i < ARRAY_SIZE(gpr_init); i++) {
-               ret = igpr_reg_write(wdev, gpr_init[i].index,
-                                    gpr_init[i].value);
+               ret = wfx_igpr_reg_write(wdev, gpr_init[i].index,
+                                        gpr_init[i].value);
                if (ret < 0)
                        return ret;
                dev_dbg(wdev->dev, "  index %02x: %08x\n",
        reg = CFG_DIRECT_ACCESS_MODE | CFG_CPU_RESET | CFG_BYTE_ORDER_ABCD;
        if (wdev->pdata.use_rising_clk)
                reg |= CFG_CLK_RISE_EDGE;
-       ret = config_reg_write(wdev, reg);
+       ret = wfx_config_reg_write(wdev, reg);
        if (ret < 0) {
                dev_err(wdev->dev, "bus returned an error during first write access. Host configuration error?\n");
                return -EIO;
        }
 
-       ret = config_reg_read(wdev, ®);
+       ret = wfx_config_reg_read(wdev, ®);
        if (ret < 0) {
                dev_err(wdev->dev, "bus returned an error during first read access. Bus configuration error?\n");
                return -EIO;
        if (ret < 0)
                return ret;
 
-       ret = control_reg_write(wdev, CTRL_WLAN_WAKEUP);
+       ret = wfx_control_reg_write(wdev, CTRL_WLAN_WAKEUP);
        if (ret < 0)
                return -EIO;
        start = ktime_get();
        for (;;) {
-               ret = control_reg_read(wdev, ®);
+               ret = wfx_control_reg_read(wdev, ®);
                now = ktime_get();
                if (reg & CTRL_WLAN_READY)
                        break;
        dev_dbg(wdev->dev, "chip wake up after %lldus\n",
                ktime_us_delta(now, start));
 
-       ret = config_reg_write_bits(wdev, CFG_CPU_RESET, 0);
+       ret = wfx_config_reg_write_bits(wdev, CFG_CPU_RESET, 0);
        if (ret < 0)
                return ret;
        ret = load_firmware_secure(wdev);
        if (ret < 0)
                return ret;
-       return config_reg_write_bits(wdev,
-                                    CFG_DIRECT_ACCESS_MODE |
-                                    CFG_IRQ_ENABLE_DATA |
-                                    CFG_IRQ_ENABLE_WRDY,
-                                    CFG_IRQ_ENABLE_DATA);
+       return wfx_config_reg_write_bits(wdev,
+                                        CFG_DIRECT_ACCESS_MODE |
+                                        CFG_IRQ_ENABLE_DATA |
+                                        CFG_IRQ_ENABLE_WRDY,
+                                        CFG_IRQ_ENABLE_DATA);
 }
 
 
 #define WFX_HIF_BUFFER_SIZE 0x2000
 
-static int read32(struct wfx_dev *wdev, int reg, u32 *val)
+static int wfx_read32(struct wfx_dev *wdev, int reg, u32 *val)
 {
        int ret;
        __le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL);
        return ret;
 }
 
-static int write32(struct wfx_dev *wdev, int reg, u32 val)
+static int wfx_write32(struct wfx_dev *wdev, int reg, u32 val)
 {
        int ret;
        __le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL);
        return ret;
 }
 
-static int read32_locked(struct wfx_dev *wdev, int reg, u32 *val)
+static int wfx_read32_locked(struct wfx_dev *wdev, int reg, u32 *val)
 {
        int ret;
 
        wdev->hwbus_ops->lock(wdev->hwbus_priv);
-       ret = read32(wdev, reg, val);
+       ret = wfx_read32(wdev, reg, val);
        _trace_io_read32(reg, *val);
        wdev->hwbus_ops->unlock(wdev->hwbus_priv);
        return ret;
 }
 
-static int write32_locked(struct wfx_dev *wdev, int reg, u32 val)
+static int wfx_write32_locked(struct wfx_dev *wdev, int reg, u32 val)
 {
        int ret;
 
        wdev->hwbus_ops->lock(wdev->hwbus_priv);
-       ret = write32(wdev, reg, val);
+       ret = wfx_write32(wdev, reg, val);
        _trace_io_write32(reg, val);
        wdev->hwbus_ops->unlock(wdev->hwbus_priv);
        return ret;
 }
 
-static int write32_bits_locked(struct wfx_dev *wdev, int reg, u32 mask, u32 val)
+static int wfx_write32_bits_locked(struct wfx_dev *wdev,
+                                  int reg, u32 mask, u32 val)
 {
        int ret;
        u32 val_r, val_w;
        WARN_ON(~mask & val);
        val &= mask;
        wdev->hwbus_ops->lock(wdev->hwbus_priv);
-       ret = read32(wdev, reg, &val_r);
+       ret = wfx_read32(wdev, reg, &val_r);
        _trace_io_read32(reg, val_r);
        if (ret < 0)
                goto err;
        val_w = (val_r & ~mask) | val;
        if (val_w != val_r) {
-               ret = write32(wdev, reg, val_w);
+               ret = wfx_write32(wdev, reg, val_w);
                _trace_io_write32(reg, val_w);
        }
 err:
        return ret;
 }
 
-static int indirect_read(struct wfx_dev *wdev, int reg, u32 addr,
-                        void *buf, size_t len)
+static int wfx_indirect_read(struct wfx_dev *wdev, int reg, u32 addr,
+                            void *buf, size_t len)
 {
        int ret;
        int i;
        else
                return -ENODEV;
 
-       ret = write32(wdev, WFX_REG_BASE_ADDR, addr);
+       ret = wfx_write32(wdev, WFX_REG_BASE_ADDR, addr);
        if (ret < 0)
                goto err;
 
-       ret = read32(wdev, WFX_REG_CONFIG, &cfg);
+       ret = wfx_read32(wdev, WFX_REG_CONFIG, &cfg);
        if (ret < 0)
                goto err;
 
-       ret = write32(wdev, WFX_REG_CONFIG, cfg | prefetch);
+       ret = wfx_write32(wdev, WFX_REG_CONFIG, cfg | prefetch);
        if (ret < 0)
                goto err;
 
        for (i = 0; i < 20; i++) {
-               ret = read32(wdev, WFX_REG_CONFIG, &cfg);
+               ret = wfx_read32(wdev, WFX_REG_CONFIG, &cfg);
                if (ret < 0)
                        goto err;
                if (!(cfg & prefetch))
        return ret;
 }
 
-static int indirect_write(struct wfx_dev *wdev, int reg, u32 addr,
-                         const void *buf, size_t len)
+static int wfx_indirect_write(struct wfx_dev *wdev, int reg, u32 addr,
+                             const void *buf, size_t len)
 {
        int ret;
 
        WARN_ON(len >= WFX_HIF_BUFFER_SIZE);
        WARN_ON(reg != WFX_REG_AHB_DPORT && reg != WFX_REG_SRAM_DPORT);
-       ret = write32(wdev, WFX_REG_BASE_ADDR, addr);
+       ret = wfx_write32(wdev, WFX_REG_BASE_ADDR, addr);
        if (ret < 0)
                return ret;
 
        return wdev->hwbus_ops->copy_to_io(wdev->hwbus_priv, reg, buf, len);
 }
 
-static int indirect_read_locked(struct wfx_dev *wdev, int reg, u32 addr,
-                               void *buf, size_t len)
+static int wfx_indirect_read_locked(struct wfx_dev *wdev, int reg, u32 addr,
+                                   void *buf, size_t len)
 {
        int ret;
 
        wdev->hwbus_ops->lock(wdev->hwbus_priv);
-       ret = indirect_read(wdev, reg, addr, buf, len);
+       ret = wfx_indirect_read(wdev, reg, addr, buf, len);
        _trace_io_ind_read(reg, addr, buf, len);
        wdev->hwbus_ops->unlock(wdev->hwbus_priv);
        return ret;
 }
 
-static int indirect_write_locked(struct wfx_dev *wdev, int reg, u32 addr,
-                                const void *buf, size_t len)
+static int wfx_indirect_write_locked(struct wfx_dev *wdev, int reg, u32 addr,
+                                    const void *buf, size_t len)
 {
        int ret;
 
        wdev->hwbus_ops->lock(wdev->hwbus_priv);
-       ret = indirect_write(wdev, reg, addr, buf, len);
+       ret = wfx_indirect_write(wdev, reg, addr, buf, len);
        _trace_io_ind_write(reg, addr, buf, len);
        wdev->hwbus_ops->unlock(wdev->hwbus_priv);
        return ret;
 }
 
-static int indirect_read32_locked(struct wfx_dev *wdev, int reg,
-                                 u32 addr, u32 *val)
+static int wfx_indirect_read32_locked(struct wfx_dev *wdev, int reg,
+                                     u32 addr, u32 *val)
 {
        int ret;
        __le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL);
        if (!tmp)
                return -ENOMEM;
        wdev->hwbus_ops->lock(wdev->hwbus_priv);
-       ret = indirect_read(wdev, reg, addr, tmp, sizeof(u32));
+       ret = wfx_indirect_read(wdev, reg, addr, tmp, sizeof(u32));
        *val = le32_to_cpu(*tmp);
        _trace_io_ind_read32(reg, addr, *val);
        wdev->hwbus_ops->unlock(wdev->hwbus_priv);
        return ret;
 }
 
-static int indirect_write32_locked(struct wfx_dev *wdev, int reg,
-                                  u32 addr, u32 val)
+static int wfx_indirect_write32_locked(struct wfx_dev *wdev, int reg,
+                                      u32 addr, u32 val)
 {
        int ret;
        __le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL);
                return -ENOMEM;
        *tmp = cpu_to_le32(val);
        wdev->hwbus_ops->lock(wdev->hwbus_priv);
-       ret = indirect_write(wdev, reg, addr, tmp, sizeof(u32));
+       ret = wfx_indirect_write(wdev, reg, addr, tmp, sizeof(u32));
        _trace_io_ind_write32(reg, addr, val);
        wdev->hwbus_ops->unlock(wdev->hwbus_priv);
        kfree(tmp);
        return ret;
 }
 
-int sram_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len)
+int wfx_sram_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len)
 {
-       return indirect_read_locked(wdev, WFX_REG_SRAM_DPORT, addr, buf, len);
+       return wfx_indirect_read_locked(wdev, WFX_REG_SRAM_DPORT,
+                                       addr, buf, len);
 }
 
-int ahb_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len)
+int wfx_ahb_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len)
 {
-       return indirect_read_locked(wdev, WFX_REG_AHB_DPORT, addr, buf, len);
+       return wfx_indirect_read_locked(wdev, WFX_REG_AHB_DPORT,
+                                       addr, buf, len);
 }
 
-int sram_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len)
+int wfx_sram_buf_write(struct wfx_dev *wdev, u32 addr,
+                      const void *buf, size_t len)
 {
-       return indirect_write_locked(wdev, WFX_REG_SRAM_DPORT, addr, buf, len);
+       return wfx_indirect_write_locked(wdev, WFX_REG_SRAM_DPORT,
+                                        addr, buf, len);
 }
 
-int ahb_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len)
+int wfx_ahb_buf_write(struct wfx_dev *wdev, u32 addr,
+                     const void *buf, size_t len)
 {
-       return indirect_write_locked(wdev, WFX_REG_AHB_DPORT, addr, buf, len);
+       return wfx_indirect_write_locked(wdev, WFX_REG_AHB_DPORT,
+                                        addr, buf, len);
 }
 
-int sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val)
+int wfx_sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val)
 {
-       return indirect_read32_locked(wdev, WFX_REG_SRAM_DPORT, addr, val);
+       return wfx_indirect_read32_locked(wdev, WFX_REG_SRAM_DPORT,
+                                         addr, val);
 }
 
-int ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val)
+int wfx_ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val)
 {
-       return indirect_read32_locked(wdev, WFX_REG_AHB_DPORT, addr, val);
+       return wfx_indirect_read32_locked(wdev, WFX_REG_AHB_DPORT,
+                                         addr, val);
 }
 
-int sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val)
+int wfx_sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val)
 {
-       return indirect_write32_locked(wdev, WFX_REG_SRAM_DPORT, addr, val);
+       return wfx_indirect_write32_locked(wdev, WFX_REG_SRAM_DPORT, addr, val);
 }
 
-int ahb_reg_write(struct wfx_dev *wdev, u32 addr, u32 val)
+int wfx_ahb_reg_write(struct wfx_dev *wdev, u32 addr, u32 val)
 {
-       return indirect_write32_locked(wdev, WFX_REG_AHB_DPORT, addr, val);
+       return wfx_indirect_write32_locked(wdev, WFX_REG_AHB_DPORT, addr, val);
 }
 
-int config_reg_read(struct wfx_dev *wdev, u32 *val)
+int wfx_config_reg_read(struct wfx_dev *wdev, u32 *val)
 {
-       return read32_locked(wdev, WFX_REG_CONFIG, val);
+       return wfx_read32_locked(wdev, WFX_REG_CONFIG, val);
 }
 
-int config_reg_write(struct wfx_dev *wdev, u32 val)
+int wfx_config_reg_write(struct wfx_dev *wdev, u32 val)
 {
-       return write32_locked(wdev, WFX_REG_CONFIG, val);
+       return wfx_write32_locked(wdev, WFX_REG_CONFIG, val);
 }
 
-int config_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val)
+int wfx_config_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val)
 {
-       return write32_bits_locked(wdev, WFX_REG_CONFIG, mask, val);
+       return wfx_write32_bits_locked(wdev, WFX_REG_CONFIG, mask, val);
 }
 
-int control_reg_read(struct wfx_dev *wdev, u32 *val)
+int wfx_control_reg_read(struct wfx_dev *wdev, u32 *val)
 {
-       return read32_locked(wdev, WFX_REG_CONTROL, val);
+       return wfx_read32_locked(wdev, WFX_REG_CONTROL, val);
 }
 
-int control_reg_write(struct wfx_dev *wdev, u32 val)
+int wfx_control_reg_write(struct wfx_dev *wdev, u32 val)
 {
-       return write32_locked(wdev, WFX_REG_CONTROL, val);
+       return wfx_write32_locked(wdev, WFX_REG_CONTROL, val);
 }
 
-int control_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val)
+int wfx_control_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val)
 {
-       return write32_bits_locked(wdev, WFX_REG_CONTROL, mask, val);
+       return wfx_write32_bits_locked(wdev, WFX_REG_CONTROL, mask, val);
 }
 
-int igpr_reg_read(struct wfx_dev *wdev, int index, u32 *val)
+int wfx_igpr_reg_read(struct wfx_dev *wdev, int index, u32 *val)
 {
        int ret;
 
        *val = ~0; /* Never return undefined value */
-       ret = write32_locked(wdev, WFX_REG_SET_GEN_R_W, IGPR_RW | index << 24);
+       ret = wfx_write32_locked(wdev, WFX_REG_SET_GEN_R_W, IGPR_RW | index << 24);
        if (ret)
                return ret;
-       ret = read32_locked(wdev, WFX_REG_SET_GEN_R_W, val);
+       ret = wfx_read32_locked(wdev, WFX_REG_SET_GEN_R_W, val);
        if (ret)
                return ret;
        *val &= IGPR_VALUE;
        return ret;
 }
 
-int igpr_reg_write(struct wfx_dev *wdev, int index, u32 val)
+int wfx_igpr_reg_write(struct wfx_dev *wdev, int index, u32 val)
 {
-       return write32_locked(wdev, WFX_REG_SET_GEN_R_W, index << 24 | val);
+       return wfx_write32_locked(wdev, WFX_REG_SET_GEN_R_W, index << 24 | val);
 }
 
 int wfx_data_read(struct wfx_dev *wdev, void *buf, size_t buf_len);
 int wfx_data_write(struct wfx_dev *wdev, const void *buf, size_t buf_len);
 
-int sram_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
-int sram_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
+int wfx_sram_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
+int wfx_sram_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
 
-int ahb_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
-int ahb_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
+int wfx_ahb_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
+int wfx_ahb_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
 
-int sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
-int sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
+int wfx_sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
+int wfx_sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
 
-int ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
-int ahb_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
+int wfx_ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
+int wfx_ahb_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
 
 #define CFG_ERR_SPI_FRAME          0x00000001 /* only with SPI */
 #define CFG_ERR_SDIO_BUF_MISMATCH  0x00000001 /* only with SDIO */
 #define CFG_DEVICE_ID_MAJOR        0x07000000
 #define CFG_DEVICE_ID_RESERVED     0x78000000
 #define CFG_DEVICE_ID_TYPE         0x80000000
-int config_reg_read(struct wfx_dev *wdev, u32 *val);
-int config_reg_write(struct wfx_dev *wdev, u32 val);
-int config_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
+int wfx_config_reg_read(struct wfx_dev *wdev, u32 *val);
+int wfx_config_reg_write(struct wfx_dev *wdev, u32 val);
+int wfx_config_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
 
 #define CTRL_NEXT_LEN_MASK   0x00000FFF
 #define CTRL_WLAN_WAKEUP     0x00001000
 #define CTRL_WLAN_READY      0x00002000
-int control_reg_read(struct wfx_dev *wdev, u32 *val);
-int control_reg_write(struct wfx_dev *wdev, u32 val);
-int control_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
+int wfx_control_reg_read(struct wfx_dev *wdev, u32 *val);
+int wfx_control_reg_write(struct wfx_dev *wdev, u32 val);
+int wfx_control_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
 
 #define IGPR_RW          0x80000000
 #define IGPR_INDEX       0x7F000000
 #define IGPR_VALUE       0x00FFFFFF
-int igpr_reg_read(struct wfx_dev *wdev, int index, u32 *val);
-int igpr_reg_write(struct wfx_dev *wdev, int index, u32 val);
+int wfx_igpr_reg_read(struct wfx_dev *wdev, int index, u32 *val);
+int wfx_igpr_reg_write(struct wfx_dev *wdev, int index, u32 val);
 
 #endif