drm/amd/display: Indirect reg read macro with shift and mask

[Why]
Recent double buffering changes for dcn2 use IX_REG_READ.
However, this macro returns the full register value, with the need to
manually shift and mask it to retrieve field data.

[How]
Create new IX_REG_GET macro that handles shift and mask.
Use this for double buffering reads instead of IX_REG_READ.

Signed-off-by: Noah Abradjian <noah.abradjian@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index 02a63e9cb62ff555b2cb2945c05f1237001f079b..737048d8a96c16cf2bf2b89763e243a80d2af8db 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -552,6 +552,36 @@ uint32_t generic_read_indirect_reg(const struct dc_context *ctx,
        return value;
 }
 
+uint32_t generic_indirect_reg_get(const struct dc_context *ctx,
+               uint32_t addr_index, uint32_t addr_data,
+               uint32_t index, int n,
+               uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
+               ...)
+{
+       uint32_t shift, mask, *field_value;
+       uint32_t value = 0;
+       int i = 1;
+
+       va_list ap;
+
+       va_start(ap, field_value1);
+
+       value = generic_read_indirect_reg(ctx, addr_index, addr_data, index);
+       *field_value1 = get_reg_field_value_ex(value, mask1, shift1);
+
+       while (i < n) {
+               shift = va_arg(ap, uint32_t);
+               mask = va_arg(ap, uint32_t);
+               field_value = va_arg(ap, uint32_t *);
+
+               *field_value = get_reg_field_value_ex(value, mask, shift);
+               i++;
+       }
+
+       va_end(ap);
+
+       return value;
+}
 
 uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
                uint32_t addr_index, uint32_t addr_data,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
index 141dea963db99c42918931299fc3baf6683c26fe..27610251c57f1df2c675e9e256e6d9a1d9850781 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
@@ -589,14 +589,22 @@
  *                     Gamut Remap Mode: [10..9]
  */
 #define CM_TEST_DEBUG_DATA_STATUS_IDX 9
-#define CM_TEST_DEBUG_DATA_ICSC_MODE_SH 3
-#define CM_TEST_DEBUG_DATA_ICSC_MODE_MASK 0x3
-#define CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE_SH 9
-#define CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE_MASK 0x3
+
+#define TF_DEBUG_REG_LIST_SH_DCN20 \
+       TF_DEBUG_REG_LIST_SH_DCN10, \
+       .CM_TEST_DEBUG_DATA_ICSC_MODE = 3, \
+       .CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE = 9
+
+#define TF_DEBUG_REG_LIST_MASK_DCN20 \
+       TF_DEBUG_REG_LIST_MASK_DCN10, \
+       .CM_TEST_DEBUG_DATA_ICSC_MODE = 0x18, \
+       .CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE = 0x600
 
 #define TF_REG_FIELD_LIST_DCN2_0(type) \
        TF_REG_FIELD_LIST(type) \
        type CM_BLNDGAM_LUT_DATA; \
+       type CM_TEST_DEBUG_DATA_ICSC_MODE; \
+       type CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE; \
        type FORMAT_CNV16; \
        type CNVC_BYPASS_MSB_ALIGN; \
        type CLAMP_POSITIVE; \

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
index 4047d406a74c69b6720838f4e665c542787dfe1d..8dc3d1f7398422e49bc7823e3c5bad56ab111673 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
@@ -176,12 +176,9 @@ static void program_gamut_remap(
         * currently. select the alternate set to double buffer
         * the update so gamut_remap is updated on frame boundary
         */
-       cur_select = IX_REG_READ(CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_DATA,
-                                       CM_TEST_DEBUG_DATA_STATUS_IDX);
-
-       /* IX_REG_READ reads whole reg, so isolate part we want [10..9] */
-       cur_select = (cur_select >> CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE_SH)
-                                       & CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE_MASK;
+       IX_REG_GET(CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_DATA,
+                                       CM_TEST_DEBUG_DATA_STATUS_IDX,
+                                       CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE, &cur_select);
 
        /* value stored in dbg reg will be 1 greater than mode we want */
        if (cur_select != DCN2_GAMUT_REMAP_COEF_A)
@@ -275,12 +272,9 @@ void dpp2_program_input_csc(
         * currently.  select the alternate set to double buffer
         * the CSC update so CSC is updated on frame boundary
         */
-       cur_select = IX_REG_READ(CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_DATA,
-                                       CM_TEST_DEBUG_DATA_STATUS_IDX);
-
-       /* IX_REG_READ reads whole reg, so isolate part we want [4..3] */
-       cur_select = (cur_select >> CM_TEST_DEBUG_DATA_ICSC_MODE_SH)
-                                       & CM_TEST_DEBUG_DATA_ICSC_MODE_MASK;
+       IX_REG_GET(CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_DATA,
+                                       CM_TEST_DEBUG_DATA_STATUS_IDX,
+                                       CM_TEST_DEBUG_DATA_ICSC_MODE, &cur_select);
 
        if (cur_select != DCN2_ICSC_SELECT_ICSC_A)
                select = DCN2_ICSC_SELECT_ICSC_A;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
index ce95e7db48142d0d8d34025befa6658603fad9db..de9c857ab3e97abf9bd8ca0e53896a391b46e55f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
@@ -153,11 +153,9 @@ void mpc2_set_output_csc(
         * currently.  select the alternate set to double buffer
         * the CSC update so CSC is updated on frame boundary
         */
-       cur_mode = IX_REG_READ(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_DATA,
-                                               MPC_OCSC_TEST_DEBUG_DATA_STATUS_IDX);
-
-       /* Isolate part of reg data we want [1..0] */
-       cur_mode = cur_mode & MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE_MASK;
+       IX_REG_GET(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_DATA,
+                                               MPC_OCSC_TEST_DEBUG_DATA_STATUS_IDX,
+                                               MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE, &cur_mode);
 
        if (cur_mode != MPC_OUTPUT_CSC_COEF_A)
                ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
@@ -213,11 +211,9 @@ void mpc2_set_ocsc_default(
         * currently.  select the alternate set to double buffer
         * the CSC update so CSC is updated on frame boundary
         */
-       cur_mode = IX_REG_READ(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_DATA,
-                                               MPC_OCSC_TEST_DEBUG_DATA_STATUS_IDX);
-
-       /* Isolate part of reg data we want [1..0] */
-       cur_mode = cur_mode & MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE_MASK;
+       IX_REG_GET(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_DATA,
+                                               MPC_OCSC_TEST_DEBUG_DATA_STATUS_IDX,
+                                               MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE, &cur_mode);
 
        if (cur_mode != MPC_OUTPUT_CSC_COEF_A)
                ocsc_mode = MPC_OUTPUT_CSC_COEF_A;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
index 950e6f9cd23e2d8154abd2af1192bf73bd9d1999..c78fd5123497b6f14a4b043aba3c01aec9ba4297 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
@@ -140,7 +140,6 @@
        SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
        SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
        SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
-       SF(MPC_OCSC_TEST_DEBUG_DATA, MPC_OCSC_TEST_DEBUG_DATA, mask_sh),\
        SF(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_INDEX, mask_sh),\
        SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
        SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
@@ -189,7 +188,12 @@
  *                     OCSC Mode: [1..0]
  */
 #define MPC_OCSC_TEST_DEBUG_DATA_STATUS_IDX 1
-#define MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE_MASK 0x3
+
+#define MPC_DEBUG_REG_LIST_SH_DCN20 \
+       .MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE = 0
+
+#define MPC_DEBUG_REG_LIST_MASK_DCN20 \
+       .MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE = 0x3
 
 #define MPC_REG_FIELD_LIST_DCN2_0(type) \
        MPC_REG_FIELD_LIST(type)\
@@ -198,7 +202,7 @@
        type MPCC_TOP_GAIN;\
        type MPCC_BOT_GAIN_INSIDE;\
        type MPCC_BOT_GAIN_OUTSIDE;\
-       type MPC_OCSC_TEST_DEBUG_DATA;\
+       type MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE;\
        type MPC_OCSC_TEST_DEBUG_INDEX;\
        type MPC_OCSC_MODE;\
        type MPC_OCSC_C11_A;\

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2ef6d0e2b0ed006637525701789d2c8aab5eda90..85f90f3e24cb50a600a447db86dcfbc061397c52 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -652,12 +652,12 @@ static const struct dcn2_dpp_registers tf_regs[] = {
 
 static const struct dcn2_dpp_shift tf_shift = {
                TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
-               TF_DEBUG_REG_LIST_SH_DCN10
+               TF_DEBUG_REG_LIST_SH_DCN20
 };
 
 static const struct dcn2_dpp_mask tf_mask = {
                TF_REG_LIST_SH_MASK_DCN20(_MASK),
-               TF_DEBUG_REG_LIST_MASK_DCN10
+               TF_DEBUG_REG_LIST_MASK_DCN20
 };
 
 #define dwbc_regs_dcn2(id)\
@@ -711,11 +711,13 @@ static const struct dcn20_mpc_registers mpc_regs = {
 };
 
 static const struct dcn20_mpc_shift mpc_shift = {
-       MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
+       MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
+       MPC_DEBUG_REG_LIST_SH_DCN20
 };
 
 static const struct dcn20_mpc_mask mpc_mask = {
-       MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
+       MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
+       MPC_DEBUG_REG_LIST_MASK_DCN20
 };
 
 #define tg_regs(id)\

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 0dd724de201af3dd93f765d6f596dfe44bcbbac2..f1ec3448c0c061d8282968795b45b7aaf2b651ee 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -471,11 +471,13 @@ static const struct dcn20_mpc_registers mpc_regs = {
 };
 
 static const struct dcn20_mpc_shift mpc_shift = {
-       MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
+       MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
+       MPC_DEBUG_REG_LIST_SH_DCN20
 };
 
 static const struct dcn20_mpc_mask mpc_mask = {
-       MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
+       MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
+       MPC_DEBUG_REG_LIST_MASK_DCN20
 };
 
 #define hubp_regs(id)\
@@ -622,12 +624,12 @@ static const struct dcn2_dpp_registers tf_regs[] = {
 
 static const struct dcn2_dpp_shift tf_shift = {
                TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
-               TF_DEBUG_REG_LIST_SH_DCN10
+               TF_DEBUG_REG_LIST_SH_DCN20
 };
 
 static const struct dcn2_dpp_mask tf_mask = {
                TF_REG_LIST_SH_MASK_DCN20(_MASK),
-               TF_DEBUG_REG_LIST_MASK_DCN10
+               TF_DEBUG_REG_LIST_MASK_DCN20
 };
 
 #define stream_enc_regs(id)\

diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
index 47e307388581a88424427101ca8f3adfb5df6d68..2470405e996bc5b9f1b1008233467194714fa769 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
@@ -458,7 +458,14 @@ uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr,
 #define IX_REG_READ(index_reg_name, data_reg_name, index) \
                generic_read_indirect_reg(CTX, REG(index_reg_name), REG(data_reg_name), IND_REG(index))
 
+#define IX_REG_GET_N(index_reg_name, data_reg_name, index, n, ...) \
+               generic_indirect_reg_get(CTX, REG(index_reg_name), REG(data_reg_name), \
+                               IND_REG(index), \
+                               n, __VA_ARGS__)
 
+#define IX_REG_GET(index_reg_name, data_reg_name, index, field, val) \
+               IX_REG_GET_N(index_reg_name, data_reg_name, index, 1, \
+                               FN(data_reg_name, field), val)
 
 #define IX_REG_UPDATE_N(index_reg_name, data_reg_name, index, n, ...)  \
                generic_indirect_reg_update_ex(CTX, \
@@ -479,6 +486,12 @@ uint32_t generic_read_indirect_reg(const struct dc_context *ctx,
                uint32_t addr_index, uint32_t addr_data,
                uint32_t index);
 
+uint32_t generic_indirect_reg_get(const struct dc_context *ctx,
+               uint32_t addr_index, uint32_t addr_data,
+               uint32_t index, int n,
+               uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
+               ...);
+
 uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
                uint32_t addr_index, uint32_t addr_data,
                uint32_t index, uint32_t reg_val, int n,