perf tool ibs: Sync AMD IBS header file

IBS support has been enhanced with two new features in upcoming uarch:

1. DataSrc extension
2. L3 miss filtering.

Additional set of bits has been introduced in IBS registers to exploit
these features.

New bits are already defining in arch/x86/ header. Sync it with tools
header file. Also rename existing ibs_op_data field 'data_src' to
'data_src_lo'.

Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
Acked-by: Namhyung Kim <namhyung@kernel.org>
Cc: Ananth Narayan <ananth.narayan@amd.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Kim Phillips <kim.phillips@amd.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Robert Richter <rrichter@amd.com>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Santosh Shukla <santosh.shukla@amd.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: like.xu.linux@gmail.com
Cc: x86@kernel.org
Link: https://lore.kernel.org/r/20220604044519.594-8-ravi.bangoria@amd.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

diff --git a/tools/arch/x86/include/asm/amd-ibs.h b/tools/arch/x86/include/asm/amd-ibs.h
index 765e9e752d038ed67e8a3a2f69ee2f6dea6f6631..9a3312e12e2ed99bd00940d96837711f2ca4b086 100644 (file)
--- a/tools/arch/x86/include/asm/amd-ibs.h
+++ b/tools/arch/x86/include/asm/amd-ibs.h
@@ -29,7 +29,10 @@ union ibs_fetch_ctl {
                        rand_en:1,      /* 57: random tagging enable */
                        fetch_l2_miss:1,/* 58: L2 miss for sampled fetch
                                         *      (needs IbsFetchComp) */
-                       reserved:5;     /* 59-63: reserved */
+                       l3_miss_only:1, /* 59: Collect L3 miss samples only */
+                       fetch_oc_miss:1,/* 60: Op cache miss for the sampled fetch */
+                       fetch_l3_miss:1,/* 61: L3 cache miss for the sampled fetch */
+                       reserved:2;     /* 62-63: reserved */
        };
 };
 
@@ -38,14 +41,14 @@ union ibs_op_ctl {
        __u64 val;
        struct {
                __u64   opmaxcnt:16,    /* 0-15: periodic op max. count */
-                       reserved0:1,    /* 16: reserved */
+                       l3_miss_only:1, /* 16: Collect L3 miss samples only */
                        op_en:1,        /* 17: op sampling enable */
                        op_val:1,       /* 18: op sample valid */
                        cnt_ctl:1,      /* 19: periodic op counter control */
                        opmaxcnt_ext:7, /* 20-26: upper 7 bits of periodic op maximum count */
-                       reserved1:5,    /* 27-31: reserved */
+                       reserved0:5,    /* 27-31: reserved */
                        opcurcnt:27,    /* 32-58: periodic op counter current count */
-                       reserved2:5;    /* 59-63: reserved */
+                       reserved1:5;    /* 59-63: reserved */
        };
 };
 
@@ -71,11 +74,12 @@ union ibs_op_data {
 union ibs_op_data2 {
        __u64 val;
        struct {
-               __u64   data_src:3,     /* 0-2: data source */
+               __u64   data_src_lo:3,  /* 0-2: data source low */
                        reserved0:1,    /* 3: reserved */
                        rmt_node:1,     /* 4: destination node */
                        cache_hit_st:1, /* 5: cache hit state */
-                       reserved1:57;   /* 5-63: reserved */
+                       data_src_hi:2,  /* 6-7: data source high */
+                       reserved1:56;   /* 8-63: reserved */
        };
 };
 

diff --git a/tools/perf/util/amd-sample-raw.c b/tools/perf/util/amd-sample-raw.c
index d19d765195c54b797a0c2fbef0dce39f0c7f1125..3b623ea6ee7ea7ef1f1552c105b044c68ce5d4cf 100644 (file)
--- a/tools/perf/util/amd-sample-raw.c
+++ b/tools/perf/util/amd-sample-raw.c
@@ -98,9 +98,9 @@ static void pr_ibs_op_data2(union ibs_op_data2 reg)
        };
 
        printf("ibs_op_data2:\t%016llx %sRmtNode %d%s\n", reg.val,
-              reg.data_src == 2 ? (reg.cache_hit_st ? "CacheHitSt 1=O-State "
+              reg.data_src_lo == 2 ? (reg.cache_hit_st ? "CacheHitSt 1=O-State "
                                                     : "CacheHitSt 0=M-state ") : "",
-              reg.rmt_node, data_src_str[reg.data_src]);
+              reg.rmt_node, data_src_str[reg.data_src_lo]);
 }
 
 static void pr_ibs_op_data3(union ibs_op_data3 reg)