ARM: dts: hisilicon: Fix SP804 users

The SP804 binding only specifies one or three clocks, but does not allow
just two clocks.
The HiSi 3620 .dtsi specified two clocks for the two timers, plus gave
one "apb_pclk" clock-name to appease the primecell bus driver.

Extend the clocks by duplicating the first clock to the end of the clock
list, and add two dummy clock-names to make the primecell driver happy.

I don't know what the real APB clock for the IP is, but with the current
DT the first timer clock was used for that, so this change keeps the
current status.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index f0af1bf2b4d8eb51bf511b25f0fe000a1439c974..355175b25fd62201782aa802b2e737cbf5f30a5c 100644 (file)
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -111,8 +111,10 @@
                        reg = <0x800000 0x1000>;
                        /* timer00 & timer01 */
                        interrupts = <0 0 4>, <0 1 4>;
-                       clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
-                       clock-names = "apb_pclk";
+                       clocks = <&clock HI3620_TIMER0_MUX>,
+                                <&clock HI3620_TIMER1_MUX>,
+                                <&clock HI3620_TIMER0_MUX>;
+                       clock-names = "timer0clk", "timer1clk", "apb_pclk";
                        status = "disabled";
                };
 
@@ -121,8 +123,10 @@
                        reg = <0x801000 0x1000>;
                        /* timer10 & timer11 */
                        interrupts = <0 2 4>, <0 3 4>;
-                       clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
-                       clock-names = "apb_pclk";
+                       clocks = <&clock HI3620_TIMER2_MUX>,
+                                <&clock HI3620_TIMER3_MUX>,
+                                <&clock HI3620_TIMER2_MUX>;
+                       clock-names = "timer0clk", "timer1clk", "apb_pclk";
                        status = "disabled";
                };
 
@@ -131,8 +135,10 @@
                        reg = <0xa01000 0x1000>;
                        /* timer20 & timer21 */
                        interrupts = <0 4 4>, <0 5 4>;
-                       clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
-                       clock-names = "apb_pclk";
+                       clocks = <&clock HI3620_TIMER4_MUX>,
+                                <&clock HI3620_TIMER5_MUX>,
+                                <&clock HI3620_TIMER4_MUX>;
+                       clock-names = "timer0lck", "timer1clk", "apb_pclk";
                        status = "disabled";
                };
 
@@ -141,8 +147,10 @@
                        reg = <0xa02000 0x1000>;
                        /* timer30 & timer31 */
                        interrupts = <0 6 4>, <0 7 4>;
-                       clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
-                       clock-names = "apb_pclk";
+                       clocks = <&clock HI3620_TIMER6_MUX>,
+                                <&clock HI3620_TIMER7_MUX>,
+                                <&clock HI3620_TIMER6_MUX>;
+                       clock-names = "timer0clk", "timer1clk", "apb_pclk";
                        status = "disabled";
                };
 
@@ -151,8 +159,10 @@
                        reg = <0xa03000 0x1000>;
                        /* timer40 & timer41 */
                        interrupts = <0 96 4>, <0 97 4>;
-                       clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
-                       clock-names = "apb_pclk";
+                       clocks = <&clock HI3620_TIMER8_MUX>,
+                                <&clock HI3620_TIMER9_MUX>,
+                                <&clock HI3620_TIMER8_MUX>;
+                       clock-names = "timer0clk", "timer1clk", "apb_pclk";
                        status = "disabled";
                };
 

diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index 4263a9339c2e5899901041acaa2c16a34112e8ce..f5871b1d1ec452ce21f7b201d811698a9985f065 100644 (file)
--- a/arch/arm/boot/dts/hip04.dtsi
+++ b/arch/arm/boot/dts/hip04.dtsi
@@ -226,8 +226,8 @@
                        compatible = "arm,sp804", "arm,primecell";
                        reg = <0x3000000 0x1000>;
                        interrupts = <0 224 4>;
-                       clocks = <&clk_50m>, <&clk_50m>;
-                       clock-names = "apb_pclk";
+                       clocks = <&clk_50m>, <&clk_50m>, <&clk_50m>;
+                       clock-names = "timer0clk", "timer1clk", "apb_pclk";
                };
 
                arm-pmu {