arm64: dts: freescale: add missing cache properties

As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:

  fsl-ls2080a-simu.dtb: l2-cache3: 'cache-unified' is a required property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 678bb0358751eb741adbd2dcb2a96af57e6c63c7..9cbb31191cf92fd345e6908922fa68cf8a8eeed9 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -47,6 +47,7 @@
                l2: l2-cache {
                        compatible = "cache";
                        cache-level = <2>;
+                       cache-unified;
                };
        };
 

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index b9fd24cdc919beff2e75b0fe0e8d194465a563fb..f8acbefc805b2039ca47038b4d3b8239e505a5f8 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -85,6 +85,7 @@
                l2: l2-cache {
                        compatible = "cache";
                        cache-level = <2>;
+                       cache-unified;
                };
        };
 

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index a01e3cfec77fb9794d7fd8a61557cac963ad3881..50f68ca5a9af710eba8044f1f164142791cab0ec 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -80,6 +80,7 @@
                l2: l2-cache {
                        compatible = "cache";
                        cache-level = <2>;
+                       cache-unified;
                };
        };
 

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 1e5d76c4d83db04e127d7528b2fddb05de53849a..1aa38ed09aa4fa89c29f651d175e75c78593e079 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -96,21 +96,25 @@
        cluster0_l2: l2-cache0 {
                compatible = "cache";
                cache-level = <2>;
+               cache-unified;
        };
 
        cluster1_l2: l2-cache1 {
                compatible = "cache";
                cache-level = <2>;
+               cache-unified;
        };
 
        cluster2_l2: l2-cache2 {
                compatible = "cache";
                cache-level = <2>;
+               cache-unified;
        };
 
        cluster3_l2: l2-cache3 {
                compatible = "cache";
                cache-level = <2>;
+               cache-unified;
        };
 
        CPU_PW20: cpu-pw20 {

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
index c12c86915ec87df70563100c4ad2011a800cf1fb..8581ea55d2540f087e5944beafde9a16f1637db4 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
@@ -96,21 +96,25 @@
        cluster0_l2: l2-cache0 {
                compatible = "cache";
                cache-level = <2>;
+               cache-unified;
        };
 
        cluster1_l2: l2-cache1 {
                compatible = "cache";
                cache-level = <2>;
+               cache-unified;
        };
 
        cluster2_l2: l2-cache2 {
                compatible = "cache";
                cache-level = <2>;
+               cache-unified;
        };
 
        cluster3_l2: l2-cache3 {
                compatible = "cache";
                cache-level = <2>;
+               cache-unified;
        };
 
        CPU_PW20: cpu-pw20 {