riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110

Add USB and PCIe PHY dts nodes for the StarFive JH7110 SoC.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 90aabeac7b51b185cf2c9c501e683b6ce5efcd89..dbc1243a0e752a1db8d93d8f65b75bd1130ed6e6 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -446,6 +446,27 @@
                        status = "disabled";
                };
 
+               usbphy0: phy@10200000 {
+                       compatible = "starfive,jh7110-usb-phy";
+                       reg = <0x0 0x10200000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
+                                <&stgcrg JH7110_STGCLK_USB0_APP_125>;
+                       clock-names = "125m", "app_125m";
+                       #phy-cells = <0>;
+               };
+
+               pciephy0: phy@10210000 {
+                       compatible = "starfive,jh7110-pcie-phy";
+                       reg = <0x0 0x10210000 0x0 0x10000>;
+                       #phy-cells = <0>;
+               };
+
+               pciephy1: phy@10220000 {
+                       compatible = "starfive,jh7110-pcie-phy";
+                       reg = <0x0 0x10220000 0x0 0x10000>;
+                       #phy-cells = <0>;
+               };
+
                stgcrg: clock-controller@10230000 {
                        compatible = "starfive,jh7110-stgcrg";
                        reg = <0x0 0x10230000 0x0 0x10000>;