i2c: cadence: Avoid fifo clear after start

The Driver unintentionally programs ctrl reg to clear the fifo, which
happens after the start of transaction. Previously, this was not an issue
as it involved read-modified-write. However, this issue breaks i2c reads
on QEMU, as i2c-read is executed before guest starts programming control
register.

Fixes: ff0cf7bca630 ("i2c: cadence: Remove unnecessary register reads")
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>

diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c
index 4bb7d6756947cd16a9ab64295dfaa650bd58677f..2fce3e84ba6464a91f80496a180df27ff452493a 100644 (file)
--- a/drivers/i2c/busses/i2c-cadence.c
+++ b/drivers/i2c/busses/i2c-cadence.c
@@ -633,6 +633,7 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id)
 
        if (hold_clear) {
                ctrl_reg &= ~CDNS_I2C_CR_HOLD;
+               ctrl_reg &= ~CDNS_I2C_CR_CLR_FIFO;
                /*
                 * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size
                 * register reaches '0'. This is an IP bug which causes transfer size