perf/x86/intel/lbr: Add a function pointer for LBR read

The method to read Architectural LBRs is different from previous
model-specific LBR. Perf has to implement a different function.

A function pointer for LBR read is introduced. Perf should initialize
the corresponding function at boot time, and avoid checking lbr_format
at run time.

The current 64-bit LBR read function is set as default.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1593780569-62993-4-git-send-email-kan.liang@linux.intel.com

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index fe49e99e4fbf2af1856b136105d75fe97eacfd76..6414b4799ce7f15eeb52021e5e5176c3ef8a02e6 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3980,6 +3980,7 @@ static __initconst const struct x86_pmu core_pmu = {
        .check_period           = intel_pmu_check_period,
 
        .lbr_reset              = intel_pmu_lbr_reset_64,
+       .lbr_read               = intel_pmu_lbr_read_64,
 };
 
 static __initconst const struct x86_pmu intel_pmu = {
@@ -4027,6 +4028,7 @@ static __initconst const struct x86_pmu intel_pmu = {
        .aux_output_match       = intel_pmu_aux_output_match,
 
        .lbr_reset              = intel_pmu_lbr_reset_64,
+       .lbr_read               = intel_pmu_lbr_read_64,
 };
 
 static __init void intel_clovertown_quirk(void)
@@ -4653,8 +4655,10 @@ __init int intel_pmu_init(void)
                x86_pmu.intel_cap.capabilities = capabilities;
        }
 
-       if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
+       if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
                x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
+               x86_pmu.lbr_read = intel_pmu_lbr_read_32;
+       }
 
        intel_ds_init();
 

diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index 7af27a766002518fa9db63775e8a7341e7e3043d..b8943f45ca693c55919753ae22a7df6939b893f1 100644 (file)
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -562,7 +562,7 @@ void intel_pmu_lbr_disable_all(void)
                __intel_pmu_lbr_disable();
 }
 
-static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
+void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
 {
        unsigned long mask = x86_pmu.lbr_nr - 1;
        u64 tos = intel_pmu_lbr_tos();
@@ -599,7 +599,7 @@ static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
  * is the same as the linear address, allowing us to merge the LIP and EIP
  * LBR formats.
  */
-static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
+void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
 {
        bool need_info = false, call_stack = false;
        unsigned long mask = x86_pmu.lbr_nr - 1;
@@ -704,10 +704,7 @@ void intel_pmu_lbr_read(void)
            cpuc->lbr_users == cpuc->lbr_pebs_users)
                return;
 
-       if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
-               intel_pmu_lbr_read_32(cpuc);
-       else
-               intel_pmu_lbr_read_64(cpuc);
+       x86_pmu.lbr_read(cpuc);
 
        intel_pmu_lbr_filter(cpuc);
 }

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 5c1ad4360715cbc60b3e1f53d9ef486f9d6f62c3..312d27f269e6aae249559d7bdfed95c37902ae9b 100644 (file)
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -694,6 +694,7 @@ struct x86_pmu {
        bool            lbr_pt_coexist;            /* (LBR|BTS) may coexist with PT */
 
        void            (*lbr_reset)(void);
+       void            (*lbr_read)(struct cpu_hw_events *cpuc);
 
        /*
         * Intel PT/LBR/BTS are exclusive
@@ -1085,6 +1086,10 @@ void intel_pmu_lbr_disable_all(void);
 
 void intel_pmu_lbr_read(void);
 
+void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc);
+
+void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc);
+
 void intel_pmu_lbr_init_core(void);
 
 void intel_pmu_lbr_init_nhm(void);