mailbox: qcom: Add support for SDX55 APCS IPC

In SDX55, the IPC bits are located in the APCS GCC block. Also, this block
can provide clock functionality. Hence, add support for IPC with correct
offset and name of the clock provider.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index 0fb0ab028b62920606c76279890f46185535a439..f25324d03842e94d342126e6d19c13121873178f 100644 (file)
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -61,11 +61,15 @@ static const struct qcom_apcs_ipc_data apps_shared_apcs_data = {
        .offset = 12, .clk_name = NULL
 };
 
+static const struct qcom_apcs_ipc_data sdx55_apcs_data = {
+       .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk"
+};
+
 static const struct regmap_config apcs_regmap_config = {
        .reg_bits = 32,
        .reg_stride = 4,
        .val_bits = 32,
-       .max_register = 0xFFC,
+       .max_register = 0x1008,
        .fast_io = true,
 };
 
@@ -163,6 +167,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {
        { .compatible = "qcom,sdm660-apcs-hmss-global", .data = &sdm660_apcs_data },
        { .compatible = "qcom,sdm845-apss-shared", .data = &apps_shared_apcs_data },
        { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data },
+       { .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data },
        {}
 };
 MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);