iio: dac: ad5766: Fix alignment for DMA safety

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes: fd9373e41b9b ("iio: dac: ad5766: add driver support for AD5766")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-54-jic23@kernel.org

diff --git a/drivers/iio/dac/ad5766.c b/drivers/iio/dac/ad5766.c
index 43189af2fb1f3a43d1930478fbbcdd7a6a4c9232..899894523752f032f655e8c7eb9720ffbbf91e46 100644 (file)
--- a/drivers/iio/dac/ad5766.c
+++ b/drivers/iio/dac/ad5766.c
@@ -123,7 +123,7 @@ struct ad5766_state {
                u32     d32;
                u16     w16[2];
                u8      b8[4];
-       } data[3] ____cacheline_aligned;
+       } data[3] __aligned(IIO_DMA_MINALIGN);
 };
 
 struct ad5766_span_tbl {