arm64: dts: qcom: sa8295p-adp: enable PCIe

The SA8295P-ADP has up to four PCIe interfaces implemented by three or
four controllers: PCIe2A, PCIe3A/PCIe3B and PCIe4.

PCIe2 is used in x4 mode, while PCIe3 can be used in either x2 or x4
mode. Enable both PCIe3A and PCI3B in x2 mode for now.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221110103558.12690-3-johan+linaro@kernel.org

diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
index b608b82dff03c177261cb0bc14501bb26aab4d07..ff1e6a6749134f1c0b978674646d52e8103860a8 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
@@ -57,6 +57,13 @@
                        regulator-max-microvolt = <3072000>;
                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
                };
+
+               vreg_l11a: ldo11 {
+                       regulator-name = "vreg_l11a";
+                       regulator-min-microvolt = <880000>;
+                       regulator-max-microvolt = <880000>;
+                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+               };
        };
 
        pmm8540-c-regulators {
@@ -151,6 +158,76 @@
        };
 };
 
+&pcie2a {
+       perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie2a_default>;
+
+       status = "okay";
+};
+
+&pcie2a_phy {
+       vdda-phy-supply = <&vreg_l11a>;
+       vdda-pll-supply = <&vreg_l3a>;
+
+       status = "okay";
+};
+
+&pcie3a {
+       num-lanes = <2>;
+
+       perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie3a_default>;
+
+       status = "okay";
+};
+
+&pcie3a_phy {
+       vdda-phy-supply = <&vreg_l11a>;
+       vdda-pll-supply = <&vreg_l3a>;
+
+       status = "okay";
+};
+
+&pcie3b {
+       perst-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie3b_default>;
+
+       status = "okay";
+};
+
+&pcie3b_phy {
+       vdda-phy-supply = <&vreg_l11a>;
+       vdda-pll-supply = <&vreg_l3a>;
+
+       status = "okay";
+};
+
+&pcie4 {
+       perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie4_default>;
+
+       status = "okay";
+};
+
+&pcie4_phy {
+       vdda-phy-supply = <&vreg_l11a>;
+       vdda-pll-supply = <&vreg_l3a>;
+
+       status = "okay";
+};
+
 &qup2 {
        status = "okay";
 };
@@ -380,3 +457,97 @@
 };
 
 /* PINCTRL */
+
+&tlmm {
+       pcie2a_default: pcie2a-default-state {
+               clkreq-n-pins {
+                       pins = "gpio142";
+                       function = "pcie2a_clkreq";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               perst-n-pins {
+                       pins = "gpio143";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-down;
+               };
+
+               wake-n-pins {
+                       pins = "gpio145";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+       };
+
+       pcie3a_default: pcie3a-default-state {
+               clkreq-n-pins {
+                       pins = "gpio150";
+                       function = "pcie3a_clkreq";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               perst-n-pins {
+                       pins = "gpio151";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-down;
+               };
+
+               wake-n-pins {
+                       pins = "gpio56";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+       };
+
+       pcie3b_default: pcie3b-default-state {
+               clkreq-n-pins {
+                       pins = "gpio152";
+                       function = "pcie3b_clkreq";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               perst-n-pins {
+                       pins = "gpio153";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-down;
+               };
+
+               wake-n-pins {
+                       pins = "gpio130";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+       };
+
+       pcie4_default: pcie4-default-state {
+               clkreq-n-pins {
+                       pins = "gpio140";
+                       function = "pcie4_clkreq";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               perst-n-pins {
+                       pins = "gpio141";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-down;
+               };
+
+               wake-n-pins {
+                       pins = "gpio139";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+       };
+};