arm64/sysreg: add PIR*_ELx registers

Add definitions of PIR_EL1, PIR_EL12, PIRE0_EL1, PIRE0_EL12, and
PIR_EL2 registers.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20230606145859.697944-5-joey.gouly@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index e72d9aaab6b1b63461b6b061536486528c041514..11b8ef74f2396f8de4b00d2c11960f5ecf423d07 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -758,6 +758,25 @@
 #define ICH_VTR_TDS_SHIFT      19
 #define ICH_VTR_TDS_MASK       (1 << ICH_VTR_TDS_SHIFT)
 
+/*
+ * Permission Indirection Extension (PIE) permission encodings.
+ * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).
+ */
+#define PIE_NONE_O     0x0
+#define PIE_R_O                0x1
+#define PIE_X_O                0x2
+#define PIE_RX_O       0x3
+#define PIE_RW_O       0x5
+#define PIE_RWnX_O     0x6
+#define PIE_RWX_O      0x7
+#define PIE_R          0x8
+#define PIE_GCS                0x9
+#define PIE_RX         0xa
+#define PIE_RW         0xc
+#define PIE_RWX                0xe
+
+#define PIRx_ELx_PERM(idx, perm)       ((perm) << ((idx) * 4))
+
 #define ARM64_FEATURE_FIELD_BITS       4
 
 /* Defined for compatibility only, do not add new users. */

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index c11ec0a4e8f6a5a8fb8cddb13f8d957b603d57be..e08d88db700e0025724d681dcba2d3ebc249988d 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2277,6 +2277,45 @@ Field    1       PIE
 Field  0       PnCH
 EndSysreg
 
+SysregFields PIRx_ELx
+Field  63:60   Perm15
+Field  59:56   Perm14
+Field  55:52   Perm13
+Field  51:48   Perm12
+Field  47:44   Perm11
+Field  43:40   Perm10
+Field  39:36   Perm9
+Field  35:32   Perm8
+Field  31:28   Perm7
+Field  27:24   Perm6
+Field  23:20   Perm5
+Field  19:16   Perm4
+Field  15:12   Perm3
+Field  11:8    Perm2
+Field  7:4     Perm1
+Field  3:0     Perm0
+EndSysregFields
+
+Sysreg PIRE0_EL1       3       0       10      2       2
+Fields PIRx_ELx
+EndSysreg
+
+Sysreg PIRE0_EL12      3       5       10      2       2
+Fields PIRx_ELx
+EndSysreg
+
+Sysreg PIR_EL1         3       0       10      2       3
+Fields PIRx_ELx
+EndSysreg
+
+Sysreg PIR_EL12        3       5       10      2       3
+Fields PIRx_ELx
+EndSysreg
+
+Sysreg PIR_EL2         3       4       10      2       3
+Fields PIRx_ELx
+EndSysreg
+
 Sysreg LORSA_EL1       3       0       10      4       0
 Res0   63:52
 Field  51:16   SA