ip->revision);
 
                        if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
-                               if (amdgpu_sriov_vf(adev)) {
-                                       /* SR-IOV modifies each VCN’s revision (uint8)
-                                        * Bit [5:0]: original revision value
-                                        * Bit [7:6]: en/decode capability:
-                                        *     0b00 : VCN function normally
-                                        *     0b10 : encode is disabled
-                                        *     0b01 : decode is disabled
-                                        */
-                                       adev->vcn.sriov_config[adev->vcn.num_vcn_inst] =
-                                               (ip->revision & 0xc0) >> 6;
-                                       ip->revision &= ~0xc0;
-                               }
+                               /* Bit [5:0]: original revision value
+                                * Bit [7:6]: en/decode capability:
+                                *     0b00 : VCN function normally
+                                *     0b10 : encode is disabled
+                                *     0b01 : decode is disabled
+                                */
+                               adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =
+                                       ip->revision & 0xc0;
+                               ip->revision &= ~0xc0;
                                adev->vcn.num_vcn_inst++;
                        }
                        if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
        return -EINVAL;
 }
 
-
-int amdgpu_discovery_get_vcn_version(struct amdgpu_device *adev, int vcn_instance,
-                                    int *major, int *minor, int *revision)
-{
-       return amdgpu_discovery_get_ip_version(adev, VCN_HWID,
-                                              vcn_instance, major, minor, revision);
-}
-
 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
 {
        struct binary_header *bhdr;
 
 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
                                     int *major, int *minor, int *revision);
 
-int amdgpu_discovery_get_vcn_version(struct amdgpu_device *adev, int vcn_instance,
-                                    int *major, int *minor, int *revision);
 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);
 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev);
 
 
 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
 {
        bool ret = false;
+       int vcn_config = adev->vcn.vcn_config[vcn_instance];
 
-       int major;
-       int minor;
-       int revision;
-
-       /* if cannot find IP data, then this VCN does not exist */
-       if (amdgpu_discovery_get_vcn_version(adev, vcn_instance, &major, &minor, &revision) != 0)
-               return true;
-
-       if ((type == VCN_ENCODE_RING) && (revision & VCN_BLOCK_ENCODE_DISABLE_MASK)) {
+       if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) {
                ret = true;
-       } else if ((type == VCN_DECODE_RING) && (revision & VCN_BLOCK_DECODE_DISABLE_MASK)) {
+       } else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) {
                ret = true;
-       } else if ((type == VCN_UNIFIED_RING) && (revision & VCN_BLOCK_QUEUE_DISABLE_MASK)) {
+       } else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) {
                ret = true;
        }
 
 
 
        uint8_t num_vcn_inst;
        struct amdgpu_vcn_inst   inst[AMDGPU_MAX_VCN_INSTANCES];
-       uint8_t                  sriov_config[AMDGPU_MAX_VCN_INSTANCES];
+       uint8_t                  vcn_config[AMDGPU_MAX_VCN_INSTANCES];
        struct amdgpu_vcn_reg    internal;
        struct mutex             vcn_pg_lock;
        struct mutex            vcn1_jpeg1_workaround;