arm64: zynqmp: Label whole PL part as fpga_full region

This will simplify dt overlay structure for the whole PL.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 43f01dca1f780ed889a9822f31925df07f3e3355..e72343756f7b31173af8619a45ab5c0540fb5321 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -135,6 +135,14 @@
                             <1 10 0xf08>;
        };
 
+       fpga_full: fpga-full {
+               compatible = "fpga-region";
+               fpga-mgr = <&zynqmp_pcap>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+       };
+
        amba_apu: amba-apu@0 {
                compatible = "simple-bus";
                #address-cells = <2>;