drm/i915/mtl: memory latency data from LATENCY_LPX_LPY for WM

Since Xe LPD+, Memory latency data are in LATENCY_LPX_LPY registers
instead of GT driver mailbox.

v2: Use the extracted wm latency adjustment function(Matt)
v3: Use Odd/even for Latency fields(MattR)

Bspec: 64608

Cc: Matt Roper <matthew.d.roper@intel.com>
Original Author: Caz Yokoyama
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/<20220818234202.451742-15-radhakrishna.sripada@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5f140c26d79fed1e8c739c111af8f554a77ba994..f60dda8702e38a7b2f85a5314e749cf1f21cf4e1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8355,4 +8355,10 @@ enum skl_power_gate {
 #define GEN12_CULLBIT2                 _MMIO(0x7030)
 #define GEN12_STATE_ACK_DEBUG          _MMIO(0x20BC)
 
+#define MTL_LATENCY_LP0_LP1            _MMIO(0x45780)
+#define MTL_LATENCY_LP2_LP3            _MMIO(0x45784)
+#define MTL_LATENCY_LP4_LP5            _MMIO(0x45788)
+#define  MTL_LATENCY_LEVEL_EVEN_MASK   REG_GENMASK(12, 0)
+#define  MTL_LATENCY_LEVEL_ODD_MASK    REG_GENMASK(28, 16)
+
 #endif /* _I915_REG_H_ */

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a34a57708b2073eca3fdbeb67311acccee36c42f..401b4481a3aee05befe32d8b2d49017fe6799406 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2910,13 +2910,27 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
                                  u16 wm[])
 {
        struct intel_uncore *uncore = &dev_priv->uncore;
+       int max_level = ilk_wm_max_level(dev_priv);
 
-       if (DISPLAY_VER(dev_priv) >= 9) {
+       if (DISPLAY_VER(dev_priv) >= 14) {
+               u32 val;
+
+               val = intel_uncore_read(uncore, MTL_LATENCY_LP0_LP1);
+               wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
+               wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
+               val = intel_uncore_read(uncore, MTL_LATENCY_LP2_LP3);
+               wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
+               wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
+               val = intel_uncore_read(uncore, MTL_LATENCY_LP4_LP5);
+               wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
+               wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
+
+               adjust_wm_latency(dev_priv, wm, max_level, 6);
+       } else if (DISPLAY_VER(dev_priv) >= 9) {
                int read_latency = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
+               int mult = IS_DG2(dev_priv) ? 2 : 1;
                u32 val;
                int ret;
-               int max_level = ilk_wm_max_level(dev_priv);
-               int mult = IS_DG2(dev_priv) ? 2 : 1;
 
                /* read the first set of memory latencies[0:3] */
                val = 0; /* data0 to be programmed to 0 for first set */