* that the OS doesn't know about and rely on our chip
         * reset handler to handle the rest.
         */
-       ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4,
-                            ahc->bus_softc.pci_softc.devconfig);
-       ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1,
-                            ahc->bus_softc.pci_softc.command);
-       ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1,
-                            ahc->bus_softc.pci_softc.csize_lattime);
+       ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
+                            ahc->bus_softc.pci_softc.devconfig, /*bytes*/4);
+       ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
+                            ahc->bus_softc.pci_softc.command, /*bytes*/1);
+       ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
+                            ahc->bus_softc.pci_softc.csize_lattime, /*bytes*/1);
        if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
                struct  seeprom_descriptor sd;
                u_int   sxfrctl1;