clk: loongson1: Remove the outdated driver

Remove the outdated driver due to the following aspects.
- no DT support
- duplicate code across LS1B and LS1C
- does not fit into the current clock framework

Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com>
Link: https://lore.kernel.org/r/20230321111817.71756-3-keguang.zhang@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index e3ca0d058a25671f2c391a1a42748358e136256b..b7b2c6d646363fec277a4da0bed6c4583abef9c3 100644 (file)
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -93,7 +93,6 @@ obj-y                                 += imx/
 obj-y                                  += ingenic/
 obj-$(CONFIG_ARCH_K3)                  += keystone/
 obj-$(CONFIG_ARCH_KEYSTONE)            += keystone/
-obj-$(CONFIG_MACH_LOONGSON32)          += loongson1/
 obj-y                                  += mediatek/
 obj-$(CONFIG_ARCH_MESON)               += meson/
 obj-y                                  += microchip/

diff --git a/drivers/clk/loongson1/Makefile b/drivers/clk/loongson1/Makefile
deleted file mode 100644 (file)
index 251d0fe..0000000
--- a/drivers/clk/loongson1/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-obj-y                          += clk.o
-obj-$(CONFIG_LOONGSON1_LS1B)   += clk-loongson1b.o
-obj-$(CONFIG_LOONGSON1_LS1C)   += clk-loongson1c.o

diff --git a/drivers/clk/loongson1/clk-loongson1b.c b/drivers/clk/loongson1/clk-loongson1b.c
deleted file mode 100644 (file)
index 13a2ca2..0000000
--- a/drivers/clk/loongson1/clk-loongson1b.c
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (c) 2012-2016 Zhang, Keguang <keguang.zhang@gmail.com>
- */
-
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/io.h>
-#include <linux/err.h>
-
-#include <loongson1.h>
-#include "clk.h"
-
-#define OSC            (33 * 1000000)
-#define DIV_APB                2
-
-static DEFINE_SPINLOCK(_lock);
-
-static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
-                                         unsigned long parent_rate)
-{
-       u32 pll, rate;
-
-       pll = __raw_readl(LS1X_CLK_PLL_FREQ);
-       rate = 12 + (pll & GENMASK(5, 0));
-       rate *= OSC;
-       rate >>= 1;
-
-       return rate;
-}
-
-static const struct clk_ops ls1x_pll_clk_ops = {
-       .recalc_rate = ls1x_pll_recalc_rate,
-};
-
-static const char *const cpu_parents[] = { "cpu_clk_div", "osc_clk", };
-static const char *const ahb_parents[] = { "ahb_clk_div", "osc_clk", };
-static const char *const dc_parents[] = { "dc_clk_div", "osc_clk", };
-
-void __init ls1x_clk_init(void)
-{
-       struct clk_hw *hw;
-
-       hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC);
-       clk_hw_register_clkdev(hw, "osc_clk", NULL);
-
-       /* clock derived from 33 MHz OSC clk */
-       hw = clk_hw_register_pll(NULL, "pll_clk", "osc_clk",
-                                &ls1x_pll_clk_ops, 0);
-       clk_hw_register_clkdev(hw, "pll_clk", NULL);
-
-       /* clock derived from PLL clk */
-       /*                                 _____
-        *         _______________________|     |
-        * OSC ___/                       | MUX |___ CPU CLK
-        *        \___ PLL ___ CPU DIV ___|     |
-        *                                |_____|
-        */
-       hw = clk_hw_register_divider(NULL, "cpu_clk_div", "pll_clk",
-                                  CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
-                                  DIV_CPU_SHIFT, DIV_CPU_WIDTH,
-                                  CLK_DIVIDER_ONE_BASED |
-                                  CLK_DIVIDER_ROUND_CLOSEST, &_lock);
-       clk_hw_register_clkdev(hw, "cpu_clk_div", NULL);
-       hw = clk_hw_register_mux(NULL, "cpu_clk", cpu_parents,
-                              ARRAY_SIZE(cpu_parents),
-                              CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
-                              BYPASS_CPU_SHIFT, BYPASS_CPU_WIDTH, 0, &_lock);
-       clk_hw_register_clkdev(hw, "cpu_clk", NULL);
-
-       /*                                 _____
-        *         _______________________|     |
-        * OSC ___/                       | MUX |___ DC  CLK
-        *        \___ PLL ___ DC  DIV ___|     |
-        *                                |_____|
-        */
-       hw = clk_hw_register_divider(NULL, "dc_clk_div", "pll_clk",
-                                  0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
-                                  DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
-       clk_hw_register_clkdev(hw, "dc_clk_div", NULL);
-       hw = clk_hw_register_mux(NULL, "dc_clk", dc_parents,
-                              ARRAY_SIZE(dc_parents),
-                              CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
-                              BYPASS_DC_SHIFT, BYPASS_DC_WIDTH, 0, &_lock);
-       clk_hw_register_clkdev(hw, "dc_clk", NULL);
-
-       /*                                 _____
-        *         _______________________|     |
-        * OSC ___/                       | MUX |___ DDR CLK
-        *        \___ PLL ___ DDR DIV ___|     |
-        *                                |_____|
-        */
-       hw = clk_hw_register_divider(NULL, "ahb_clk_div", "pll_clk",
-                                  0, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
-                                  DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED,
-                                  &_lock);
-       clk_hw_register_clkdev(hw, "ahb_clk_div", NULL);
-       hw = clk_hw_register_mux(NULL, "ahb_clk", ahb_parents,
-                              ARRAY_SIZE(ahb_parents),
-                              CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
-                              BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock);
-       clk_hw_register_clkdev(hw, "ahb_clk", NULL);
-       clk_hw_register_clkdev(hw, "ls1x-dma", NULL);
-       clk_hw_register_clkdev(hw, "stmmaceth", NULL);
-
-       /* clock derived from AHB clk */
-       /* APB clk is always half of the AHB clk */
-       hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
-                                       DIV_APB);
-       clk_hw_register_clkdev(hw, "apb_clk", NULL);
-       clk_hw_register_clkdev(hw, "ls1x-ac97", NULL);
-       clk_hw_register_clkdev(hw, "ls1x-i2c", NULL);
-       clk_hw_register_clkdev(hw, "ls1x-nand", NULL);
-       clk_hw_register_clkdev(hw, "ls1x-pwmtimer", NULL);
-       clk_hw_register_clkdev(hw, "ls1x-spi", NULL);
-       clk_hw_register_clkdev(hw, "ls1x-wdt", NULL);
-       clk_hw_register_clkdev(hw, "serial8250", NULL);
-}

diff --git a/drivers/clk/loongson1/clk-loongson1c.c b/drivers/clk/loongson1/clk-loongson1c.c
deleted file mode 100644 (file)
index 1ebf740..0000000
--- a/drivers/clk/loongson1/clk-loongson1c.c
+++ /dev/null
@@ -1,95 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (c) 2016 Yang Ling <gnaygnil@gmail.com>
- */
-
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/io.h>
-
-#include <loongson1.h>
-#include "clk.h"
-
-#define OSC            (24 * 1000000)
-#define DIV_APB                1
-
-static DEFINE_SPINLOCK(_lock);
-
-static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
-                                         unsigned long parent_rate)
-{
-       u32 pll, rate;
-
-       pll = __raw_readl(LS1X_CLK_PLL_FREQ);
-       rate = ((pll >> 8) & 0xff) + ((pll >> 16) & 0xff);
-       rate *= OSC;
-       rate >>= 2;
-
-       return rate;
-}
-
-static const struct clk_ops ls1x_pll_clk_ops = {
-       .recalc_rate = ls1x_pll_recalc_rate,
-};
-
-static const struct clk_div_table ahb_div_table[] = {
-       [0] = { .val = 0, .div = 2 },
-       [1] = { .val = 1, .div = 4 },
-       [2] = { .val = 2, .div = 3 },
-       [3] = { .val = 3, .div = 3 },
-       [4] = { /* sentinel */ }
-};
-
-void __init ls1x_clk_init(void)
-{
-       struct clk_hw *hw;
-
-       hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC);
-       clk_hw_register_clkdev(hw, "osc_clk", NULL);
-
-       /* clock derived from 24 MHz OSC clk */
-       hw = clk_hw_register_pll(NULL, "pll_clk", "osc_clk",
-                               &ls1x_pll_clk_ops, 0);
-       clk_hw_register_clkdev(hw, "pll_clk", NULL);
-
-       hw = clk_hw_register_divider(NULL, "cpu_clk_div", "pll_clk",
-                                  CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
-                                  DIV_CPU_SHIFT, DIV_CPU_WIDTH,
-                                  CLK_DIVIDER_ONE_BASED |
-                                  CLK_DIVIDER_ROUND_CLOSEST, &_lock);
-       clk_hw_register_clkdev(hw, "cpu_clk_div", NULL);
-       hw = clk_hw_register_fixed_factor(NULL, "cpu_clk", "cpu_clk_div",
-                                       0, 1, 1);
-       clk_hw_register_clkdev(hw, "cpu_clk", NULL);
-
-       hw = clk_hw_register_divider(NULL, "dc_clk_div", "pll_clk",
-                                  0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
-                                  DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
-       clk_hw_register_clkdev(hw, "dc_clk_div", NULL);
-       hw = clk_hw_register_fixed_factor(NULL, "dc_clk", "dc_clk_div",
-                                       0, 1, 1);
-       clk_hw_register_clkdev(hw, "dc_clk", NULL);
-
-       hw = clk_hw_register_divider_table(NULL, "ahb_clk_div", "cpu_clk_div",
-                               0, LS1X_CLK_PLL_FREQ, DIV_DDR_SHIFT,
-                               DIV_DDR_WIDTH, CLK_DIVIDER_ALLOW_ZERO,
-                               ahb_div_table, &_lock);
-       clk_hw_register_clkdev(hw, "ahb_clk_div", NULL);
-       hw = clk_hw_register_fixed_factor(NULL, "ahb_clk", "ahb_clk_div",
-                                       0, 1, 1);
-       clk_hw_register_clkdev(hw, "ahb_clk", NULL);
-       clk_hw_register_clkdev(hw, "ls1x-dma", NULL);
-       clk_hw_register_clkdev(hw, "stmmaceth", NULL);
-
-       /* clock derived from AHB clk */
-       hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
-                                       DIV_APB);
-       clk_hw_register_clkdev(hw, "apb_clk", NULL);
-       clk_hw_register_clkdev(hw, "ls1x-ac97", NULL);
-       clk_hw_register_clkdev(hw, "ls1x-i2c", NULL);
-       clk_hw_register_clkdev(hw, "ls1x-nand", NULL);
-       clk_hw_register_clkdev(hw, "ls1x-pwmtimer", NULL);
-       clk_hw_register_clkdev(hw, "ls1x-spi", NULL);
-       clk_hw_register_clkdev(hw, "ls1x-wdt", NULL);
-       clk_hw_register_clkdev(hw, "serial8250", NULL);
-}

diff --git a/drivers/clk/loongson1/clk.c b/drivers/clk/loongson1/clk.c
deleted file mode 100644 (file)
index f336a31..0000000
--- a/drivers/clk/loongson1/clk.c
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (c) 2012-2016 Zhang, Keguang <keguang.zhang@gmail.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/slab.h>
-
-#include "clk.h"
-
-struct clk_hw *__init clk_hw_register_pll(struct device *dev,
-                                         const char *name,
-                                         const char *parent_name,
-                                         const struct clk_ops *ops,
-                                         unsigned long flags)
-{
-       int ret;
-       struct clk_hw *hw;
-       struct clk_init_data init;
-
-       /* allocate the divider */
-       hw = kzalloc(sizeof(*hw), GFP_KERNEL);
-       if (!hw)
-               return ERR_PTR(-ENOMEM);
-
-       init.name = name;
-       init.ops = ops;
-       init.flags = flags;
-       init.parent_names = parent_name ? &parent_name : NULL;
-       init.num_parents = parent_name ? 1 : 0;
-       hw->init = &init;
-
-       /* register the clock */
-       ret = clk_hw_register(dev, hw);
-       if (ret) {
-               kfree(hw);
-               hw = ERR_PTR(ret);
-       }
-
-       return hw;
-}

diff --git a/drivers/clk/loongson1/clk.h b/drivers/clk/loongson1/clk.h
deleted file mode 100644 (file)
index 1246423..0000000
--- a/drivers/clk/loongson1/clk.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (c) 2012-2016 Zhang, Keguang <keguang.zhang@gmail.com>
- */
-
-#ifndef __LOONGSON1_CLK_H
-#define __LOONGSON1_CLK_H
-
-struct clk_hw *clk_hw_register_pll(struct device *dev,
-                                  const char *name,
-                                  const char *parent_name,
-                                  const struct clk_ops *ops,
-                                  unsigned long flags);
-
-#endif /* __LOONGSON1_CLK_H */