PCI: dwc: histb: Use pci_ops for root config space accessors

Now that DWC drivers can setup their own pci_ops for the root and child
buses, convert the HiSilicon histb driver to use the standard pci_ops
for root bus config accesses.

Link: https://lore.kernel.org/r/20200821035420.380495-12-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controller/dwc/pcie-histb.c
index 2a28357460775fc7171569fa999c8615fed72836..af1deae2b15de186676fa65a2ac0bd718f8df765 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-histb.c
+++ b/drivers/pci/controller/dwc/pcie-histb.c
@@ -122,32 +122,37 @@ static void histb_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
        histb_pcie_dbi_w_mode(&pci->pp, false);
 }
 
-static int histb_pcie_rd_own_conf(struct pcie_port *pp, int where,
-                                 int size, u32 *val)
+static int histb_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
+                                 int where, int size, u32 *val)
 {
-       struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-       int ret;
+       struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
 
-       histb_pcie_dbi_r_mode(pp, true);
-       ret = dw_pcie_read(pci->dbi_base + where, size, val);
-       histb_pcie_dbi_r_mode(pp, false);
+       if (PCI_SLOT(devfn)) {
+               *val = ~0;
+               return PCIBIOS_DEVICE_NOT_FOUND;
+       }
 
-       return ret;
+       *val = dw_pcie_read_dbi(pci, where, size);
+       return PCIBIOS_SUCCESSFUL;
 }
 
-static int histb_pcie_wr_own_conf(struct pcie_port *pp, int where,
-                                 int size, u32 val)
+static int histb_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn,
+                                 int where, int size, u32 val)
 {
-       struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-       int ret;
+       struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
 
-       histb_pcie_dbi_w_mode(pp, true);
-       ret = dw_pcie_write(pci->dbi_base + where, size, val);
-       histb_pcie_dbi_w_mode(pp, false);
+       if (PCI_SLOT(devfn))
+               return PCIBIOS_DEVICE_NOT_FOUND;
 
-       return ret;
+       dw_pcie_write_dbi(pci, where, size, val);
+       return PCIBIOS_SUCCESSFUL;
 }
 
+static struct pci_ops histb_pci_ops = {
+       .read = histb_pcie_rd_own_conf,
+       .write = histb_pcie_wr_own_conf,
+};
+
 static int histb_pcie_link_up(struct dw_pcie *pci)
 {
        struct histb_pcie *hipcie = to_histb_pcie(pci);
@@ -194,6 +199,8 @@ static int histb_pcie_establish_link(struct pcie_port *pp)
 
 static int histb_pcie_host_init(struct pcie_port *pp)
 {
+       pp->bridge->ops = &histb_pci_ops;
+
        histb_pcie_establish_link(pp);
 
        if (IS_ENABLED(CONFIG_PCI_MSI))
@@ -203,8 +210,6 @@ static int histb_pcie_host_init(struct pcie_port *pp)
 }
 
 static const struct dw_pcie_host_ops histb_pcie_host_ops = {
-       .rd_own_conf = histb_pcie_rd_own_conf,
-       .wr_own_conf = histb_pcie_wr_own_conf,
        .host_init = histb_pcie_host_init,
 };