drm/amd/display: add additional refresh rate conditions for SubVP cases

[Why]
Want to further constrain these refresh rate conditions for SubVP:
- SubVP + SubVP: either both <= 120Hz or both between 120-165Hz
- SubVP + DRR: SubVP <= 120Hz
- SubVP + VBlank: SubVP <= 120Hz

[How]
Add constraints in subvp_subvp_admissable(),
dcn32_subvp_drr_admissable() and dcn32_subvp_vblank_admissable()

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Samson Tam <samson.tam@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index 5be242a1b82c4c3768505c034167140f458a6497..db9c55a09d9f4f62c75d5130fa1416fc985288ca 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -641,6 +641,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)
        uint8_t non_subvp_pipes = 0;
        bool drr_pipe_found = false;
        bool drr_psr_capable = false;
+       uint64_t refresh_rate = 0;
 
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
                struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
@@ -649,8 +650,14 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)
                        continue;
 
                if (pipe->plane_state && !pipe->top_pipe) {
-                       if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
+                       if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
                                subvp_count++;
+
+                               refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
+                                       pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);
+                               refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
+                               refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
+                       }
                        if (pipe->stream->mall_stream_config.type == SUBVP_NONE) {
                                non_subvp_pipes++;
                                drr_psr_capable = (drr_psr_capable || dcn32_is_psr_capable(pipe));
@@ -662,7 +669,8 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)
                }
        }
 
-       if (subvp_count == 1 && non_subvp_pipes == 1 && drr_pipe_found && !drr_psr_capable)
+       if (subvp_count == 1 && non_subvp_pipes == 1 && drr_pipe_found && !drr_psr_capable &&
+               ((uint32_t)refresh_rate < 120))
                result = true;
 
        return result;
@@ -693,6 +701,7 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int
        bool drr_pipe_found = false;
        struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
        bool vblank_psr_capable = false;
+       uint64_t refresh_rate = 0;
 
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
                struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
@@ -701,8 +710,14 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int
                        continue;
 
                if (pipe->plane_state && !pipe->top_pipe) {
-                       if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
+                       if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
                                subvp_count++;
+
+                               refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
+                                       pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);
+                               refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
+                               refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
+                       }
                        if (pipe->stream->mall_stream_config.type == SUBVP_NONE) {
                                non_subvp_pipes++;
                                vblank_psr_capable = (vblank_psr_capable || dcn32_is_psr_capable(pipe));
@@ -715,7 +730,8 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int
        }
 
        if (subvp_count == 1 && non_subvp_pipes == 1 && !drr_pipe_found && !vblank_psr_capable &&
-                       vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp)
+               ((uint32_t)refresh_rate < 120) &&
+               vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp)
                result = true;
 
        return result;

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index a950348017128bcead306d0b6f7de9b3b4517ad3..0e2f25985378548682771e30320c49865f1aea20 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1040,7 +1040,7 @@ static bool subvp_subvp_admissable(struct dc *dc,
        uint32_t i;
        uint8_t subvp_count = 0;
        uint32_t min_refresh = subvp_high_refresh_list.min_refresh, max_refresh = 0;
-       uint32_t refresh_rate = 0;
+       uint64_t refresh_rate = 0;
 
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
                struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
@@ -1050,19 +1050,21 @@ static bool subvp_subvp_admissable(struct dc *dc,
 
                if (pipe->plane_state && !pipe->top_pipe &&
                                pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
-                       refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
-                                       pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
-                                       / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
-                       if (refresh_rate < min_refresh)
-                               min_refresh = refresh_rate;
-                       if (refresh_rate > max_refresh)
-                               max_refresh = refresh_rate;
+                       refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
+                               pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);
+                       refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
+                       refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
+
+                       if ((uint32_t)refresh_rate < min_refresh)
+                               min_refresh = (uint32_t)refresh_rate;
+                       if ((uint32_t)refresh_rate > max_refresh)
+                               max_refresh = (uint32_t)refresh_rate;
                        subvp_count++;
                }
        }
 
        if (subvp_count == 2 && ((min_refresh < 120 && max_refresh < 120) ||
-                       (min_refresh >= 120 && max_refresh >= 120)))
+               (min_refresh >= 120 && max_refresh <= 165)))
                result = true;
 
        return result;