PCI: cadence: Allow pci_host_bridge to have custom pci_ops

Certain platforms like TI's J721E allows only 32-bit configuration
space access. In such cases pci_generic_config_read and
pci_generic_config_write cannot be used. Add support in Cadence core
to let pci_host_bridge have custom pci_ops.

Link: https://lore.kernel.org/r/20200722110317.4744-7-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 4e650c7a00323d5390df9d5c0b713f83104e9904..f889914563fe85fadf1c341c4d8cacae0e5273c4 100644 (file)
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -506,7 +506,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
        list_splice_init(&resources, &bridge->windows);
        bridge->dev.parent = dev;
        bridge->busnr = pcie->bus;
-       bridge->ops = &cdns_pcie_host_ops;
+       if (!bridge->ops)
+               bridge->ops = &cdns_pcie_host_ops;
        bridge->map_irq = of_irq_parse_and_map_pci;
        bridge->swizzle_irq = pci_common_swizzle;